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Part Manufacturer Description Datasheet Download Buy Part
LTC1040MJ Linear Technology IC DUAL COMPARATOR, 750 uV OFFSET-MAX, 80000 ns RESPONSE TIME, CDIP18, 0.300 INCH, HERMETIC SEALED, CERDIP-18, Comparator
LTC1040CJ Linear Technology IC DUAL COMPARATOR, 750 uV OFFSET-MAX, 80000 ns RESPONSE TIME, CDIP18, 0.300 INCH, HERMETIC SEALED, CERDIP-18, Comparator
LT1078S16 Linear Technology IC DUAL OP-AMP, 750 uV OFFSET-MAX, 0.2 MHz BAND WIDTH, PDSO16, PLASTIC, SOL-16, Operational Amplifier
LT1112CS8 Linear Technology IC DUAL OP-AMP, 750 uV OFFSET-MAX, PDSO8, 0.150 INCH, PLASTIC, SO-8, Operational Amplifier
LT1079S Linear Technology IC QUAD OP-AMP, 750 uV OFFSET-MAX, 0.2 MHz BAND WIDTH, PDSO16, PLASTIC, SOL-16, Operational Amplifier
LT1055CH#PBF Linear Technology IC OP-AMP, 750 uV OFFSET-MAX, 4.5 MHz BAND WIDTH, MBCY8, LEAD FREE, METAL CAN, TO-5, 8 PIN, Operational Amplifier

MIL-STD-750 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
MIL-STD-750

Abstract: MIL-STD-750 2072
Text: = 25°C for BVDSS, VGSlh, IDSS, IGSS, VSD, RDSon 100% Visual Inspection i.a.w. method 2072 of MIL-STD-750 , ) i.a.w. method 5001 of MIL-STD-750 , including SEM Unclamped Inductive Switching (IAS) i.a.w. method 3470 of MIL-STD-750 at VGSpcak= 15 V, L= 100|xH, IAS= 132 A Gate Stress Test for 250 |is at VGS= 30 Vdc. Safe Operating Area i.a.w. m ethod 3474 of MIL-STD-750 at VDS= 160 V, ID= 2.8 A for 10 ms High Temperature Gate Bias i.a.w. method 1042 cond.B of MIL-STD-750 : 48 hrs at T ambicnt= 150°C, Drain shorted to


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PDF MX043J MX043G FSC260R 1012RAD MX043J) MX043G) 1042B MIL-STD-750 MIL-STD-750 MIL-STD-750 2072
Not Available

Abstract: No abstract text available
Text: o f MIL-STD-750 DIE ELEMENT EVALUATION a. b. Wafer Lot Evaluation Testing (WLAT) i.a.w. method 5001 of MIL-STD-750 , including SEM Unclamped Inductive Switching (IA i.a.w. method 3470 o f MIL-STD-750 at VGSpeak= 15 V, L= 100|xH, IA 132 A S) S= C. Gate Stress Test for 250 |^s at VGS= 30 Vdc. d. Safe Operating Area i.a.w. method 3474 o f MIL-STD-750 at VDS= 160 V, ID= 2.8 A for 10 ms e. High Temperature Gate Bias i.a.w. method 1042 cond.B o f MIL-STD-750 : 48 hrs at T am bient= 150Â


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PDF MX043J MX043G FSC260R MX043J) MIL-STD-750 1042B MIL-STD-750
Not Available

Abstract: No abstract text available
Text: €¢ 1 Visual Inspection MIL-STD-750 – Method 2073 2 Pre-Cap Inspection MIL-STD-750 – Method 2070 • • 3 High-Temperature Bake MIL-STD-750 – Method 1032 t = 340 Hrs. • • • 4 Temperature Cycling MIL-STD-750 – Method 1051 20 Cycles. Condition C • • • 5 Thermal Impedance MIL-STD-750 – Method 3101 • • • 6 Constant Acceleration MIL-STD-750 – Method 2006 20,000Gs Min., Y1 Axis Only • â


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PDF BRO383-11B
1998 - MIL-STD-750 2072

Abstract: MIL-STD-750 MIL-STD-750 3470 FSC260R ID100 MX043G MX043J
Text: Inspection i.a.w. method 2072 of MIL-STD-750 a. b. c. d. e. Wafer Lot Evaluation Testing (WLAT) i.a.w. method 5001 of MIL-STD-750 , including SEM Unclamped Inductive Switching (IAS) i.a.w. method 3470 of MIL-STD-750 at VGS peak= 15 V, L= 100µH, I AS= 132 A Gate Stress Test for 250 µs at VGS= 30 Vdc. Safe Operating Area i.a.w. method 3474 of MIL-STD-750 at VDS= 160 V, ID= 2.8 A for 10 ms High Temperature Gate Bias i.a.w. method 1042 cond.B of MIL-STD-750 : 48 hrs at T ambient= 150° Drain shorted to


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PDF MX043J MX043G FSC260R MX043J) MX043G) MIL-STD-750 1042B MIL-STD-750 MIL-STD-750 2072 MIL-STD-750 3470 ID100 MX043G MX043J
MIL-STD-750

Abstract: MIL-STD-750C
Text: WITH COOL 168/1000HRS MIL-STD-750C METHOD 1027.1 MIL-STD-750 METHOD 1038. A I MIL-STD-750 METHOD , -202 METHOD 208 MIL-STD-750 METHOD 2036.3 MIL-STD-750 METHOD 2036.3 1 SOLDERABILITY 230 ± 5 D C 5 , 125 °C FOR BRIDGE -55 °C 1 PULSE MIL-STD-750 METHOD 4066.2 8 HIGH TEMPERATURE STORAGE LIFE LOW TEMPERATURE STORAGE LIFE 168/1000HRS MIL-STD-750 METHOD 1031.4 I EC-68-2-1 TEST A: COLD 9 , /IOOOHRS MIL-STD-750 METHOD 1021.1 M IL- S- 19500 APPENDIX C MIL-STD-750 METHOD 1056.1 MIL-STD-750


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PDF MIL-STD-202 MIL-STD-750 90-DEGREE 168/1000HRS MIL-STD-750C
2002 - Reliability

Abstract: No abstract text available
Text: inspection MIL-STD-750 - Method 2073 X 2 High temperature bake MIL-STD-750 - Method 1032 X 3 Temperature cycling MIL-STD-750 - Method 1051 Condition C X 4 Constant acceleration MIL-STD-750 - Method 2006 20,000G's min., Y1 axis only X 5 Initial electrical test , Interim electricals Read and record X 8 Burn-in Condition B, t = 96 hrs X MIL-STD-750 - Method 1038 MIL-STD-750 - Method 1038 9 Final electrical test Read and record X 10


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2002 - MIL-STD-750

Abstract: 4011 high temperature reverse bias
Text: (non-operating life/ stabilization bake MIL-STD-750 ) Method 1032 48 hrs @ +175°C 2) Temperature Cycling MIL-STD-750 Method 1051 Condition C 20 Cycles -65°C to +175°C 15 min. extremes No dwell , Leakage Current Method 1038 Condition A MIL-STD-750 5) Final Electrical MIL-STD-750 96 , . 1) High Temperature Life (non-operating life/ stabilization bake MIL-STD-750 ) Method 1032 , VRWM MIL-STD-750 5) Final Electrical MIL-STD-750 Method 4011 Method 4016 Method 4021


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PDF MIL-PRF-19500 MIL-STD-750 MIL-STD-750 4011 high temperature reverse bias
2000 - ingot

Abstract: MIL-STD-750
Text: MIL-STD-750 ) Method 1032 48 hrs @ +175°C 2) Temperature Cycling MIL-STD-750 Method 1051 , Condition A MIL-STD-750 5) Final Electrical MIL-STD-750 96 hrs min. @ TA=150°C and min , Temperature Life (non-operating life/ stabilization bake MIL-STD-750 ) Method 1032 24 hrs @ 125°C 2 , Leakage Current Method 1038 Condition A 24 hrs @ +125°C at 80% of VRWM MIL-STD-750 5) Final Electrical MIL-STD-750 Method 4011 Method 4016 Method 4021 Forward Voltage Drop Leakage Current


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PDF MIL-STD-750 ingot MIL-STD-750
TRANSISTOR BL s93

Abstract: K1007
Text: * lg 0 7 n ICB0 io rx tUL 1 ; Snitter Cut-Off Current MIL-STD-750 Method 3061 or , ,1IL-STD-75Ó Method 3026 or K1007/3 7.2.3. MIL-STD-750 Method 3206 or K1007/3 Ic = 25mA, IB = 0 , *n«JCirouit Output Capacitano«* MIL-STD-750 MethoJ ïp&r K1007/3 7 «4*9» Tra -íoroltáa IJg - 0 Ob , . Dimensions MIL-STD-750 Method 2066 or K1007/3 Para. 5>1*2 ) | In aooordanoe with Fig. 2 Page 8 ; Sub-Group 2 Solderability , · 4 mil-std-750 Method 2026 or n 007/3 Para. 5.13. . 84 j { !.


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2n7507

Abstract: IRF5NJ3315 BL 15 SMD
Text: -19500 - Semiconductor Devices, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 , with MIL-PRF-19500, MIL-STD-750 , and herein. Where a choice of lead finish is desired, it shall be , ) (3) (4) Method 3470 of MIL-STD-750 (see 4.3.2) optional Method 3470 of MIL-STD-750 (see 4.3.2) optional (3) 3c Method 3161 of MIL-STD-750 (see 4.3.3) Method 3161 of MIL-STD-750 (see 4.3.3) 9 IGSSF1, IGSSR1, IDSS1, subgroup 2 of table I herein Not applicable 10 Method 1042 of MIL-STD-750


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PDF MIL-PRF-19500/750 2N7507U3, MIL-PRF-19500. O-276AA 2N7507U3 IRF5NJ3315 2n7507 IRF5NJ3315 BL 15 SMD
MIL-STD-750

Abstract: CK6001 UPS835LE3 1038A plaskon UPS1040E3 UPS840e3 SEC77 qualify JESD22-A-102-C
Text: HTRB (Life Test) MIL-STD-750 , Method 1038A Ta = 125 deg C VR = 32 Vdc Duration = 1000 Hours , hours 77 Units 0 0% Completed Temperature Cycling MIL-STD-750 , Method 1051 Temp , MIL-STD-750 , Method 2006 Y1 Direction 15,000 G's Minimum 77 Units 0 0% Completed Variable Frequency Vibration MIL-STD-750 , Method 2056 50 G's Minimum 100Hz to 2kHz 77 Units 0 0% Completed Mechanical Shock MIL-STD-750 , Method 2016 Non-Operating , 1500 G


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PDF CK6001) MIL-STD-750, JESD22-A102-C MSC/PCN-0002 UPS340e3 UPS835Le3 UPS360e3 UPS840e3 MIL-STD-750 CK6001 UPS835LE3 1038A plaskon UPS1040E3 UPS840e3 SEC77 qualify JESD22-A-102-C
2013 - 2N7423

Abstract: 2N7422 662F 2N7423U
Text: . DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test Methods for Semiconductor Devices. * (Copies of , copper tungsten. Lead finish shall be solderable as defined in MIL-PRF-19500, MIL-STD-750 , and herein , MIL-STD-750 that were used to qualify the device for inclusion into section 6 of the slash sheet , stress test (see 4.3.1) (3) Method 3470 of MIL-STD-750 , EAS test (see 4.3.2) Method 3470 of MIL-STD-750 , EAS test (see 4.3.2) (3) 3c Method 3161 of MIL-STD-750 , thermal impedance (see 4.3.3


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PDF MIL-PRF-19500/662F MIL-PRF-19500/662E 2N7422, 2N7422U, 2N7423, 2N7423U, MIL-PRF-19500. 2N7423 2N7422 662F 2N7423U
1998 - MIL-STD-750

Abstract: 100C
Text: 7.2.2 12 METHODS PER MIL-STD-750 UNLESS OTHERWISE SPECIFIED SUMMARY OF TEST RESULTS GROUP B , 12 0 0 12 0 0 METHODS PER MIL-STD-750 UNLESS OTHERWISE SPECIFIED SUMMARY OF , Ton = Toff IF/Io = 2.0 Amps COMMENTS: Upr5ge~2 METHODS PER MIL-STD-750 UNLESS OTHERWISE , COMMENTS: Upr5ge~2 0 METHODS PER MIL-STD-750 UNLESS OTHERWISE SPECIFIED SUMMARY OF TEST RESULTS , Autoclave TA = 121C/15psi t=96 hrs COMMENTS: Upr5ge~2 7.2.8 METHODS PER MIL-STD-750 UNLESS


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PDF 100nA 300nA 975mV 600nA MIL-STD-750 to-220 1000G 100C
2013 - 2N7464T2

Abstract: No abstract text available
Text: Semiconductor Devices, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test , ) herein. 3.4.1 Lead finish. Lead finish shall be solderable in accordance with MIL-PRF-19500, MIL-STD-750 , test conditions from section 5 of method 1080 of MIL-STD-750 that were used to qualify the device for , level (1) (2) (3) Method 3470 of MIL-STD-750 , EAS (see 4.3.1) (3) Gate stress test (see 4.3.3) Gate stress test (see 4.3.3) (3) 3c Method 3161 of MIL-STD-750 , thermal impedance (see


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PDF MIL-PRF-19500/675E MIL-PRF-19500/675D 2N7463T2, 2N7464T2, 2N7463U5 2N7464U5 MIL-PRF-19500. 2N7464T2
2013 - 2N7470

Abstract: JANS 2N7470T1
Text: , General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test Methods for , 3.4.1 Lead formation and finish. Lead finish shall be solderable in accordance with MIL-STD-750 , MIL-PRF , ) (3) Method 3470 of MIL-STD-750 , EAS (see 4.3.2) Method 3470 of MIL-STD-750 , EAS (see 4.3.2) (3) 3c Method 3161 of MIL-STD-750 , thermal impedance, (see 4.3.3) Method 3161 of MIL-STD-750 , applicable 10 Method 1042 of MIL-STD-750 , test condition B Method 1042 of MIL-STD-750 , test


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PDF MIL-PRF-19500/698E MIL-PRF-19500/698D 2N7470T1 2N7471T1, MIL-PRF-19500. 2N7470 JANS 2N7470T1
2013 - Not Available

Abstract: No abstract text available
Text: . DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test Methods for Semiconductor Devices. * (Copies of , . Terminal finish shall be solderable as defined in MIL-PRF-19500, MIL-STD-750 , and herein. Where a choice , conditions from section 5 of method 1080 of MIL-STD-750 that were used to qualify the device for inclusion , ) Gate stress test (see 4.3.1) Gate stress test (see 4.3.1) (3) Method 3470 of MIL-STD-750 , EAS test (see 4.3.2) Method 3470 of MIL-STD-750 , EAS test (see 4.3.2) (3) 3c Method 3161 of


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PDF MIL-PRF-19500/664D MIL-PRF-19500/664C 2N7431U, 2N7432U, 2N7433U, MIL-PRF-19500.
2013 - Not Available

Abstract: No abstract text available
Text: section 4 of MIL-STD-750. 8 MIL-PRF-19500/663F TABLE I. Group A inspection. MIL-STD-750 , . DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 * - Test Methods for Semiconductor Devices. (Copies of , with MIL-STD-750 , MIL-PRF-19500 and herein. Where a choice of finish is desired, it shall be specified , MIL-STD-750 that were used to qualify the device for inclusion into section 6 of the slash sheet , ) Gate stress test (see 4.3.1) (3) Method 3470 of MIL-STD-750 , EAS (see 4.3.2) Method 3470 of


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PDF MIL-PRF-19500/663F MIL-PRF-19500/663E 2N7431, 2N7432, 2N7433, MIL-PRF-19500.
2009 - 2N6903 JANTX

Abstract: 2N6903
Text: -19500 - Semiconductor Devices, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 , accordance with MIL-PRF-19500, MIL-STD-750 , and herein. Where a choice of lead finish is desired, it shall , ) (3) Method 3470 of MIL-STD-750 , (see 4.3.2) optional Method 3470 of MIL-STD-750 , (see 4.3.2) optional (3) 3c Method 3161 of MIL-STD-750 , (see 4.3.3) Method 3161 of MIL-STD-750 , (see 4.3.3 , MIL-STD-750 , test condition B Method 1042 of MIL-STD-750 , test condition B 11 Subgroup 2 of


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PDF MIL-PRF-19500/570D MIL-PRF-19500/570C 2N6901 2N6903, MIL-PRF-19500. 2N6903 JANTX 2N6903
Krypton-85

Abstract: 2N1484 2N1486 2N1483 2N1485 2N1485 JANTX transistor 2n1485
Text: and Electrical Component Parts. MIL-STD-750 - Test Methods for Semiconductor Devices. (Copies of , 4 of MIL-STD-750. 4.4.2 Time limit for end points. End point tests for qualification and quality , . TABLE I. Group A inspection MIL-STD-750 LTPD Symbol Limits Examination or test Method Details , -19500/ 180D TABLE I. Group A inspection - Continued MIL-STD-750 LTPD Symbol Limits Examination or test , -19500/ 180D TABLE I. Group A inspection - Continued Examination or test MIL-STD-750 LTPD Symbol Limits


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PDF MIL-S-19500/180D MIL-S-19500/180C 2N1483, TX2N1483, 2N1484, TX2N1484 2N1485, TX2N1485, 2N1486, TX2N1486 Krypton-85 2N1484 2N1486 2N1483 2N1485 2N1485 JANTX transistor 2n1485
2N7509

Abstract: transistor 1020 2N7510 FSGJ264 FSGJ160
Text: -19500 - Semiconductor Devices, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 , -19500, MIL-STD-750 , and herein. Where a choice of lead finish is desired, it shall be specified in the , ) (3) Method 3470 of MIL-STD-750 , (see 4.3.2) Method 3470 of MIL-STD-750 , (see 4.3.2) (3) 3c Method 3161 of MIL-STD-750 , (see 4.3.3) Method 3161 of MIL-STD-750 , (see 4.3.3) 7 Optional , of table I herein 10 Method 1042 of MIL-STD-750 , test condition B Method 1042 of MIL-STD-750


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PDF MIL-PRF-19500/687B MIL-PRF-19500/687A 2N7509, 2N7510, 2N7511, MIL-PRF-19500. 2N7509 transistor 1020 2N7510 FSGJ264 FSGJ160
SHARP IR3

Abstract: 1N5621 1N5619 1N5617 1N5615 1N4948 1N4947 1N4946 1N4944 1N4942
Text: . DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test Methods for Semiconductor Devices. * (Copies of , ) = 1 A dc. TA = +55°C maximum. Test conditions in accordance with method 1038 of MIL-STD-750 , condition B. Use method 3100 of MIL-STD-750 to measure TJ. Adjust IO or TA to achieve the required TJ. TJ = , in section 4 of MIL-STD-750. 4.5.2 Inspection conditions. Unless otherwise specified, all , method 3100 of MIL-STD-750 to measure TJ. 4.5.3.2 Mounting conditions. At the option of the manufacturer


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PDF MIL-PRF-19500/359K MIL-PRF-19500/359J 1N4942, 1N4944, 1N4946, 1N4947, 1N4948, 1N5615, 1N5617, 1N5619, SHARP IR3 1N5621 1N5619 1N5617 1N5615 1N4948 1N4947 1N4946 1N4944 1N4942
2013 - 2N7380

Abstract: No abstract text available
Text: ) Gate stress test (see 4.3.1) (3) Method 3470 of MIL-STD-750. (see 4.3.2) Method 3470 of MIL-STD-750. (see 4.3.2) (3) 3c Method 3161 of MIL-STD-750 (see 4.3.3) Method 3161 of MIL-STD-750 , -19500 - Semiconductor Devices, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 , finish shall be solderable in accordance with MIL-PRF-19500, MIL-STD-750 , and herein. Where a choice of , MIL-STD-750 that were used to qualify the device for inclusion into section 6 of the slash sheet


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PDF MIL-PRF-19500/614H MIL-PRF-19500/614G 2N7380 2N7381, MIL-PRF-19500.
2013 - Not Available

Abstract: No abstract text available
Text: MIL-STD-750. 8 MIL-PRF-19500/697E TABLE I. Group A inspection. Inspection 1/ MIL-STD-750 , . DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test Methods for Semiconductor Devices. * (Copies of , 3.4.1 Lead formation and finish. Lead finish shall be solderable in accordance with MIL-STD-750 , MIL-PRF , MIL-STD-750 , single pulse avalanche energy test (see 4.3.2) Method 3470 of MIL-STD-750 , single pulse avalanche energy test (see 4.3.2) (3) 3c Method 3161 of MIL-STD-750 , thermal impedance (see 4.3.3


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PDF MIL-PRF-19500/697E MIL-PRF-19500/697D 2N7478T1, MIL-PRF-19500.
LTPD15

Abstract: No abstract text available
Text: . Tempera lure Cycling Method 2072, Mil -STD-7!>0 1032, MIL-STD-750 1051, MIL-STD-750 Conditions In , +125°C 4. Constant Acceleration 5. Fine Leak t>. Gross Leak 2006, MIL-STD-750 1071, MIL-STD-750 1071, Mil .-ST D- 750 See individual product specs for conditions. Condition Ft, Leak Rate <5 x I0 ? , MIL-STD-750 Method Conditions Sample Size Subgroup 1 Resistance lo Solvents Internal Visual and , , Classes A and B of MIL-STD-87157 Subgroup/Test MIL-STD-750 Method Conditions Sample Size Subgroup 1


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PDF -D-87157 MIL-D-87157 MIL-STD-750 MIL-STD-750 D-750 340-hour LTPD15
2N7291

Abstract: 2N7295 c 3421 transistor 2N7293 FRK150 frk450
Text: for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test Methods for Semiconductor Devices , (3) Gate stress test (see 4.3.1) Gate stress test (see 4.3.1) (3) Method 3470 of MIL-STD-750 , (see 4.3.2) Method 3470 of MIL-STD-750 , (see 4.3.2) (3) 3c Method 3161 of MIL-STD-750 , (see 4.3.3) Method 3161 of MIL-STD-750 , (see 4.3.3) 7 Optional. Optional. 9 IGSSF1, IGSSR1, IDSS1, subgroup 2 of table I herein Subgroup 2 of table I herein 10 Method 1042 of MIL-STD-750


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PDF MIL-PRF-19500/606B MIL-PRF-19500/606A 2N7291, 2N7293, 2N7295, 2N7297, MIL-PRF-19500. 2N7291 2N7295 c 3421 transistor 2N7293 FRK150 frk450
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