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LT5554IUH#TRPBF Linear Technology LT5554 - Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C
LT1328CS8 Linear Technology LT1328 - 4Mbps IrDA Infrared Receiver; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT5503EFE#TR Linear Technology LT5503 - 1.2GHz to 2.7GHz Direct IQ Modulator and Mixer; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
LT5519EUF#TR Linear Technology LT5519 - 0.7GHz to 1.4GHz High Linearity Upconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
LT5525EUF#TR Linear Technology LT5525 - High Linearity, Low Power Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
LTC1757A-1EMS8#TR Linear Technology LTC1757A - Single/Dual Band RF Power Controllers; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C

MDIO clause 45 specification Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2004 - MDIO clause 22

Abstract: MDIO clause 45 specification MDIO clause 45 tda series class d BBT3420
Text: Data Input/Output ( MDIO ) interface specified in IEEE 802.3 Clause 22 or Clause 45 . The device supports both the 5-bit PHY address for Clause 22 and the 5-bit port address for Clause 45 . The four , bit is set in the MDIO register C001'h ( Clause 45 , Table 333) and/or 1D'h ( Clause 22, Table 3-28). , listed in Table 3-6, and the Clause 45 registers in Table 3-7. TABLE 3-6. MDIO REGISTERS IN CLAUSE 22 , 3-7. MDIO REGISTERS IN CLAUSE 45 FORMAT MII REGISTERS ADDRESS NAME DESCRIPTION DEFAULT R


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PDF BBT3420 FN7481 1875Gbps/Channel 75Gbps 1875Gbps 59Gbps 3ae-2002 MDIO clause 22 MDIO clause 45 specification MDIO clause 45 tda series class d BBT3420
2009 - MDIO clause 45 specification

Abstract: Virtex-7 serdes xilinx tcp vhdl MDIO 10G Ethernet MAC virtex 5 ddr data path virtex7 xilinx kintex virtex-7 kintex 7
Text: specification IEEE 802.3-2008 clause 49 Optional Management Data Interface ( MDIO ) interface to manage PCS/PMA registers according to specification IEEE 802.3-2008 clause 45 Virtex-6 Block RAMs 1910-2210 3 , defined in clause 45 of the IEEE 802.3-2008 standard. In this core, the MDIO interface is an optional , Specification 0 Introduction The LogiCORETM IP 10-Gigabit Ethernet PCS/PMA core forms a seamless , -6 HXT 710-960 0 Provided with Core Documentation Product Specification User Guide ·


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PDF 10-Gigabit DS739 10-Gigabit 10GBASE-R MDIO clause 45 specification Virtex-7 serdes xilinx tcp vhdl MDIO 10G Ethernet MAC virtex 5 ddr data path virtex7 xilinx kintex virtex-7 kintex 7
2009 - MDIO

Abstract: MDIO clause 45 specification MDIO clause 45 vhdl code for mac interface 10GBASE-X ffs 642 UCF virtex-4 10GBASE-LX4 vhdl code for ethernet mac spartan 3 giga media converter
Text: Machines (optional for Virtex-5 FPGAs) · UCF IEEE 802.3-2005 clause 45 MDIO interface (optional , signal and a bi-directional data signal. The interface is defined in clause 45 of IEEE 802.3-2005 , MDIO interface is omitted. 8 www.xilinx.com DS266 June 24, 2009 Product Specification , 0 XAUI v8.2 DS266 June 24, 2009 0 Product Specification 0 Introduction LogiCORE , optical modules. · Designed to 10-Gigabit Ethernet IEEE 802.3-2005 specification Uses four


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PDF DS266 10-Gbps 10-Gigabit MDIO MDIO clause 45 specification MDIO clause 45 vhdl code for mac interface 10GBASE-X ffs 642 UCF virtex-4 10GBASE-LX4 vhdl code for ethernet mac spartan 3 giga media converter
MDIO

Abstract: MDIO clause 45 MDIO communication protocol MDIO clause 22 i2c software program visual i2c Serial communication I2C in USB-MPC-KIT
Text: communicating · Low voltage I2C support · 400kHz I2C support · MDIO Clause 22 and Clause 45 · USB-MPC kit , standard I2C & MDIO peripherals · MDIO support for IEEE 802/802.3 serial communication using Clause 22 and Clause 45 . · Descriptor File (DDF) allows user to add support for new devices · MDIO & I2C , USB-MPC-KIT USB-MPC-KIT Let your PC Talk I2C & MDIO This Windows-based USB to Multi-Protocol Converter provides multiple communications capabilities supporting: I2C & MDIO . The USB-MPC


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PDF 30-day MDIO MDIO clause 45 MDIO communication protocol MDIO clause 22 i2c software program visual i2c Serial communication I2C in USB-MPC-KIT
2009 - Virtex-7 serdes

Abstract: virtex-7 virtex7 kintex7 ucf file MDIO clause 45 specification MDIO clause 45 kintex7 10GBASE-R 10G Ethernet MAC xilinx virtex 5 mac 1.3
Text: -Gigabit Ethernet specification IEEE 802.3-2008 clause 49 Optional Management Data Interface ( MDIO ) interface to manage PCS/PMA registers according to specification IEEE 802.3-2008 clause 45 No-Cost core available , , consisting of a clock signal and a bidirectional data signal. The interface is defined in clause 45 of the , Specification Introduction The LogiCORETM IP 10-Gigabit Ethernet PCS/PMA core forms a seamless interface , Specification User Guide NGC netlist VHDL, Verilog VHDL, Verilog .ucf (user constraints file) VHDL, Verilog Test


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PDF 10-Gigabit DS739 10GBASE-R Virtex-7 serdes virtex-7 virtex7 kintex7 ucf file MDIO clause 45 specification MDIO clause 45 kintex7 10G Ethernet MAC xilinx virtex 5 mac 1.3
2009 - 10Gbase-kr backplane connector

Abstract: Virtex-7 serdes virtex-7 Auto-Negotiation 10Gbase kr
Text: 770-1019 XGMII Block RAMs 3 0 Features · · Designed to 10-Gigabit Ethernet specification IEEE 802.3-2008 clause 49, 72, 73, 74 Optional Management Data Interface ( MDIO ) interface to manage PCS/PMA registers according to specification IEEE 802.3-2008 clause 45 Delivered through the Xilinx CORE GeneratorTM , signal. The interface is defined in clause 45 of the IEEE 802.3-2008 standard. In this core, the MDIO , Specification Introduction The LogiCORETM IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium


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PDF 10-Gigabit DS739 10GBASE-KR 10GBASE-R 10Gbase-kr backplane connector Virtex-7 serdes virtex-7 Auto-Negotiation 10Gbase kr
usb-mpc-kit

Abstract: MDIO clause 45 MDIO clause 22 MDIO Serial communication I2C in I2C cable USB CABLE
Text: support · MDIO Clause 22 and Clause 45 · USB-MPC kit includes: USB-MPC I2C Cable MDIO Cable , IEEE 802/802.3 serial communication using Clause 22 & Clause 45 · Menus allow easy selection from a , USB-MPC-KIT USB-MPC-KIT Let your PC Talk I2C & MDIO This USB to Multi-Protocol Converter (MPC) provides USB (V1.1 or V2.0) communications with I2C and MDIO devices. The provided Windows , support for new I2C and MDIO devices with easy to read text files. For advanced projects, please visit


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PDF 30-day usb-mpc-kit MDIO clause 45 MDIO clause 22 MDIO Serial communication I2C in I2C cable USB CABLE
Not Available

Abstract: No abstract text available
Text: 3V  MDIO to 1.8V  100 KHz and 400 KHz I2C support  MDIO Clause 22 and Clause 45 , serial communication using Clause 22 & Clause 45  Menus allow easy selection from a wide variety , USB-MPC-KIT USB-MPC-KIT Let your PC Talk I2C & MDIO This USB to Multi-Protocol Converter (MPC) provides USB V1.1 or V2.0 FS and HS communications with I2C and MDIO devices. The Windows , support for new I2C and MDIO devices with easy to read text files. For advanced projects, please visit


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PDF 2000/XP/Vista/Win7) 30-day
2009 - MDIO clause 45 specification

Abstract: MDIO clause 45 MDIO vhdl code for ethernet csma cd vhdl code for mac interface vhdl code for ethernet mac spartan 3 Xilinx ISE Design Suite 9.2i ffs 642 verilog code for frame synchronization SPARTAN-6 mgt
Text: device-specific transceivers for the XAUI interface IEEE 802.3-2005 clause 45 MDIO interface (optional) IEEE , signal and a bi-directional data signal. The interface is defined in clause 45 of IEEE 802.3-2005 , MDIO interface is omitted. 8 www.xilinx.com DS266 December 2, 2009 Product Specification , 0 XAUI v9.1 DS266 December 2, 2009 0 Product Specification 0 Introduction , 700 0 Delivered through CORE GeneratorTM Provided with Core Product Specification Getting


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PDF DS266 10-Gbps 10-Gigabit MDIO clause 45 specification MDIO clause 45 MDIO vhdl code for ethernet csma cd vhdl code for mac interface vhdl code for ethernet mac spartan 3 Xilinx ISE Design Suite 9.2i ffs 642 verilog code for frame synchronization SPARTAN-6 mgt
2010 - MDIO clause 45

Abstract: MDIO clause 22 verilog code for mdio protocol vhdl code SECDED avalon mdio register TB D83 diode RTL code for ethernet IEEE803 AN-578 32 bit SECDED* encoder adds 5 bit ecc
Text: , prtadr, devphyadr, regadr, data) Arguments clause45 Set to 1 if the MDIO is for clause 45 ; set to 0 if the MDIO is for clause 22. prtadr Clause 45 PHY port address. devphyadr Clause 45 address of device ( clause 45 ) or PHY ( clause 22). regadr MDIO register address. It uses16 bits for clause 45 and the 5 low-order bits for clause 22. data Write data for the MDIO register , , prtadr, devphyadr, regadr, data) Arguments clause45 Set to 1 if the MDIO is for clause 45 ; set


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PDF 10-Gbps UG-01076-2 MDIO clause 45 MDIO clause 22 verilog code for mdio protocol vhdl code SECDED avalon mdio register TB D83 diode RTL code for ethernet IEEE803 AN-578 32 bit SECDED* encoder adds 5 bit ecc
2009 - MDIO clause 45

Abstract: MDIO clause 22 verilog code for 10 gb ethernet testbench of an ethernet transmitter in verilog avalon mm vhdl fpga vhdl code for crc-32 verilog code CRC generated ethernet packet 10 Gbps ethernet phy clause 22 phy registers verilog code for mdio protocol
Text: (XAUI) Management data input/output ( MDIO ) master interface for PHY device management 64 , -Gbps Ethernet MAC XGMII Interface 10-Gbps Ethernet MAC 10-Gbps Ethernet PHY Device MDIO , Application Avalon-ST Interface Altera FPGA MDIO Master Verification Altera verified the 10 , reference design: Register access Management data input and output ( MDIO ) access Frame , and Resource Utilization-Stratix II GX Device XAUI FIFO (eightbyte words) MDIO


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PDF 10-Gbps AN-516-2 IP-10GETHERNET MDIO clause 45 MDIO clause 22 verilog code for 10 gb ethernet testbench of an ethernet transmitter in verilog avalon mm vhdl fpga vhdl code for crc-32 verilog code CRC generated ethernet packet 10 Gbps ethernet phy clause 22 phy registers verilog code for mdio protocol
2006 - 1310nm fp tosa 10g

Abstract: TOSA 1310 10G Optical Encoder a15 10Gb CDR MDIO ROSA 1310 10G MDIO clause 45 specification A06F P802 AEL 2006 phy
Text: IEEE 802.3ae Clause 47 Control interface: MDIO , 1.2 V, per IEEE 802.3ae Clause 45.3 Non Volatile , .3ae clause 47 Receiver lane 0:3 - 42, 45 , 48, 51 O XAUI per IEEE802.3ae clause 47 Transmitter , , 62, 65 I XAUI per IEEE802.3ae clause 47 Control & Sense I/O Pins MDIO Pins High Speed , /DEMUX, XAUI interface and MDIO management functions are all integrated into the module, as is a , wide XAUI Electrical interface · MDIO Management Interface · Front Panel hot pluggable · Digital


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PDF HFBR-707X2DEM 10GBASE-LRM, 10GbE EN60825-1 AV02-0197EN 1310nm fp tosa 10g TOSA 1310 10G Optical Encoder a15 10Gb CDR MDIO ROSA 1310 10G MDIO clause 45 specification A06F P802 AEL 2006 phy
2005 - DB62

Abstract: Optical Encoder a15 PMA 30 D15
Text: 802.3ae Clause 47 Control interface: MDIO , 1.2 V, per IEEE 802.3ae Clause 45.3 Non Volatile memory: 48 , specification defines a 256 byte block of register space that is accessible over the 2 wire serial MDIO /MDC , and MDIO management functions are all integrated into the module, as is a precision oscillator. The , interface · MDIO Management Interface · Front Panel hot pluggable · Digital Optical Monitoring (DOM , /patents General Specifications Optics PIN TIA EDC 802.3ae SerDes LD Micro I2C MDIO Other Signals


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PDF HFBR-707X2DEM 10GBASE-LRM, 10GbE EN60825-1 AV02-0197EN DB62 Optical Encoder a15 PMA 30 D15
2005 - AKR 121

Abstract: A008 intersil cx4 loopback connector 10GBaseER
Text: configuration and status reporting via 802.3 Clause 45 compliant MDC/ MDIO serial interface Automatic load of , IEEE 802.3 Clause 45 . The BBT3821 supports a 5-bit Port Address, and DEVice ADdresses (DEVAD) 1,3 & 4 , ) outputs appear in the MDIO Vendor-Specific registers at address 1.C00A'h (Table 45 ) and 4.C00A'h (Table 97 , the IEEE802.3ae-2002 clause 48 specification , and is very robust. This algorithm relies on the 10b/8b , Receive Parallel Data 8B/10B Encoder & Mux TX0N TX0P MDIO MDC SCL SDA RFCP RFCN


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PDF BBT3821 FN7483 488Gbps 1875Gbps/Lane 1875Gbps, 244Gbps 59325Gbps 195mW 1550mW AKR 121 A008 intersil cx4 loopback connector 10GBaseER
2010 - DXAU

Abstract: xilinx logicore fifo generator 6.2 Xilinx ISE Design Suite 9.2i 10Gigabit Ethernet PHY MDIO clause 45 specification 10G Ethernet PHy verilog code for 10 gb ethernet vhdl code for ethernet mac spartan 3 kintex 7
Text: clause 45 Management Data Input/Output ( MDIO ) interface (optional) IEEE 802.3-2008 clause 48 State , Specification www.xilinx.com 7 LogiCORE IP XAUI v10.3 Management Interface ( MDIO ) The MDIO , signal and a bidirectional data signal. The interface is defined in clause 45 of IEEE 802.3-2008 standard , LogiCORE IP XAUI v10.3 DS266 April 24, 2012 Product Specification Introduction The eXtended , MHz Provided with Core Documentation Product Specification User Guide Native Generic Circuit (NGC


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PDF DS266 10-Gb/s 10-Gigabit 64-bit DXAU xilinx logicore fifo generator 6.2 Xilinx ISE Design Suite 9.2i 10Gigabit Ethernet PHY MDIO clause 45 specification 10G Ethernet PHy verilog code for 10 gb ethernet vhdl code for ethernet mac spartan 3 kintex 7
2012 - MAX24287

Abstract: RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
Text: and duplex autonegotiation between parallel MII MDIO and the serial interface. This device is ideal , and Duplex Mode Negotiation Between MDIO and SGMII PCS Supports 10/100 MII or RGMII , Reference Clock Software Control Through MDIO Interface GPIO Pins Can Be Configured as Clocks, Status , . 18 MDIO Overview . 19 Examples of MAX24287 and PHY Management Using MDIO


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PDF MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-1000 switch SGMII MII GMII 1000base SX transmitter sc ENG-46158 TF401
2007 - intel 8035

Abstract: TXN17431 XENPAK Intel intel xenpak MDIO clause 22
Text: 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name NC NC MDIO MDC PRTAD4 PRTAD3 PRTAD2 PRTAD1 , as defined by IEEE 802.3ae Clause 45 and the XENPAK MSA. This interface consists of the following: · , Sinking Designed for 200 Linear Feet-Per-Minute, 50 °C Ambient Air Flow Digital Management Interface ( MDIO , . 13 MDIO Interface . 16 6.1 MDIO Physical Interface


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PDF TXN17431 10GBASE-LR 70-Pin, 5-Nov-2007 intel 8035 TXN17431 XENPAK Intel intel xenpak MDIO clause 22
MDIO clause 45 specification

Abstract: RTL code for ethernet block code error management, verilog vhdl code scrambler verilog code for 64 32 bit register 10Base-R encoder verilog coding design of scrambler and descrambler Gigabit 10GBase-R
Text: internal registers of the PCS according to the Clause 45 definition of extended MDIO of 802.3ae. · , . MAC, POS-PHY L3, Flexbus-4 and MDIO Cores). It is designed to be used in conjunction with the , MAC 10G Base-R PCS 10G Base-SR/LR/ER PHY (with FIFO) extended MDIO & Host Interface MDIO Management µP Figure 2: 10G Ethernet Serial LAN System Solution 2 10 Gigabit Ethernet , final specification . Test Pattern Check BER Test 64b/66b Block Decoding 16 64


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PDF 10GBase-R MDIO clause 45 specification RTL code for ethernet block code error management, verilog vhdl code scrambler verilog code for 64 32 bit register 10Base-R encoder verilog coding design of scrambler and descrambler Gigabit
2009 - MDIO clause 45 specification

Abstract: xaui marvell "reduced xaui" dune Marvell PHY Xilinx virtex rxaui marvell DS740 Marvell PHY register map marvell ethernet PHY transceivers Marvell design guide XGXS
Text: IEEE 802.3-2008 clause 45 MDIO interface (optional) Available under the Xilinx End User License , . The interface is defined in clause 45 of IEEE 802.3-2008 standard. In the RXAUI core, the MDIO , Machine monitors the deskew logic per the IEEE 802.3-2008 specification . Optional MDIO Interface is a , LogiCORE IP RXAUI v2.3 DS740 April 24, 2012 Product Specification Introduction The LogiCORETM , IP Facts Table Core Specifics Virtex-7, Kintex-7, Virtex-6 XGMII, MDIO Resources(2) Configuration


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PDF DS740 MDIO clause 45 specification xaui marvell "reduced xaui" dune Marvell PHY Xilinx virtex rxaui marvell Marvell PHY register map marvell ethernet PHY transceivers Marvell design guide XGXS
2005 - Not Available

Abstract: No abstract text available
Text: specifications. High speed electrical and optical specifications are compliant with IEEE 802.3ba Clause 86 for 100GBASE-SR10 media, Clause 86A for CPPI electrical interface, Clause 83A for CAUI electrical interface and Clause 45 for MDIO . • Compliant to RoHS directives The transceiver electrical interface , module operating conditions over the MDIO interface. Applications • 100 Gb/s Ethernet Interconnects (802.3ba Clause 86) • 10×10 Gb/s Ethernet Interconnects (802.3ae Clause 52) • Datacom


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PDF AFBR-8420Z 100GBASE-SR10 AFBR-8420Z 100Gbps 125Gb/s 3125Gb/s AV02-4018EN
2007 - MDIO clause 45 specification

Abstract: pc 248 10G APD FTLX8541 FTLX8541E2 FTLX8541F2 MDIO clause 45
Text: clause 45 & 47 X2 MSA Issue 2.0b X. For More Information Finisar Corporation 1389 Moffett Park Drive , Product Specification RoHS-6 Compliant 10 Gb/s 850nm Multimode X2 Transponder FTLX8541E2 , MDIO 2-wire bus 70-pin connector Separated signal/chassis ground Mid Pak module variance for front , Page 1 FTLX8541 Product Specification ­ November 2007 I. Pin Descriptions Signal Name Level I/O Management and Monitoring Ports MDIO Open Drain I/O Pin No. Description 17 MDC


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PDF 850nm FTLX8541E2/FTLX8541F2 FTLX8541E2) FTLX8541F2) 70-pin FTLX8541 3ae-2002 10GBASE-SR 10GFC 1200-M5-SN-I MDIO clause 45 specification pc 248 10G APD FTLX8541E2 FTLX8541F2 MDIO clause 45
2007 - Not Available

Abstract: No abstract text available
Text: Standard Specifications References ̇ ̇ IEEE Std 802.3ae-2002 clause 45 & 47 X2 MSA Issue 2.0b X , Product Specification RoHS-6 Compliant 10 Gb/s 850nm Multimode X2 Transponder FTLX8541E2 , (FTLX8541E2) 4x 3.1875 Gb/s Fibre Channel (FTLX8541F2) Management and control via MDIO 2-wire bus 70 , FTLX8541 Product Specification – November 2007 I. Pin Descriptions Signal Name Level I/O Management and Monitoring Ports MDIO Open Drain I/O Pin No. Description 17 MDC I 18


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PDF 850nm FTLX8541E2/FTLX8541F2 FTLX8541E2) FTLX8541F2) 70-pin 3ae-2002 10GBASE-SR 10GFC 1200-M5-SN-I
2004 - sgmii specification ieee

Abstract: ENG-46158 virtex-7 1000BASE-X sfp sgmii traffic light controller vhdl coding ISERDES vhdl code for ethernet mac spartan 3 SPARTAN 6 ethernet vhdl ethernet spartan 3a vhdl ethernet spartan 3e
Text: Specification Introduction The LogiCORETM Ethernet 1000BASE-X PCS/PMA or Serial Gigabit Media Independent , SMGII to GMII bridge, as defined in the Serial-GMII specification (ENG-46158) LogiCORE IP Facts Table , Specification User Guide VHSIC Hardware Description Language (VHDL_ and Verilog, Native Generic Circuit (NGC , monitored through the serial Management Data Input/Output ( MDIO ) Interface (MII Management), which can , respective owners. DS264 January 18, 2012 Product Specification www.xilinx.com 1 LogiCORE IP


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PDF 1000BASE-X DS264 ENG-46158) sgmii specification ieee ENG-46158 virtex-7 1000BASE-X sfp sgmii traffic light controller vhdl coding ISERDES vhdl code for ethernet mac spartan 3 SPARTAN 6 ethernet vhdl ethernet spartan 3a vhdl ethernet spartan 3e
2012 - RGMII-1000

Abstract: MAX24287 switch SGMII MII GMII sgmii specification ieee ENG-46158
Text: duplex autonegotiation between parallel MII MDIO and the serial interface. Microprocessor interaction is , MDIO and SGMII PCS Supports 10/100 MII or RGMII Operation with SGMII Running at the Same , at Reset for Many Common Usage Scenarios Optional Software Control Through MDIO Interface GPIO Pins , . 18 MDIO Overview . 19 Examples of MAX24287 and PHY Management Using MDIO


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PDF MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-1000 switch SGMII MII GMII sgmii specification ieee ENG-46158
2011 - MAX24287

Abstract: RGMII-100 max24287etk sgmii switch RGMII-1000 125Gb 1000BASE-X sfp 369B switch SGMII MII GMII MII100
Text: speed and duplex autonegotiation between parallel MII MDIO and the serial interface. Microprocessor , MDIO and SGMII PCS Supports 10/100 MII or RGMII Operation with SGMII Running at the Same Rate , MDIO Interface GPIO Pins Can Be Configured as Clocks, Status Signals and Interrupt Outputs , . 18 MDIO INTERFACE . 19 6.4 6.4.1 6.4.2 MDIO Overview


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PDF MAX24287 MAX24287 25Gbps 1000BASE-X 1000BASE-T RGMII-100 max24287etk sgmii switch RGMII-1000 125Gb 1000BASE-X sfp 369B switch SGMII MII GMII MII100
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