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MSP430-3P-TOTAL-TP320120-PRGA Texas Instruments Beagle I2C/SPI/MDIO Protocol Analyzer

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2012 - BV03C

Abstract: DVR RXD1
Text: (Pin# 26) pin unconnected. Since the MDC and MDIO management signals are not used in this mode, they , Figure 6. 3_3VD 10kΩ 1.5kΩ MDIO MDC SOC (CODEC) TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TX_CLK RX_CLK RX_ER RX_DV RXD0 RXD1 RXD2 RXD3 3_3VD 3_3V 10kΩ 330Ω MDIO MDC 4 3 26 29 30 31 32 33 37 36 38 39 40 41 44 45 MDIO MDC TX_ER_B TX_EN_B TX_D0_B , RX_DV_A RX_D0_A RX_D1_A RX_D2_A RX_D3_A 53 MDIO MDC LED 17 14 18 19 20 21 Transmit


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PDF TW3801-C1, TW3811- AN1804 1-888-INTERSIL OpeW3811 TW3811 BV03C DVR RXD1
power connector hdr1x2

Abstract: J0011D21B HDR1X2 dp83848 dp83848 application MDIO MDC HDR 1X2 Header HDR1X2 LP3964 LTM673
Text: 1.5K MDIO MDC Populate J6 & X1 and Depopulate C3, C4 & Y1 only for RMII option 3V3 3V3 , X2 C4 33PF LED_LINK R13 2.2K U1 MDIO MDC J1 VCC3 GND1 GND2 GND3 GND4 , VCC1 MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 , 2.2K MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER 33 33 R2 R4 R6 33 RX_CLK , 0.1uF 1 2 DGND IOGND X1 X2 IOVDD33 MDC MDIO RESET_N LED_LINK/AN0 LED_SPEED/AN1 LED_ACT


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PDF DP83848 RJ-45 DP83848 J0011D21B DP83848, DP83848YB 1500pF HDR-2X18 power connector hdr1x2 J0011D21B HDR1X2 dp83848 application MDIO MDC HDR 1X2 Header HDR1X2 LP3964 LTM673
Delta LF8505

Abstract: delta lf8731 YCL PT163020 Transpower HB826-2 YCL PH406466 lf8505 LF8731 Pt163020 lf8505 delta PH406466
Text: JP SDA SCL C25 SPIQ SCL SDA SPIS-N RST# MDIO MDC MDIO MDC PS1 PS0 95M ONLY , LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SCL/SPIC SDA/SPID SPIS-N PS1 PS0 RST-N GNDD , VCC MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 , NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC 10K R102 VCC MDIO MDC , 17 18 19 20 JP24JP25JP26JP27JP28JP29JP30JP31 JP MDIO MDC JP JP JP JP JP


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PDF JP39-JP42 MIC39150-1 MIC5209-3 POST03C KS8995M/8995X Delta LF8505 delta lf8731 YCL PT163020 Transpower HB826-2 YCL PH406466 lf8505 LF8731 Pt163020 lf8505 delta PH406466
OSC 125MHz

Abstract: U17E AX88655 AX88655P CRYSTAL 27MHZ 8c350 AT24C16B
Text: GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 NC NC NC NC VDD33 /RST VSS SYSCLK NC MDC MDIO SDC SDIO , MDIO I I I/O/PU 40 170 165 MDC SDIO O I/O/PU 166 163 Crystal or OSC 27MHz , one packet. 3.6 MII Polling The AX88655 supports PHY management through the serial MDIO / MDC , /1000BASE-T Ethernet Switch register of PHYs via MDIO / MDC interface after power on reset. The AX88655 will , , duplex mode, and 802.3x flow control capable status of the connected PHY devices through MDIO / MDC serial


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PDF AX88655 10/100/1000BASE-T AX88655-1 OSC 125MHz U17E AX88655P CRYSTAL 27MHZ 8c350 AT24C16B
ttl7404

Abstract: OP404 U1056 193 ec5 LF8708 U2011 U105 U1015 r110x RJ45X
Text: Sheet E 1 of 6 1 2 3 4 5 U1 U3 5V 5V F1 5V MDIO MDC RXD1_3 RXD1_2 FUSE 4 R62 RXC1 RXC1 RXD1_1 RXD1_0 RXDV1 U201_1 MDIO MDC RXD1_3 RXD1_2 1 2 3 , TXD1_2 TXD1_3 COL1 CRS1 U201_1 16 17 18 19 20 VCC MDIO MDC RXD<3> RXD<2> VCC , 25 24 23 22 21 GND GND GND GND U201_1 F3 MDIO MDC RXD3_3 RXD3_2 FUSE GND RXC3 RXC3 R64 RXD3_1 RXD3_0 RXDV3 U203_1 MDIO MDC RXD3_3 RXD3_2 1 2 3 4 5


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PDF 1000PF RX8BI82 SPD100LED6# LED17 SPD100LED8# LED25 LED14 LED15 LED24 ttl7404 OP404 U1056 193 ec5 LF8708 U2011 U105 U1015 r110x RJ45X
2000 - GMII magnetics

Abstract: MDIO MDC DP83862 PAM-5 GMII ethernet mdio circuit diagram 10BASET MDIO controller
Text: 10/100/1000 ETHERNET MAC/Controller MDIO / MDC MII/GMII /SGMII DP83862 10/100/1000 Mb/s MII/GMII ETHERNET PHYSICAL LAYER /SGMII STATUS LEDs MDIO / MDC MAGNETICS 10/100/1000 , One Port) COMBINED GMII, MII INTERFACE MDIO MDC GTX_CLK TX_ER TX_EN TXD[7:0] TX_CLK


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PDF DP83862 10BASET, 100BASE-TX 1000BASE-T 10BASE-T, GMII magnetics MDIO MDC PAM-5 GMII ethernet mdio circuit diagram 10BASET MDIO controller
1995 - S82557

Abstract: crystal oscillator KDS 20MHz intel 82557 IMBT4401 equivalent TCO-711JTCR TCO-711JTCR-25MHZ 93C46 national semiconductor XL93LC46ARF-111 res pack DX200
Text: Management ( MDIO , MDC ) 156, 157 Input Clocks (RXCLK, TXCLK) 151, 8 Receive Data (RXD0) 150 , RXERR RXDV CRS CDT TXD3:0 TXCLK TXEN 82557 PHY MDC MDIO RESET PCI Bus Signals 3.1 , PE69001 MDIO MDC 102 103 104 107 108 109 114 115 118 119 120 123 S3X S2Y VCC4 VCC5 GND5 VCC2 MDINT#/LPBK/JAM# MDC MDIO COL CRS RX_ER RX_DV R2 510 VCC3 PLED0# PLED1 , FA1 FA0 144 1 2 3 4 5 6 7 8 15 16 1 82557 FDXRSTOUT LPBCK MDIO MDC


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PDF AP-370 1/10W S82557 NM93C46M8 NM93C46M8-TR crystal oscillator KDS 20MHz intel 82557 IMBT4401 equivalent TCO-711JTCR TCO-711JTCR-25MHZ 93C46 national semiconductor XL93LC46ARF-111 res pack DX200
circuit diagram of smart home

Abstract: MDIO MDC dvr wiring diagram MDIO DM9801E DM9801 MDIO controller MII IEEE802.3u home PNA
Text: provided by MDIO / MDC when operating in MII mode, or a Serial Peripheral Interface bus when operating in , physical-layer, single-chip transceiver Supports the MII including the MDIO / MDC serial management interface


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PDF DM9801E DM9801 DM9801 IEEE802 100-pin DM9801E circuit diagram of smart home MDIO MDC dvr wiring diagram MDIO MDIO controller MII IEEE802.3u home PNA
ip108

Abstract: transforme MDIO MDIO MDC IP1726 IP108 IP1726 SIGNAL PATH DESIGNER mdio termination
Text: layout 5.3 MDC and MDIO recommendation The MDIO and MDC are routed across every IP108 and IP1726 , the MDC and MDIO should not be parallel to any high-speed click signal to avoid the interference. MDC / MDIO MDC / MDIO RXCLK/TXCLK RXCLK/TXCLK Poor Good Figure 5.3 Avoid signal , Switch system, the MDC and the MDIO are routed to each PHY device. To achieve the best performance of , MDC =8mil MDIO =8mil MDC & MDIO space=16mil MDC MDIO MDC MDIO IP1726 MDC MDIO IP108


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PDF IP1726 IP108 100mil 100mil transforme MDIO MDIO MDC IP1726 IP108 SIGNAL PATH DESIGNER mdio termination
2005 - J311

Abstract: dp83848 application 2.2k 250v dp83848 h1102 application note PS2501-1-H PA1269 H1102 .22K 250V X2 R110
Text: 19 21 23 25 27 29 31 33 35 37 39 MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER , R7 2.2K D R107 2.2K 3V3 2.2K R8 1.5K MII_MODE AN0 AN1 AN_EN MDIO MDC , TANT. PHYAD0 PHYAD1 PHYAD2 36 35 34 33 32 31 30 29 28 27 26 25 U1 MDIO MDC , C8 0.1uF 1 2 3 4 5 6 7 8 9 10 11 12 MTG2 VCC3 VCC1 GND1 MDIO GND2 MDC GND3 , 34 35 36 37 38 39 40 MTG1 41 PFBOUT C C3 C4 DGND IOGND X1 X2 IOVDD33 MDC


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PDF RJ-45 001uF R101-R104 R91-R94 1500pF MTG250R125 RJ-45 DP83848 J311 dp83848 application 2.2k 250v h1102 application note PS2501-1-H PA1269 H1102 .22K 250V X2 R110
2005 - PS2501-1-H

Abstract: mtg250r125 dp83848 application mdc r69 h1102 application note DP83848 R110 R107 LM5070 hd01
Text: 29 31 33 35 37 39 MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER D TX_CLK , R107 2.2K 3V3 2.2K R8 1.5K MII_MODE AN0 AN1 AN_EN MDIO MDC LED_CFG AN0 , PHYAD1 PHYAD2 36 35 34 33 32 31 30 29 28 27 26 25 U1 MDIO MDC RXD3 RXD2 RXD1 , 2 3 4 5 6 7 8 9 10 11 12 MTG2 VCC3 VCC1 GND1 MDIO GND2 MDC GND3 RXD3 GND4 , 38 39 40 MTG1 41 PFBOUT C C3 C4 DGND IOGND X1 X2 IOVDD33 MDC MDIO RESET_N


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PDF R101-R104 R91-R94 1500pF MTG250R125 RJ-45. DP83848 PS2501-1-H mtg250r125 dp83848 application mdc r69 h1102 application note R110 R107 LM5070 hd01
2004 - Not Available

Abstract: No abstract text available
Text: backplane applications • IEEE 802.3ae 10 Gigabit Ethernet compliant - XAUI, XGMII, and MDC / MDIO , serial or parallel ports is available under external pin or MDIO control. Suitable control and status registers are available through the IEEE standard MDIO / MDC system. The XGMII interface can be configured , MDIO RFCP RFCN Static Clock Multiplier 2.5 to 3.1875G Controls MDIO / MDC Register File MDC FIGURE 2. BBT3420 FUNCTIONAL BLOCK DIAGRAM FOR A SINGLE CHANNEL All Intersil U.S. products


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PDF BBT3420 FN7481 8-bit/10-bit 488Gbps 488Gbpsil
2004 - HSBGA

Abstract: BBT3420
Text: backplane applications · IEEE 802.3ae 10 Gigabit Ethernet compliant - XAUI, XGMII, and MDC / MDIO interfaces , Byte CLK Equalization MDIO RFCP RFCN Static Clock Multiplier 2.5 to 3.1875G Controls MDIO / MDC Register File MDC FIGURE 2. BBT3420 FUNCTIONAL BLOCK DIAGRAM FOR A SINGLE , or MDIO control. Suitable control and status registers are available through the IEEE standard MDIO / MDC system. The XGMII interface can be configured in source-centered or source synchronous timing


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PDF BBT3420 FN7481 8-bit/10-bit 488Gbps HSBGA
LM5070

Abstract: DP83848 R101 R102 R104 "Power over Ethernet"
Text: J59 MII Header MDIX_EN LED_CFG MII_MODE 25MHz_OUT MDIO / MDC MII Male Connector JTAG pins , datasheet. 25MHz clock output Allow MDIO / MDC signals connect from J1 to J13 SmartBits interface JTAG , supply: Remove jumper on J58 and resistor R12. Use J55 for external power connections. To access MDIO


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PDF DP83848 RJ-45 50MHz 25MHz LM5070 R101 R102 R104 "Power over Ethernet"
2005 - j0011d21b

Abstract: ECCM1 XTAL - 25M PulseJack J0011D21B 174214-2 47R5 GND14 AVDD33 BLM21AG121SN1 HDR1X3 mrxd3
Text: stuff resistor R31 C25 0.1uF MDIO MDC D D For PHY address 1 (Default) do not stuff , TXD_0 TXD_1 TXD_2 TXD_3 RESERVED RESERVED RESERVED VCC3 VCC1 GND1 MDIO GND2 MDC GND3 , PulseJack J0011D21B 33 R13 1 2 3 30 29 28 27 26 25 24 23 22 21 MDIO MDC PFBIN2 DGND X1 X2 IOVDD33 MDC MDIO RESET_N LED_LNK LED_SPD R34 0.0 TX_CLK R10 TX_EN TXD0 R12 , stuff MDIO Access Connection 33 B 33 33 Remove R42 for PHYTERMini R42 LED_SPD 275


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PDF SemJ0011D21B IOVDD33 DP83848J/K. 1500pF DP83848J/K j0011d21b ECCM1 XTAL - 25M PulseJack J0011D21B 174214-2 47R5 GND14 AVDD33 BLM21AG121SN1 HDR1X3 mrxd3
2004 - verilog code of prbs pattern generator

Abstract: verilog code of parallel prbs pattern generator MDIO clause 22 verilog code for fibre channel BBT3420 BBT3421 verilog code for serial multiplier
Text: encoding schemes · Extensive configuration and status reporting via 802.3 compliant MDC / MDIO serial interface Get FULL DATASHEET · MDIO Interface Compliant with IEEE 802.3ae Clause 45 and Clause 22 , control and status registers are available through the IEEE standard MDIO / MDC system. If the , /10B Encoder & Mux OUT0OUT0+ MDIO Static Clock Multiplier Controls MDIO / MDC Register File 3.125G MDC FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF BBT3421 All Intersil U.S. products


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PDF BBT3421 FN7482 10Gigabit 10GBASE-LX4) OC-48 OC-48, 10GFC-SN4 488Gbps 187Gbps verilog code of prbs pattern generator verilog code of parallel prbs pattern generator MDIO clause 22 verilog code for fibre channel BBT3420 verilog code for serial multiplier
verilog prbs generator

Abstract: BBT3400 MDIO MDC nPowerBBT3400
Text: Data-Rate (DDR) Mode 802.3 compliant MDC / MDIO serial interface Clock compensation via IDLE insertion , MDIO / MDC system. The XGMII interface may be configured in source-centered or source synchronous , + Deserializer & Comma Detector 8B/10B Decoder Receive FIFO Receive Byte CLK MDIO RCLOCK NRCLOCK Static Controls MDIO / MDC Register File Clock Multiplier 3.125G MDC Figure 2


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PDF BBT3400 125Gbps BBT3400 8-bit/10-bit 10-Gigabit 289-pin verilog prbs generator MDIO MDC nPowerBBT3400
2004 - Not Available

Abstract: No abstract text available
Text: schemes • Extensive configuration and status reporting via 802.3 compliant MDC / MDIO serial interface Get FULL DATASHEET • MDIO Interface Compliant with IEEE 802.3ae Clause 45 and Clause 22 Frame , control and status registers are available through the IEEE standard MDIO / MDC system. If the , NRCLOCK 8B/10B Encoder & Mux OUT0OUT0+ MDIO Static Clock Multiplier Controls MDIO / MDC Register File 3.125G MDC FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF BBT3421 All Intersil U.S


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PDF BBT3421 FN7482 10Gigabit 10GBASE-LX4) OC-48 OC-48, 10GFC-SN4 488Gbps 187Gbps
2004 - RGMII 3COM

Abstract: mdio termination r23b DP83865 SCHEMATIC rj45 stackup LM370 DP83865DVH R10B LM3704 duplex-led
Text: impedance of the MAC chip's output pins. MDC / MDIO termination as suggested by IEEE spec. TX_EN TX_ER , CRS COL 2 1k5 MDIO MDC 1 R5 2 18 4 33 MDIO MDC 1 U2 1 2 3 4 5 R51 , 2 75 R18 2 10n 80 81 MDIO MDC 103 105 111 117 123 98 100 11 19 25 35 , / PHYAD0_STRAP GTX_CLK / RGMII_TCK PHYAD1_STRAP PHYAD2_STRAP PHYAD3_STRAP PHYAD4_STRAP MDIO MDC


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PDF DP83865DVH: LINK100 25MHz DP83865 RGMII 3COM mdio termination r23b DP83865 SCHEMATIC rj45 stackup LM370 DP83865DVH R10B LM3704 duplex-led
mem 10b

Abstract: MDIO MDC Optical Encoder Modules
Text: Equalization Per Channel Signal detect indicator Double Data-Rate (DDR) Mode 802.3 compliant MDC / MDIO serial , MDIO / MDC system. The XGMII interface may be configured in source-centered or source synchronous , + Deserializer & Comma Detector 8B/10B Decoder Receive FIFO Receive Byte CLK MDIO RCLOCK NRCLOCK Static Controls MDIO / MDC Register File Clock Multiplier 3.125G MDC Figure 2


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PDF BBT2400 50Gbps 289-pin mem 10b MDIO MDC Optical Encoder Modules
2004 - CX4 cable

Abstract: 10GBASE-CX4 BBT3821 MDIO MDC 10GBASE-LX4
Text: -Gigabit Ethernet (IEEE 802.3ae) Clause 45, 53 & 54 - MDC / MDIO serial interface - 10GBASE-LX4 - 10GBASE , of the serial signals is available under MDIO / MDC control. Both the BBT3821 and the XENPAK/XPAK/X2 control and status registers are available through the IEEE standard MDIO / MDC system. If the , low-power operation - 1.5 Watts - 1.5V Power Supply · XENPAK compatible MDIO Interface · I2C for NVR or


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PDF BBT3821 FN7483 CX4 cable 10GBASE-CX4 MDIO MDC 10GBASE-LX4
2004 - CX4 cable

Abstract: 10GBASE-CX4 BBT3821
Text: -Gigabit Ethernet (IEEE 802.3ae) Clause 45, 53 & 54 - MDC / MDIO serial interface - 10GBASE-LX4 - 10GBASE , of the serial signals is available under MDIO / MDC control. Both the BBT3821 and the XENPAK/XPAK/X2 control and status registers are available through the IEEE standard MDIO / MDC system. If the , low-power operation - 1.5 Watts - 1.5V Power Supply · XENPAK compatible MDIO Interface · I2C for NVR or


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PDF BBT3821 FN7483 CX4 cable 10GBASE-CX4
1998 - amp 120527-1

Abstract: SN74ALS244ADW TCSCN1C106MCAR MCR10JW102 2A3 zener diode GMC21X7R103K50NT 74ALS245D 74ALS244D TCSCN1C106 SG51P-1VC
Text: . 12 MDIO / MDC Interface on TNETX3150/TNETX3100 . 13 , ThunderSWITCH. The MDIO / MDC interface now has two options: PHY access is accomplished using either the ThunderSWITCH MDIO / MDC interface or the DIO board. Move from +5V design to +3.3V for voltage compatibility , write is complete. BUSY is not used for any other register or MDIO / MDC signal access. Table 3 and , Interrupt Bits R 0x14 - 0x17 Switch STXRDY/ SRXRDY Bits R MDIO / MDC Interface on TNETX3150


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PDF SPWA027 DS0027-001 amp 120527-1 SN74ALS244ADW TCSCN1C106MCAR MCR10JW102 2A3 zener diode GMC21X7R103K50NT 74ALS245D 74ALS244D TCSCN1C106 SG51P-1VC
1997 - header 30X2

Abstract: JS29 EPM7032LC44-10 FB j33 AD11 RXD11 AD14 TXD11 js35 JS17
Text: DevSel~ Stop~ Frame~ Par TRdy~ IRdy~ C/Be~[3:0] AD[31:0] Int~ B B MDC MDIO RXD0[3:0 , ] Ras~[1:0] Cas~ WE~ ChipSel~ C MDC_PHY Addr[7:0] Rst~ Clk C SERIAL MDC MDIO , Technology mdc mdio crs0 crs1 col0 col1 rxdv0 rxdv1 rxer0 rxer1 rxclk0 rxclk1 , Data4 Data3 Data2 Data1 Data0 4 C/Be~[3:0] AD[31:0] Addr[8:0] 18 MDC MDIO CRS , 3 4 MDC MDIO [1:0] TX_ER[1:0] TX_EN[1:0] A A MDIO0 MDIO1 TX_ER0 TX_ER1


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PDF Clk33Out Clk33In GT48002A TXD11 TXD13 RXD11 RXD13 TXD00 TXD01 TXD02 header 30X2 JS29 EPM7032LC44-10 FB j33 AD11 RXD11 AD14 TXD11 js35 JS17
2005 - j0011d21b

Abstract: HDR1X2 MDIO MDIO MDC power connector hdr1x2 PulseJack LTM673 LP3964 PulseJack J0011D21B HDR 1X2
Text: -J6 settings 1 to 2 MDIO MDC 3V3 D 1 D C11 Phy Address J4 Address , Populate R13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 J3C MDIO MDC PFBIN2 DGND X1 X2 IOVDD33 MDC MDIO RESET_N LED_LNK 25MHz_OUT VCC3 VCC1 GND1 MDIO GND2 MDC GND3 RXD3 GND4 RXD2 GND5 RXD1 GND6 RXD0 GND7 RX_DV GND8 RX_CLK GND9 RX_ER GND10 , 800mA R11 SD MDIX_EN MII_VDD R23 Open X2 C4 33PF MDIO Access Connection J3A-J3B


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PDF DB-25-M) NC7SZ126 w/J15 DP83848M/T/H j0011d21b HDR1X2 MDIO MDIO MDC power connector hdr1x2 PulseJack LTM673 LP3964 PulseJack J0011D21B HDR 1X2
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