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LTC3566EUF#PBF-ES Linear Technology High Efn¼üciency USB Power Manager Plus 1A Buck-Boost Converter
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LT3500IMSE#TRPBF Linear Technology LT3500 - Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C
LT3500EDD#PBF Linear Technology LT3500 - Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
LTC1704BEGN#TRPBF Linear Technology LTC1704 - 550kHz Synchronous Switching Regulator Controller Plus Linear Regulator Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
LTC3566EUF-2#PBF Linear Technology LTC3566 - High Efficiency USB Power Manager Plus 1A Buck-Boost Converter; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C

MAX PLUS II datasheet (18)

Part Manufacturer Description Type PDF
Max+Plus II Altera Max+Plus II - A Perspective Original PDF
Max+Plus II Altera Max+Plus II Programmable Logic Development System Original PDF
MAX+PLUS II Altera MAX+PLUS II Programmable Logic Development System & Software Data Sheet Original PDF
MAX+PLUS II Altera TB 49: Generating Post-Route Files in the MAX+PLUS II Software for Third-Party Verification Tools Original PDF
MAX+PLUS II Altera MAX+PLUS II Brochure Original PDF
MAX+PLUS II Command-Line Altera MAX+PLUS II Command-Line Mode Original PDF
MAX+PLUS II,Manual Altera Preface & Section 1: MAX+PLUS II Installation Original PDF
MAX+PLUS II,Manual Altera MAX+PLUS II Getting Started Manual Original PDF
MAX+PLUS II,Manual Altera Section 2: MAX+PLUS II - A Perspective Original PDF
MAX+PLUS II,Manual Altera Appendices, Glossary & Index Original PDF
MAX+PLUS II,Manual Altera Section 3: MAX+PLUS II Tutorial Original PDF
MAX+PLUS II,Quartus II software Altera Design Software Selector Guide Original PDF
MAX+PLUS II,Technical Brief Altera TB 42: Using Synopsys FPGA Express Software to Synthesize Designs for MAX+PLUS II Software Original PDF
MAX+PLUS II,Technical Brief Altera TB 40: Advantage of MAX+PLUS II Fitting Original PDF
MAX+PLUS II,Technical Brief Altera TB 44: Using Synplicity Synplify Software to Synthesize Designs for MAX+PLUS II Software Original PDF
MAX+PLUS II,Technical Brief Altera TB 39: Using Synopsys Design Compiler & FPGA Compiler to Synthesize Designs for MAX+PLUS II Software Original PDF
MAX+PLUS II,Technical Brief Altera TB 45: Importing Synthesized Files from EDA Tools into the MAX+PLUS II Software for Place & Route Original PDF
Max+Plus II Tutorial Altera Max+Plus II Tutorial Original PDF

MAX PLUS II Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2000 - format .rbf

Abstract: FLEX10K20 AN-116 19PSA Altera flex10k max plus flex 7000 EPC1441 EP20K600E 20KFLEX EP20K400
Text: 20K, FLEX 10K & FLEX 6000 Devices Raw Binary File .rbf (1) MAX PLUS II Quartus MAX PLUS II Quartus APEX 20K FLEX 10K FLEX 6000 5 EPC4E 2.5V 1.8V 4,194 , nSTATUS High OE nSTATUS CONF_DONE High nSTATUS Low MAX PLUS II , DCLK Low CONF_DONE Low CONF_DONE Low MAX PLUS II Quartus User-Supplied Start-Up Clock , DCLK DATA nCS OE nCE GND (1) SRAM .sof .pof MAX PLUS II Combine Programming Files


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PDF 20KFLEX 10KFLEX EPC1EPC1441 2000Altera 03-3340-9480FAX. format .rbf FLEX10K20 AN-116 19PSA Altera flex10k max plus flex 7000 EPC1441 EP20K600E EP20K400
1998 - 4005E

Abstract: No abstract text available
Text: as much device resources. The second Altera team could not complete the design because Altera's MAX PLUS II software kept issuing a "Device Does Not Fit" error. Summary of the teams' results: Device


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alarm clock design of digital VHDL

Abstract: digital dice design of digital VHDL altera alarm clock design of digital VHDL altera FPT-XCS10TQ144 design counter traffic light digital dice design VHDL different vendors of cpld and fpga traffic light using VHDL FPT1 xcs10tq144
Text: 9V Adaptor or Extend Power Pin provided for user. Specification :DC 5V 11.Support ALTERA MAX + Plus II Baseline and XILINX Foundation's development system. 12.Not use expanded area I/O Pin provided


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PDF 25pin alarm clock design of digital VHDL digital dice design of digital VHDL altera alarm clock design of digital VHDL altera FPT-XCS10TQ144 design counter traffic light digital dice design VHDL different vendors of cpld and fpga traffic light using VHDL FPT1 xcs10tq144
1997 - 4x2 mux

Abstract: verilog code for stop watch KEYPAD 4 X 4 verilog KEYPAD 4 X 3 verilog source code synario
Text: SYN-MAX) - select this interface kit only if you own and have already installed MAX + Plus II software from Altera X Altera Device Kit (model number SYN-MAX-PR) - select this device kit to install the MAX Device Kit and MAX + Plus II software For installation instructions, please refer to the beginning of this , tutorial provides some useful examples of two device kits: PLD and Altera MAX plus II . It leads you through , plus (+) key on the numeric keypad. As the cursor moves to the sequences through the clock edges, the


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PDF Multi-63 Multi-64 4x2 mux verilog code for stop watch KEYPAD 4 X 4 verilog KEYPAD 4 X 3 verilog source code synario
2001 - dual 7 segment led display

Abstract: APEX nios development board APEX20K200E apex lcd 7-segment LED display module via RS232 "10-pin dip" amd ieee embedded system projects MAX PLUS II 20K200EFC484
Text: on page 14. MAX PLUS + II projects that include the design, implementation, and programming files , -bit Nios embedded processor system reference design. A QuartusTM II project directory containing the , A JTAG connection (JP3) that can be used with Quartus II software via a ByteBlaster or , A logic-negative power-on-reset signal. Two regulated 3.3-V power-supply pins (500 mA total max , 5-V power supply (50 mA max load) is presented on pin 2 of JP12 (the corresponding pin on the 3.3


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PDF -MNL-NIOS-01 20K200E 16-bit) 32-bit 16-bit EP20K200E RS-232 dual 7 segment led display APEX nios development board APEX20K200E apex lcd 7-segment LED display module via RS232 "10-pin dip" amd ieee embedded system projects MAX PLUS II 20K200EFC484
2001 - EPF10K200S

Abstract: EPF10K50S FLEX 10ke pll EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E
Text: Corporation MAX PLUS II Programmable Logic Development System & Quartus Programmable Logic , 16 90 MHz f CLKDEV MAX PLUS II (1) 25,000 PPM t INCLKSTB 100 ps , ClockBoost 2 16 37.5 MHz f CLKDEV MAX PLUS II (1) 25,000 PPM t INCLKSTB , t INCLKSTB <50 200 (4) ps 60 40 50 : (1) MAX PLUS II ClockLock , V I OL = 2 mA DC, V CCIO = 2.30 V (10) V OL 0.7 V 2.5 V Low II V I


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PDF EPF10K30E EPF10K50E EPF10K50S EPF10K200S EPF10K50S FLEX 10ke pll EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E
2001 - EPF10K10

Abstract: MAX PLUS II EPF10K50V EPF10K50 EPF10K40 EPF10K30A EPF10K30 EPF10K20 EPF10K10A flex 10k altera
Text: -3DX C 7.2 MAX PLUS II 9 3 PCIPeripheral Component Interconnect MultiVolt I/O , Sheet MAX PLUS II EDA ns 0.1 24 FLEX 10K 24. FLEX 10K I/O Altera , HP 9000 700/800 f Altera Corporation MAX+PLUS II Programmable Logic Development , V OL 0.2 V II I OZ V I = V CC ground (9) ­ 10 10 µA I/O V O , I OL = 0.1 mA DC (9) 0.2 V II V I = 5.3 V to ­ 0.3 V (10) ­ 10 10 µA I


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PDF EPF10K10 EPF10K20 EPF10K10A EPF10K30 EPF10K40 EPF10K30A EPF10K50 EPF10K50V MAX PLUS II EPF10K50V EPF10K50 EPF10K40 EPF10K30A EPF10K20 EPF10K10A flex 10k altera
2000 - EPF10K30ETC144-1

Abstract: EPF10K50ETC144-1 EPF20K EP20K100E EP20K60E EPF10K100EQC208-1
Text: = 50 The MAX + PLUS II software was used to compile the top level file, VSAA.TDF. The target device , = 0 GE= 0 GF= 0 GG= 0 BMGWIDE= 15 V= 360 The MAX + PLUS II software was used to compile the top , + PLUS , MAX + PLUS II and Quartus are trademarks and/or service marks of Altera Corporation in the United , BMGWIDE= 14 V= 35 The Altera MAX+PLUS® II Software was used to compile the top level file, VSAA.TDF. The , GD= 0 GE= 0 GF= 0 GG= 0 BMGWIDE= 14 V= 100 The MAX+PLUS II software was used to compile the top


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PDF APEXTM20K, EPF10K30ETC144-1 EPF10K50ETC144-1 EPF20K EP20K100E EP20K60E EPF10K100EQC208-1
Not Available

Abstract: No abstract text available
Text: . MAX+PLUS II Timing Analyzer MAX+plus II File MAX * plus II - c:\max2worlflchiptrip\chiptrip ^ode A nalysis , devices is provided by Altera's PLD shell Plus software.) The M A X + P L U S II Message Processor , Figure 9, uses programming files generated by the M A X + P L U S II Com piler or PLD shell Plus compiler , MAX+PLUS II ® Programmable Logic Development System & Software Introduction Ideally, a , use the design entry methods and tools of their choice. The Altera M A X + P L U S II development


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Quartus II Handbook

Abstract: QII51002-7 Quartus II Simulator
Text: assignments can be imported incorrectly from the MAX + PLUS II software into the Quartus II software due to , 3. Quartus II Design Flow for MAX+PLUS II Users QII51002-7.1.0 Introduction The feature-rich Quartus® II software helps you shorten your design cycles and reduce time-to-market. With support for FLEX®, ACEX®, and MAX ® device families, as well as all of Altera®'s newest devices, the Quartus II software is the most widely accepted Altera design software tool today. This chapter describes


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PDF QII51002-7 Quartus II Handbook Quartus II Simulator
2010 - F487 transistor

Abstract: 2A86 transistor D889 65e9 F487 4B71 ix 2933 65e9 transistor 529B 3d0c
Text: logo, MAX , MAX+PLUS, MAX+PLUS II , MegaCore, NativeLink, Quartus, Quartus II , the Quartus II logo, and , . 16 Setting up the Quartus II Software with a JTAG Server on a Network . 17 Using the 64-bit Version of the Quartus II Software for Linux . 17 , Starting the Quartus II Software . 20 Starting the Quartus II Software in Windows. 20


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PDF MNL-01054-1 F487 transistor 2A86 transistor D889 65e9 F487 4B71 ix 2933 65e9 transistor 529B 3d0c
vhdl code for fifo

Abstract: vhdl code mips code V320USC
Text: Altera's Max + plus II software and the EPM7032AELC44-5 PLD4. However, only high speed grade FPGA will


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PDF MCF5307 V320USC vhdl code for fifo vhdl code mips code
ALU IC 74381

Abstract: encoder IC 74147 16CUDSLR 74139 truth table ic 7447 truth table alu 74382 truth table for 7446 from IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
Text: Figure 4. MAX * PLUS II Waveform Editor M A Xtplus II MAX+plus 1- E:\MAX2W0RK\TUT0RIAHT-BIRD - [W avelorm , PLDS-HPS, PLS-HPS, PLS-OS & PLS-ES A N & r * a \ MAX+PLUS II Programmable Logic Development System & Software Data Sheet S eptem ber 1991, ver. 1 U U M A X + P L U S II is the , P L D s . M A X + P L U S II runs u n d er M icro so ft W in d o w s versio n 3.0 to p ro v id e a h , cap a b ility, and extensive p rin te r/ p lo tte r support. U M A X + P L U S II offers


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PDF 486-based 12-ms 44-Mbyte, ALU IC 74381 encoder IC 74147 16CUDSLR 74139 truth table ic 7447 truth table alu 74382 truth table for 7446 from IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
1998 - electret condenser microphone preamplifier

Abstract: TMS320c6x EVM SPRU269C SN74ACT8990 74act8990 SFM140L2SDLC TMS320C6X programmable multi pulse waveform generator cpld electret condenser microphone element mge service manual
Text: Corporation. Altera, ByteBlaster, and MAX + PLUS are trademarks of the Altera Corporation. AMCC is a , interface) TL750L05 5 V voltage regulator 4-pin Molex ext. power connector 5V (150 mA MAX , 2-pin fan power connector PT6502B 1.8/2.5 VDC voltage regulator 3.3 V (3A MAX ) 40 or , ) 1.8/2.5 V Red CE0 CE2 VDD3 LED1 Red 2.5/1.8 V (8A MAX ) 33.25 or 25 MHz Addr , SDCLK Digital 3.3 V Power sequence control Note: 3A Max . option From/to CPLD PLDCLK


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PDF TMS320C6201/6701 SPRU305 Win32 Index-10 electret condenser microphone preamplifier TMS320c6x EVM SPRU269C SN74ACT8990 74act8990 SFM140L2SDLC TMS320C6X programmable multi pulse waveform generator cpld electret condenser microphone element mge service manual
2009 - datasheet mb 8719

Abstract: d67b b548 altera jtag ethernet AMD64 altera board b824 B824 transistor VHDL code for generate sound D896
Text: logo, MAX , MAX+PLUS, MAX+PLUS II , MegaCore, NativeLink, Quartus, Quartus II , the Quartus II logo, and , Downloaded Software with the Linux Install Script . 15 Installing the Quartus II Web Edition Software for , . 23 Setting up the Quartus II Software with a JTAG Server on a Network . 23 Using the 64-bit Version of the Quartus II Software on Linux. 24 , . 27 Development Kits Containing the Quartus II Software. 29 Non-Licensed Software


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PDF MNL-01050-1 datasheet mb 8719 d67b b548 altera jtag ethernet AMD64 altera board b824 B824 transistor VHDL code for generate sound D896
74LS181

Abstract: No abstract text available
Text: 1 F=(A-B) PLUS AB PLUS 1 F= A MINUS B IC O < II u. F=A PLUS AB PLUS 1 F=A PLUS B PLUS 1 F=(A+B) PLUS AB PLUS 1 F=AB F=A PLUS A PLUS 1 F=(A+B) PLUS A PLUS 1 F=(A+B) PLUS A PLUS 1 F=A < II U. F= 1 II , SWITCHING CHARACTERISTICS VCC = 5V. TA - 25° C 54/74 TRUTH TABLE INPUTS £ OF 1'» AT 0 THRU 7 EVEN MAX , P 17 Y G i l il i l II n n n n I l II « 1 1 u LLLLLLLL ninni i rr m t I ? r , FUNCTIONS F -Â F=A+B F=AB F=0 F=ÀB F=B F= A © B F=AB F=A+B F=A © B TÏ II G D F=A F=A+B F=A+B F=MINUS 1 (2


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PDF 400S2 74LS181
MEP-12T user manual

Abstract: MEP-12T tyco mep 6t smd 718 ASG TYCO BMEP-5T bmep 3t bmep 5t pc104 press fit connector bmep-5t
Text: 1.02-0.98 for PC/104- Plus Connectors Pad Diameter ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÏÏ ÉÉ ÌÌ ÉÉÉÉÏÏ ÉÉ ÌÌ , Connectors and 1.06-1.02 for PC/104- Plus Connectors Pad Diameter as Required ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÌÌ , 1.06-1.02 for PC/104- Plus Pad Diameter as Required ÉÉÉÉÉÉ ÉÉÉÉÉÌÌ É ÉÉÉÉÉÏÏ É ÌÌ ÉÉÉÉÉÏÏ É ÌÌ , Application Specification 114-13021 PC/104 and PC/104- Plus Connectors NOTE i 12 APR , PC/104­ Plus Connectors. These connectors are available with press­fit and solder contact versions


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PDF PC/104 PC/104-Plus MEP-12T user manual MEP-12T tyco mep 6t smd 718 ASG TYCO BMEP-5T bmep 3t bmep 5t pc104 press fit connector bmep-5t
2001 - Not Available

Abstract: No abstract text available
Text: Module – Ares II 3D- Plus , reserves the right to change products or specifications without notice.  , SHEET PIN ASSIGNMENT FUNCTIONAL BLOCK DIAGRAM SDRam Memory Module – Ares II 3D- Plus , reserves , Module – Ares II 3D- Plus , reserves the right to change products or specifications without notice.  , Memory Module – Ares II 3D- Plus , reserves the right to change products or specifications without , . SDRam Memory Module – Ares II 3D- Plus , reserves the right to change products or specifications


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PDF 32Mx64-BGA 3DSD2G64VB4383 32Mx64, 32Mx16 512Mbit 32Mx64bit. 133Mhz 3DDS-0383-2
54S181

Abstract: No abstract text available
Text: = Sa = 4.5V Diff Mode, see Waveform 3 and Table II LIMITS Cu = 15pF Max 10.5 10.5 12 12 12 12 , FEATURES · Provides 16 arithmetic operations: ADD, SUBTRACT, COMPARE, DOUBLE, plus 12 other arithmetic , , plus 10 other logic operations · Full lookahead carry for high-speed arithmetic operation on long words , A+B A Arithmetic * (M s L M C ^ H ) A A+B A+B minus 1 A plus AB (A + B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A + B) plus AB AB minus 1 A plus A* (A + B) plus A (A + B) plus A A minus 1


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PDF 54S181 54S181 54SXXX 500ns 1N916 1N3064,
2001 - Not Available

Abstract: No abstract text available
Text: Module – Ares II 3D- Plus , reserves the right to change products or specifications without notice.  , SHEET PIN ASSIGNMENT FUNCTIONAL BLOCK DIAGRAM SDRam Memory Module – Ares II 3D- Plus , reserves , Module – Ares II 3D- Plus , reserves the right to change products or specifications without notice.  , Memory Module – Ares II 3D- Plus , reserves the right to change products or specifications without , . SDRam Memory Module – Ares II 3D- Plus , reserves the right to change products or specifications


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PDF 32Mx64-BGA 3DSD2G64VB4383 32Mx64, 32Mx16 512Mbit 32Mx64bit. 133Mhz 3DDS-0383-2
Application Notes SN74181

Abstract: 8 BIT ALU by 74181 74181 ALU texas SN74181 74181 pin configuration 74181 Application Notes SN74182 SN74182 SN54181 G322
Text: Operating Modes: • Addition Subtraction Shift Operand A One Position Magnitude Comparison Plus Twelve , . 12 ns Logic Function Modes: Exclusive-OR Comparator AND, NAND, OR, NOR Plus Ten Other Logical , +4 X Y Active-low data (Figure II ) AO BO A1 B1 a2 b2 A3 B3 FO TÏ F2 n Cn Cn+4 T fr Subtraction is , designations as shown in Figures I or II . The logic functions and arithmetic operations obtained with signal designations as in Figure I are given in Table I; those obtained with the signal designations of Figure II are


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PDF SN54181, SN74181 SN74182 SN54182 64-BIT Application Notes SN74181 8 BIT ALU by 74181 74181 ALU texas 74181 pin configuration 74181 Application Notes SN74182 SN54181 G322
tl 501 cn

Abstract: No abstract text available
Text: Plus 1 F = A B Plus A P lus 1 F = A B Plus A Plus 1 F = A Plus 1 T1 LL II II * Each bit is , 1 (2's Compì) F = A Plus (AB) F = (A + B) Plus AB F = CD T l II * Each bit is shifted , ) Plus A B Plus 1 F = AB F = A Plus A Plus 1 F = (A + B) Plus A P lus 1 F = (A + B) Plus A Plus 1 II , SPEED tPD = 13 ns (TYP.) AT Vcc = 5 V LOW POWER DISSIPATION Icc = 4 nA ( MAX .) at Ta = 25 "C HIGH NOISE , (with carry) F = A M inus 1 F = AB M inu s 1 F = A B M inus 1 F = M inus 1 (2's C om pì) F = A Plus (A


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PDF 54/74LS181 74HC181 S-10041 M74HC181 tl 501 cn
74ACT11181

Abstract: No abstract text available
Text: ) < II F = A MINUS 1 F = AB MINUS 1 F = AB MINUS 1 F = MINUS 1 (2's COMP) F = A PLUS (A + B) F = AB , B) F = A PLUS A t F = AB PLUS A F = AB PLUS A < 1 1 U. C O < <9 II II u. u. F = ZERO F = A PLUS , PLUS 1 F = AB PLUS A PLUS 1 F = A PLUS 1 F=A® B F=B F=A +B F=0 F = AB < < II II U. UCD Table 2 , is shifted to the next more significant position. < II A F = A PLUS A PLUS 1 F F = = II (A (A + + B) PLUS A PLUS 1 B) PLUS A PLUS 1 + B (A + B) PLUS A A MINUS 1 < II u


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PDF 74ACT11181 SCAS086 D3200, 500-mA
Not Available

Abstract: No abstract text available
Text: LL F=A © B F= B F=A + B F= 0 F = AB C Û < I " IL. F=A r F = AB Plus A LÜ1 < II F = AB Plus A Plus 1 F , A Plus (A + B) F = A Plus B F = AB Plus (A + B) F=A + B F = A Plus A * F = AB Plus A IL II h Cn = H (w ith carry) < II i F = Zero F = A Plus (A + B) Plus 1 F = AB Plus (A + B) Plus 1 F = A Minus B , ) Plus A Plus 1 II LL 17 F= B F=A© B F = AB F=A + B F=A © B F= B II U .| F= 1 F=A + B F= A + B , GENERATOR HIGH SPEED tP D = 13 ns (TYP.) AT Vcc = 5 V LOW POWER DISSIPATION Icc = 4 (jA ( MAX .) at TA = 25


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PDF M74HC181 54/74LS181 74HC181M 74HC181B1R 74HC181 S-10041 GDS4703 c32tiE37
Not Available

Abstract: No abstract text available
Text: position Magnitude comparison Plus 12 other arithmetic operations · Logic function modes: ' Exclusive-OR Comparator AND, NAND, OR, NOR Plus 10 other logic operations · Full look-ahead for high-speed operations on , ) F" A F -A B F=AB F=Zero F=A Plus (A + B) Plus 1 F=AB Plus (A + B) Plus t . F=A Minus B F -(A + B ) Plus 1 ' F=A Plus (A + B) Plus 1 F -A Plus B Plus 1 F=AB Plus (A + B) Plus 1 F=(A + B) Plus 1 F=A Plus A Plus 1 F=AB Plus A Plus 1 F=AB Plus A Plus 1 F=A Rus 1 S2 L L L L H H H H L L L L H H H H SI


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PDF KS54HCTLS KS74HCTLS 7Tb414S 90-XO 14-Pin
Supplyframe Tracking Pixel