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RH1034MW-1.2 Linear Technology Micropower Dual Reference
RH1009H Linear Technology IC 1-OUTPUT TWO TERM VOLTAGE REFERENCE, MBCY3, TO-46, 3 PIN, Voltage Reference
LTC6652BHMS8-2.5 Linear Technology IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 2.5 V, PDSO8, PLASTIC, MSOP-8, Voltage Reference
LT1019ACN-4.5 Linear Technology IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 4.5 V, PDIP, Voltage Reference
LT1019CN-5 Linear Technology IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 5 V, PDIP, Voltage Reference
LT1019IS-5 Linear Technology IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 5 V, PDSO, Voltage Reference

MACH110 cross reference Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1996 - PAL22V16

Abstract: MACH110 MACH210 MACH215 PAL22V10
Text: FINAL COM'L: -12/15/20 IND: -14/18/24 MACH110 -12/15/20 Lattice/Vantis High-Density , GENERAL DESCRIPTION The MACH110 is a member of our high-performance EE CMOS MACH 1 family. This device , speed. The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two , routed efficiently. The MACH110 macrocell provides either registered or combinatorial outputs with , /O31 2 MACH110 -12/15/20 CLK1/I5, CLK0/I2 14127I-1 CONNECTION DIAGRAM Top View I/O0


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PDF MACH110-12/15/20 PAL22V16" MACH111, MACH210, MACH211, MACH215 MACH110 PAL22V10 PAL22VQ2 PAL22V16 MACH210 MACH215
Not Available

Abstract: No abstract text available
Text: FINAL COM’L: -12/15/20 IND: 14/18/24 a MACH110 -12/15/20 High-Density EE CMOS , – Pin-compatible with MACH210, MACH215 ■2 “PAL22V16” Blocks GENERAL DESCRIPTION The MACH110 is a , the logic macrocell capability of the popular PAL22V10 with no loss of speed. The MACH110 consists , _ The MACH110 macrocell provides either registered or combinatorial outputs with programmable polarity , . AMD BLOCK DIAGRAM lo - ll, l/Oo - I/O 15 I/Oie -1/031 MACH110 -12/15/20 025752b 0035535


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PDF MACH110-12/15/20 MACH210, MACH215 PAL22V16â MACH110 PAL22V10 QS5752ta
Not Available

Abstract: No abstract text available
Text: "T- ll-Q)r] MIL: -20 MACH110 -12/15/20 High-Density EE CMOS Programmable Logic Advanced , Amendment/0 Issue Dale: A p rili 993 _ The MACH110 macrocell provides either , €” , 11 b -14 I/O16 —I/O31 CLK1/I5. CLKo/l2 12 MACH110 -12/15/20 ,4,27-g -! bOE D , MACH110 -12/15/20 13 bOE D ■023752b 0033011 T71 ■AND2 ADV MICRO PLA /PLE/ARRAYS AMD , ) Valid Combinations MACH110 -20 H OPERATING CONDITIONS C = Commercial (0°Cto +75°C) DEVICE


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PDF G033QÃ MACH110-12/15/20 MACH210, MACH215 PAL22V16â ACH110 PAL22V10
1995 - mach 1 family amd

Abstract: PAL22V16 MS1028 mach 1 to 5 from amd PAL22V10 MACH215 MACH210 MACH110 teradyne lasar MACH110 12JC 14JI
Text: FINAL COM'L: -12/15/20 IND: -14/18/24 Advanced Micro Devices MACH110 -12/15/20 , Inputs GENERAL DESCRIPTION The MACH110 is a member of AMD's high-performance EE CMOS MACH 1 family , without loss of speed. The MACH110 consists of two PAL blocks interconnected by a programmable switch , placed and routed efficiently. The MACH110 macrocell provides either registered or combinatorial , 16 I/O16 ­ I/O31 2 MACH110 -12/15/20 CLK1/I5, CLK0/I2 14127I-1 AMD CONNECTION


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PDF MACH110-12/15/20 PAL22V16" MACH111, MACH210, MACH211, MACH215 MACH110 PAL22V10 44-Pin mach 1 family amd PAL22V16 MS1028 mach 1 to 5 from amd MACH215 MACH210 teradyne lasar MACH110 12JC 14JI
Not Available

Abstract: No abstract text available
Text: – 77 MHz fcNT ■38 Inputs GENERAL DESCRIPTION The MACH110 is a member of AMD’s , capability of the popular PAL22V10 without loss of speed. The MACH110 consists of two PAL blocks intercon , fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH110 macrocell , DIAGRAM lo - 11. l/Oo - 1/015 l3 - 14 l/016 -1/031 CLK 1/I 5 , CLK0/I 2 MACH110 -12/15 , I = Input I/O = Input/Output Vcc = Supply Voltage MACH110 -12/15/20 0257S2b


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PDF 32Macrocells PAL22V16â MACH111, MACH210, MACH211, MACH215 MACH110 PAL22V10 MACH110-12/15/20
Not Available

Abstract: No abstract text available
Text: – 38 Inputs G E N E R A L D E S C R IP T IO N The MACH110 is a memberof AMD’s high-performance , of the popular PAL22V10 at an equal speed with a lower cost per macrocell. The MACH110 consists of , allows designs to be placed and routed efficiently. The MACH110 macrocell provides either registered or , li, l/ O o - I/O 15 I/O 16 - I/O 31 I3 - I 4 C L K 1/I 5, C LK 0/I 2 12 MACH110 , Input I/O Input/Output Vcc Supply Voltage 14127-002A MACH110 -12/15/20 13 C l AMD O R


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PDF PAL22V16â MACH210 MASC110 MACH110 PAL22V10 MACH110-12/15/20
1996 - PAL22V16

Abstract: MACH110 MACH210 MACH215 PAL22V10 AIR33
Text: FINAL COM'L: -12/15/20 IND: -14/18/24 MACH110 -12/15/20 Lattice Semiconductor , Inputs GENERAL DESCRIPTION The MACH110 is a member of our high-performance EE CMOS MACH 1 family , without loss of speed. The MACH110 consists of two PAL blocks interconnected by a programmable switch , placed and routed efficiently. The MACH110 macrocell provides either registered or combinatorial , I/O16 ­ I/O31 2 MACH110 -12/15/20 CLK1/I5, CLK0/I2 14127I-1 CONNECTION DIAGRAM Top


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PDF MACH110-12/15/20 PAL22V16" MACH111, MACH210, MACH211, MACH215 MACH110 PAL22V10 14127I-26 PAL22V16 MACH210 MACH215 AIR33
PAL 002a

Abstract: PAL 010a pal 007a PAL 006A MACH110-15JC pal 005a MACH110-15 MACH110 MACH110-20JC PAL22V10
Text: COM'L: -15/20 MIL: -20 CI MACH110 -15/20 High-Density EE CMOS Programmable Logic Advanced , 2 "PAL22V16" Blocks GENERAL DESCRIPTION The MACH110 is a memberof AM D's high-performance EE CMOS , PAL22V10 at an equal speed with a lower cost per macrocell. The MACH110 consists of two PAL blocks , PAL blocks. This allows designs to be placed and routed efficiently. The MACH110 macrocell provides , Voltage t4127-002A MACH110 -15/20 11 This Material Copyrighted By Its Respective Manufacturer AMD 2H


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PDF MACH110-15/20 PAL22V16" MACH110 PAL22V10 2350-024A PAL 002a PAL 010a pal 007a PAL 006A MACH110-15JC pal 005a MACH110-15 MACH110-20JC
Not Available

Abstract: No abstract text available
Text: fMAx Commercial 40 MHz (m a x Military 2 “PAL22V16” Blocks GENERAL DESCRIPTION The MACH110 , per macrocell. The MACH110 consists of two PAL blocks intercon­ nected by a programmable switch , and routed efficiently. The MACH110 macrocell provides either registered or combinatorial outputs , -1/O 3 1 I3 - U C L K 1/ I5 14127-001B 10 MACH110 -15/20 AMD CONNECTION DIAGRAM , I Input I/O Input/Output Vcc Supply Voltage MACH110 -15/20 14127-002A 11


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PDF PAL22V16â MACH110 PAL22V10 MACH110-15/20
1996 - 5962-8515505RX

Abstract: 7C291 81c78 27PC256-12 8464C PAL164A 39C10B 5C6408 72018 MACH110 cross reference
Text: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C , Product Line Cross Reference ALTERA CYPRESS ALTERA CYPRESS AMD CYPRESS 5032PC-2 , Product Line Cross Reference AMD 27S291AC 27S291AM 27S291C 27S291M 27S291SAC 27S291SAM 27S35AC , PALCE22V1020DMB PALCE22V1025LMB Product Line Cross Reference AMD CYPRESS AUSTIN PALCE22V10H25/BLA , Cross Reference FUJITSU 81C86-70 8287-35 8287-45 8299 8464L-70 8464L-100 HARRIS PREFIX


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PDF 2147-35C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35M 2148-45C 5962-8515505RX 7C291 81c78 27PC256-12 8464C PAL164A 39C10B 5C6408 72018 MACH110 cross reference
Not Available

Abstract: No abstract text available
Text: Input/Output Vcc = Supply Voltage MACH110 -12/15/20 13 C l AMD ORDERING INFORMATION , availability of specific valid co m bin a tion s and to ch eck on newly re­ leased com binations. MACH110 , valid co m bin a tion s and to ch e c k on new ly re­ leased com binations. MACH110 -20 (Mil) 15 , The MACH110 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL , . The I/O Cell The I/O cell in the MACH110 consists of a three-state output buffer. The three-state


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PDF PAL22V16â MACH210, MACH215 MACH110-12/15/20
Not Available

Abstract: No abstract text available
Text: PAL22V10 without loss of speed. The MACH110 consists of two PAL blocks intercon­ nected by a , check on newly released combinations. MACH110 -12/15/20 (Com’l) ORDERING INFORMATION Industrial , Switch Matrix The MACH110 switch matrix is fed by the inputs and feedback signals from the PAL blocks , device. The Product-Term Array The MACH110 product-term array consists of 64 product terms for logic , and preset product terms. The I/O Cell The I/O cell in the MACH110 consists of a three-state


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PDF PAL22V16â MACH111, MACH210, MACH211, MACH215 PAL22V10 MACH110 44-Pin MACH110-12/15/20 16-038-SQ
Not Available

Abstract: No abstract text available
Text: logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH110 consists of two , MACH110 -12/15/20 3 C I AMD ORDERING INFORMATION Commercial Products AMD programmable logic , to check on newly released combinations. MACH110 -12/15/20 (Com’l) AMD C l ORDERING , Matrix The MACH110 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each , device. The Product-Term Array The MACH110 product-term array consists of 64 product terms for logic


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PDF PAL22V16â MACH111, MACH210, MACH211, MACH215 ACH110 PAL22V10 MACH110 44-Pin 16-038-SQ
Not Available

Abstract: No abstract text available
Text: CO M ’L: -12/15/20 MIL: -20 MACH110 -12/15/20 High-Density EE CMOS Programmable Logic , MACH110 consists of two PAL blocks intercon­ nected by a program m able switch matrix. The two PAL , I/O = Input/Output Vcc = Supply Voltage MACH110 -12/15/20 13 i l AMD ORDERING , on new ly re­ leased com binations. MACH110 -12/15/20 (Com’l) AMD Ü ORDERING INFORMATION , com bin a tion s. MACH110 -20 (Mil) 15 AMD FUNCTIONAL DESCRIPTION Table 5. Logic


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PDF MACH110-12/15/20 PAL22V16â MACH210, ACH215 PAL22V10 MACH110
1995 - pal16v8

Abstract: MACH Technical Briefs Manual 79C960 MACH110 cross reference PAL 16V8 motorola 68000 microprocessor motorola SEMICONDUCTOR APPLICATION NOTE amd 29000 M68000FR motorola 68000
Text: ; odd-addressed bytes reference data on the low-byte data lines D<0­7>, even-addressed bytes on the high-byte , little-endian machine, where evenaddressed bytes reference data on the low-byte data lines D<0­7> and , the PCnet-ISA controller point of reference ) and all remaining evenaddressed data-bytes are shifted , (minimum) for a 50 ns MEMW cycle minimum 9. The MACH110 design is partitioned into six major , Application Examples 5 AMD 6. M68000 Family Reference , 1990, Motorola Reference # M68000FR/AD


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PDF MC68000 pal16v8 MACH Technical Briefs Manual 79C960 MACH110 cross reference PAL 16V8 motorola 68000 microprocessor motorola SEMICONDUCTOR APPLICATION NOTE amd 29000 M68000FR motorola 68000
Texas Instruments TTL

Abstract: mach devices applications handbook IC 4024 AMD socket 938 PIN diagram video sender circuit diagram BB105 50C11 rx2-1110 commodore t/51511d150/fw/a/buy/mach210 die
Text: minimizes the number of signals that cross the boundary of that block. A second MACH110 , with similar , . 1-24 Chapter 2 Psion Organizer Digital Interface: MACH110 , Transm ission: MACH110 and MACH210 . 5-1 5-4 5-10 5-17 5-20 , . Chapter 6 Self-Timing ISA Bus Interface: MACH110 and M AC H 210. Ulrich , -pin MACH110 , to the 84-pin MACH230. The majority of these designs were obtained from European customers that


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PDF DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 Texas Instruments TTL mach devices applications handbook IC 4024 AMD socket 938 PIN diagram video sender circuit diagram BB105 50C11 rx2-1110 commodore t/51511d150/fw/a/buy/mach210 die
1991 - mach 3 family amd

Abstract: MACH110 CNT15UP F050 mach 1 family amd
Text: product terms can be eliminated. One asynchronous reset PT is available per MACH110 block. In this , are required to implement it in a MACH110 device. The maximum clock speed of the counter is reduced , on the 70% recommended utilization guideline, it appears this design will fit in a MACH110 device , partitioning steps. MACH Device Design Planning Guide Resource Used MACH110 Utilization Pins , guidelines and should fit in a MACH110 device. Note: In this brief, a detailed pre-entry analysis of the


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PDF DIV16 CNT15DN PULSE16 mach 3 family amd MACH110 CNT15UP F050 mach 1 family amd
PAL26V16

Abstract: mach 1 family
Text: CO ND ENSED COM'L: -5/7.5/10/12/15/20 MACH111-5/7/10/12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 44 Pins 32 Macrocells 5 ns tpD 167 MHz f c u t 38 Bus-FriendlyTM Inputs Peripheral Component Interconnect (PCI) compliant A d v a ^ Devices Programmable power-down mode 32 Outputs 32 Flip-flops; 4 clock choices 2 "PAL26V16" Blocks Pin-compatible with MACH110 , MACH210, MACH211, MACH215 Improved routing over the MACH110 GENERAL DESCRIPTION The MACH111 is a


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PDF MACH111-5/7/10/12/15/20 PAL26V16" MACH110, MACH210, MACH211, MACH215 MACH110 MACH111 PAL22V10 PAL26V16 mach 1 family
mach 1 family amd

Abstract: MACH110
Text: Device Families CONDENSED FINAL COM’L: -12/15/20 MIL: -20 MACH110 -12/15/20 High-Density , DESCRIPTION The MACH110 is a memberof AMD's high-performance EE CMOS MACH 1 family. This device has approxi , MACH110 consists of two PAL blocks intercon­ nected by a programmable switch matrix. The two PAL blocks , routed efficiently. Publication# C14127 Rev. G Issue Date: June 1993 Amendment/0 The MACH110 , 2 3-8 MACH110 -12/15/20 C14127G-1 CONDENSED FINAL MACH120-15/20 High-Density EE CMOS


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PDF MACH215 I/O8-I/O15 C16751C-1 MACH215-12/15/20 mach 1 family amd MACH110
Not Available

Abstract: No abstract text available
Text: PA-MACH44(Z)(-LD) Data Sheet 44 pin PLCC socket/28 pin DIP 0.6” plug Supported Device/Footprints Adapter Construction Using this adapter, the AMD MACH110 , 210 & 215 in either PLCC or CLCC package can be programmed on DIP programmers. The PA-MACH44-LD is for use with the Logical Devices AllPro programmer. The adapter is made up of 3 sub-assemblies. They assemble via connectors making the adapter modular. This way the subassemblies can be replaced easily. Mfgr AMD Device Device


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PDF PA-MACH44 socket/28 MACH110, PA-MACH44-LD 28-170-LDM44. PA-MACH44Z PA-MACH44 PA-MACH44-LD PA-MACH44Z-LD
2001 - MACH211-15JC

Abstract: mach210-15jc Mach445-15yc GAL20V8C-10LJ GAL22V10D-15LS GAL16V8D-25LP GAL16V8D PALCE16V8H-10JC/4 MACH210-12JC GAL16V8D 15LP datasheet
Text: -192/160-12YC M5-192/160-12YI M5-192/160-15YC M5-192/160-15YI M5-192/160-20YI M5-192/160-7YC MACH110 -12JC MACH110 -14JI MACH110 -15JC MACH110 -18JI MACH111-10JC MACH111-10JI MACH111-10VC MACH111-12JC MACH111


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PDF 10A-01 PALLV16V8Z-20JI PALLV16V8Z-20PI PALLV22V10-10PC PALLV22V10-15JI PALLV22V10-15PC PALLV22V10Z-25JI PALLV22V10Z-25PI MACH211-15JC mach210-15jc Mach445-15yc GAL20V8C-10LJ GAL22V10D-15LS GAL16V8D-25LP GAL16V8D PALCE16V8H-10JC/4 MACH210-12JC GAL16V8D 15LP datasheet
PAL26V16

Abstract: No abstract text available
Text: CONDENSED COM'L: -7.5/10/12/15/20 IND: -10/12/14/18/24 MACH211-7/10/12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 44 Pins 64 Macrocetls 7.5 ns tp D Commercial 10 ns tro Industrial 133 MHzfcNT 38 Bus-Friendly inputs and l/Os Peripheral Component Interconnect (PCI) compliant A d v a M n ^ Devices Programmable power-down mode 32 Outputs 64 Flip-flops; 4 clock choices 4 "PAL26V16" blocks with buried macrocells Pin-compatible with MACH110 , MACH111


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PDF MACH211-7/10/12/15/20 PAL26V16" MACH110, MACH111, MACH210, MACH215 MACH210 MACH211 C1M01 PAL26V16
1995 - MACH110

Abstract: TXC-05501 TXC-05601 Transwitch SARA-R 010ns
Text: parity bit over TxData[7:0], driven by the ATM Layer. TxRef*: Transmit Reference . Input to the PHY layer , 4 of 14 RxRef*: Receive Reference . Output from the PHY Layer for synchronization purposes (e.g , Tx Interface Clk The Tx Control Logic was implemented in a PLD, an AMD MACH110 . The PLD , Javier C. Berrios COMPANY TranSwitch Corporation DATE 03/28/95 CHIP _saras2ut MACH110 , COMPANY TranSwitch Corporation DATE 03/29/95 CHIP _sarar2ut MACH110 ;-


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PDF TXC-05501-0002-AN MACH110 TXC-05501 TXC-05601 Transwitch SARA-R 010ns
mach 1 to 5 from amd

Abstract: pal programmer schematic mach 1 to 5 family amd mach 1 family amd Simulating MACH Designs MACH110 "pin compatible" MACH Programmer MACH231
Text: power savings of up to 75% The MACH111, MACH211, and MACH231 have improved routing over the MACH110 , Max Inputs Max Outputs Max Flip-Flops Speed (ns) MACH110 MACH111 (SP) MACH 120 MACH130 MACH 131


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PDF 5/7/10/12/15/20-ns 6/50-MHz MACH111, MACH131, MACH211, MACH221, MACH231 mach 1 to 5 from amd pal programmer schematic mach 1 to 5 family amd mach 1 family amd Simulating MACH Designs MACH110 "pin compatible" MACH Programmer
MACH Technical Briefs Manual

Abstract: amd 44 MACH210
Text: for high-volum e applications PRODUCT SELECTOR GUIDE Device MACH 1 Family MACH110 MACH120 MACH 130 , ent form s for efficient logic implementation. Table 1. PAL Block Inputs Device MACH110 MACH 120 MACH , input to the same device. Table 3. Macrocell Clocks Device MACH110 MACH120 MACH130 MACH210 MACH220 , MACH110 -12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 44 Pins 32 M , routed efficiently. The MACH110 macrocell provides either registered or combinatorial outputs with


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PDF 14051G, 14051H, ACH220-12 ACHLV210 MACH Technical Briefs Manual amd 44 MACH210
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