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Part Manufacturer Description Datasheet Download Buy Part
MA-23 Curtis Industries CONN BARRIER STRIP 23CIRC 0.5
MA230.LBC.002 Taoglas Antenna Solutions ANT LTS/GSM/UMTS
MMA2301KEG NXP Semiconductors SPECIALTY ANALOG CIRCUIT, PDSO16
MMA2301KEGR2 NXP Semiconductors SPECIALTY ANALOG CIRCUIT, PDSO16
MMA23-0141Q1 Vishay Dale CONN RACK/PANEL 14POS 5A
MMA23-0201S1 Vishay Dale CONN RACK/PANEL 20POS 5A

MA23 B Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2008 - IEPE

Abstract: iepe circuit MA23 honeywell Accelerometer
Text: Model MA23 Accelerometer DESCRIPTION The Model MA23 subminiature amplified piezoelectric acceler , studies, and structural monitoring. The constant current The model MA23 would normally be mounted to , adhesive. The model MA23 can be supplied high load capacitance allows long runs of low cost cable without with different cable lengths. degradation of data. The Model MA23 features a high natural , Model MA23 PERFORMANCE SPECIFICATIONS OPTION CODES Characteristic Measure Dynamic range


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PDF 008738-1-EN IEPE iepe circuit MA23 honeywell Accelerometer
2002 - PXA250

Abstract: "memory controller" sdram controller MA23 sdram pcb schematics MA23 B SDRAM controller 32bit 16MB
Text: Device B nSDCS0 MA23 nSDCS0 MA23 32MB 11 11 32MB 10 10 32MB 01 01 32MB 00 00 x16 x16 nSDCS1 nSDCS0 Connect Signals: nSDCS0 to BS1 MA23 to BS0 , ] PXA250 Applications Processor MA23 BS0 BS1 DQM[3.0] U1 U2 nCAS nRAS nWE MD[31.0 , ] MA23 A[12:0] BS0 BS1 U3 nCAS nRAS nWE CLK CKE nCS 8 Application Note 278532-001


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PDF PXA250 PXA250 "memory controller" sdram controller MA23 sdram pcb schematics MA23 B SDRAM controller 32bit 16MB
4MD01

Abstract: OTI-043
Text: B HSYNC VSYNC P[7:0] FRAME SHFCK LP FSYNC WGTCK MD01[15:0] MA01[7:0] MA23 [7:0] MA01/WE01 Hn , ] DACRDn DACWn PCLK BLANKn Rn WRn PCLK BLANKn P[7:0] R Ü B HSYNC VSYNC P[7:0] FRAME LP FSYNC WGTCK MD01|15:0] MA01[7:0] MA23 [7:0] MA01/WE01Hn MA23 /WE23Hn RASn CASAn WE01n WE23n MD01[3:0] DQ[3:0] RASn , BLANKn P[7:0] HSYNC VSYNC P[7:0] FRAME SHFCK LP FSYNC WGTCK MD01[15:0] MA01[7:0] MA23 [7:0] RASn , MCLK CSEL[1:0 CASAn WE01n MA01/WE01Hn WE23n MA23 /WE23Hn CAS Bn MD23[15:0] CASn D Q [3:0


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PDF OTI-043 WE023n MA/WE01Hn MA/WE23Hn 4MD01 OTI-043
WE01

Abstract: lcd ibm monitor circuit diagram crt monitor block diagram OTI-040 OTI-043 laptop lcd to vga laptop lcd display interface MA23 ramdac 800 600 vga Oak Technology
Text: HSYNC VSYNC VCLK MCLK CSEI41:0] MD01[15:0] M A01 [7:0] MA23 [7:0] MA01/WE01Hn MA23 /WE23Hn RASn CASAn , LP FSYNC WGTCK MD01[15:0] MA01 [7:0] MA23 [7:0] RASn CASAn WE01n MA01/WE01Hn WE23n MA23 /WE23Hn , WGTCK MD01[15:0] MA01 [7:0] MA23 [7:0] MA01/WE01 Hn MA23 /WE23Hn RASn CASAn WE01n WE23n PWCTL[1:0] MD23 , lOWn P[7:0] I016n FRAME VGARDY RFSHn SHFCK CINTn FSYNC WGTCK MD01[15:0] MA01[7:0] MA23 [7:0] VCLK RASn MCLK CASAn CSEL[1:0] WE01n MA01/WE01 Hn WE23n MA23 /WE23Hn CASBn MD23


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PDF QTI-043 WE01 lcd ibm monitor circuit diagram crt monitor block diagram OTI-040 OTI-043 laptop lcd to vga laptop lcd display interface MA23 ramdac 800 600 vga Oak Technology
80386 chipset

Abstract: OTI-087 TL016 CHIPset for 80286 160X64 CACHE MEMORY FOR 80386DX 8X16 640X480 PAL16L8-20 oak capacitance
Text: 80386DX/80486 block diagrams following this section. The OTI-087 requires four buffers (A, B ,E,F in the , generate the CPU address 0,1 and the CPUBHEn signal for the OTI-087. The A, B buffers are used to interface , MEMORY ADDRESS 129-126 MAPS 0, 1. MA23 [8:1] 115-108 O MEMORY ADDRESS MAPS 2, 3. RASLn 120 O ROW , STROBE. WEAn 118 o WRITE ENABLE A. WEBn 119 o WRITE ENABLE B . WECn 116 o WRITE ENABLE C. WEDn 117 o WRITE ENABLE D. MA01[0]/ 124 o MEMORY AD CASBn DRESS BIT 0. MA23 [0] 122 o MEMORY AD DRESS BIT 0


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PDF 0000api OTI-087 OTI-087 24-bit 640x480 1024x768 1280x1024 I016n, 80386 chipset TL016 CHIPset for 80286 160X64 CACHE MEMORY FOR 80386DX 8X16 PAL16L8-20 oak capacitance
OTI-087

Abstract: OTI-068 80386dx memory interfacing TL016 CHIPset for 80286 80386 chipset 486 system bus weco 80486 chipset 8X16
Text: 80386DX/80486 block diagrams following this section. The OTI-087 requires four buffers (A, B ,E,F in the , generate the CPU address 0,1 and the CPUBHEn signal for the OTI-087. The A, B buffers are used to interface , 129-126 MAPS 0, 1. MA23 [8:1] 115-108 O MEMORY ADDRESS MAPS 2, 3. RASLn 120 O ROW ADDRESS , 118 o WRITE ENABLE A. WEBn 119 o WRITE ENABLE B . WECn 116 o WRITE ENABLE C. WEDn 117 o WRITE ENABLE D. MA01[0]/ 124 o MEMORY AD CASBn DRESS BIT 0. MA23 [0] 122 o MEMORY AD DRESS BIT 0. MD[31


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PDF 0000api OTI-087 OTI-087 24-bit 640x480 1024x768 1280x1024 I016n, OTI-068 80386dx memory interfacing TL016 CHIPset for 80286 80386 chipset 486 system bus weco 80486 chipset 8X16
FE3030

Abstract: No abstract text available
Text: D ■b ? 2 cmDS Q0QD204 S b 4 H O A K T August 1992 0TI-087 Product Overview , following this section. The OTI-087 requires four buffers (A, B ,E,F in the diagram) and 1 pal to interface , and the CPUBHEn signal for the OTI-087. The A, B buffers are used to interface the OTI-087 data bus to , OAK TECHNOLOGY I NC SSE D August 1992 ■b ?2T4DS □□□□205 4T0 H O A K , ¬ Z ì« hw i ì a X 9 ^ ; BUFFER A QÌ*S Ì I § 9 . c BUFFER B DIR DIR


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PDF 00002Q1 OTI-087 24-bit 640x480 1024x768 1280x1024 I016n, FE3030
ymz2

Abstract: YMZ280B-F YSS225 Yamaha YSS225 LE16 YAMAHA DSP
Text: 52 ZI MA23 uuuuuuuuuuuuuuuuuuu ü > l O > I > M > I Í > 0 , data bus data bus data bus data bus data bus data bus data bus data bus 3 Ï1 B No. 42 43 44 45 , output clock output vss MA14 MA15 MA16 MA17 MA18 MA19 MA20 MA21 MA22 MA23 /MOE /MWR /MCE /DSPCS , clear, the MD7 to MDO, MA23 to MAO, /MCE, /MOE, and /MWR pins become high impedance. +: Pin with , the address data is output 1 om the MA23 to MAO pins. Data is input and output at the MD7 to MDO pins


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PDF YMZ280B YMZ280B 16-bit 3K-1215 ymz2 YMZ280B-F YSS225 Yamaha YSS225 LE16 YAMAHA DSP
YSS225

Abstract: ymz2 Yamaha YSS225 LS14I LE16 YAMAHA DSP
Text: MA16 MA17 MA18 MA19 MA20 MA21 MA22 MA23 /MOE /MWR /MCE /DSPCS /DSPSCK VDD DSPCDI, /IRQ /CS AO /WR /RD , + Note) At initial clear, the MD7 to MDO, MA23 to MAO, /MCE, /MOE, and/MWR pins become high impedance. + , , /MWR/ MA23 ~MA0, MD7-MD0 The external memory control signals are output from the /MCE, /MOE, and /MWR pins and the address data is output from the MA23 to MAO pins. Data is input and output at the MD7 to , B $1C~1F $20 ST23 $21 $22 $23 EN23 $24-27 $28~2B $2C~2F $30-33 $34-37 $38~3B $3C~3F CH1 CH2 CH3 CH4


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PDF YMZ280B YMZ280B 16-bit YSS225 ymz2 Yamaha YSS225 LS14I LE16 YAMAHA DSP
4605-7

Abstract: LC8213 md-1562
Text: performed. No. 4605-4/12 LC8213 Pin Assignment I : Input pin 0 : Output pin B : Bidirectional pin P , 7 vdd p 8 nc 9 d7 b 10 d6 b 11 d5 b 12 d4 b 13 Vss p 14 d3 b 15 d2 b 16 d1 b 17 do b 18 , 46 iord 0 47 iowr 0 48 lüe 0 49 üde 0 50 ready i 51 dtc 0 52 Vss p 53 Vdd p 54 ma23 0 55 , /MD15 0 63 Vss p 64 MA/MD14 B 65 MA/MD13 B 66 MA/MD12 B 67 MA/MD11 B 68 MA/MD10 B 69 MA/MD9 B 70 MA/MD8 B 71 MA/MD7 B 72 Vss P 73 Vdd P 74 MA/MD6 B 75 MA/MD5 B 76 MA/MD4 B 77 MA/MD3 B 78 MA


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PDF LC8213 LC8213 MA/MD15-0 4605-7 md-1562
2003 - Magnetic

Abstract: bernstein magnetic
Text: plastic PA 6 cable 22 mm bistable M 12 x 1 x 60 mm MA-23 M 12 x 1 x 80 mm 100 VA/3 A MA , Designation MAK-3012- B -1 MAK-3013-X-1 MAK-4612-A-2 MAK-4613-3 MAA-0612-F-1 MAA-0613-L-1 MAA , change over plug Ø 6.5 18 mm T-62N/S (212) 10 VA (4) 250 V N.O. Standard Designation MAN-0812- B -1 MAN-0813-Y-1 MAN-0813-STK MAM-1812- B -1 MAM-1813-L-1 Part number 631.1208.596 631.0308.595 631.1218.294 Threaded barrels MA-28, M12 x 1 x 60 mm PA MA-23 , M12 x 1 x 80 mm


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PDF MA-04 MA-06 MA-08 MA-11 MA-12 MA-13 MA-16 MA-17 MA-18 MA-23 Magnetic bernstein magnetic
Invensys Sensor Systems MA230

Abstract: MA230SAN Invensys speed sensor MA23 15IPS 202F 204D 300F
Text: 5/8 M16* MA230/MA240 SERIES SEALED FRONT-END VRS SENSORS METERS / SECOND 0 2.5 5.1 7.6 10.1 12.7 15.2 17.8 20.3 22.9 25.4 200 175 150 125 MA23 *SAN 100 V P/P 75 50 MA24*SAN 25 0 100 200 300 400 500 600 700 800 900 1000 INCHES / SECOND FOR SPEED SENSING APPLICATIONS WHERE THE SENSING AREA IS EXPOSED TO FLUIDS , min. TEST CONDITION: B VRS Tech Data COIL RESISTANCE: 120 to 162 OHMS INDUCTANCE: 85 mH max. POLE


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PDF MA230/MA240 CA210 MA240SAN MA243SAN Invensys Sensor Systems MA230 MA230SAN Invensys speed sensor MA23 15IPS 202F 204D 300F
2006 - W 5753

Abstract: LC8213K MA20 MA21 MA22 MA23
Text: V 0.4 µA 25 10 V +10 ­10 MHz 20 mA Block Diagram MA23 to MA16 MA , to +75°C, VSS = 0 V I: Input pin O: Output pin B : Bi-directional pin P: Power supply pin NC: No , 6 A0 I 7 VDD 8 P Address inputs Power supply NC 9 D7 B 10 D6 B 11 D5 B 12 D4 B 13 VSS P 14 D3 B 15 D2 B 16 D1 B 17 D0 Data bus 18 Ground Data bus B NC 19 VDD P 20 IREQ


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PDF LC8213K LC8213K 3174-QFP80E LC8213K] W 5753 MA20 MA21 MA22 MA23
Yamaha YSS225

Abstract: YSS225 YMZ280B-F YAMAHA DSP Yamaha YMZ280B YAMAHA DSP1 ymz280 YMZ263 pan1
Text: + address bus 50 MA21 0+ address bus 51 MA22 0+ address bus 52 MA23 0+ address bus 53 /MOE 0 , Note) At initial clear, the MD7 to MDO, MA23 to MAO, /MCE, /MOE, and /MWR pins become high impedance. + , the MA23 to MAO pins. Data is input and output at the MD7 to MDO pins. At initial clear, these pins , '0' by initial clear. For start address, loop start address, loop end address, and end address, MA23 , address (H) MA23 MA22 MA21 MA20 , MA19 , MA18 , MA17 , MA16 $85 RAM address (M) MA15 | MA14 | MA13


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PDF YMZ280B YMZ280B 16-bit 3K-1005 Yamaha YSS225 YSS225 YMZ280B-F YAMAHA DSP Yamaha YAMAHA DSP1 ymz280 YMZ263 pan1
Not Available

Abstract: No abstract text available
Text: designation n R M C -E ( B )F B - B S L A 6 K ey position C ontact # 1 -j ■■Part number Key position Key position RMC-E( B )15FB-BSLA{ )-MA12 RMC-E( B )15FB-BSLA( )-MA13 RMC-E( B )15FB-BSLA( )- MA23 12 13 23 A12 A13 A23 i— fl Mating connector I 1 0 .8 11 2 Part Number • RMC-E15FB-BS .A3-MB12-BK I B type polarization f1 \ -Cable termination EB , 5 X 5 .5 R M C -E ( B )F B - B S L A 6 K ey position Contact # 1 1± 4 0 5 0 na


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PDF RMC-E15FB-BS LA3-MA12 15FB-BSLA{ -MA12 15FB-BSLA( -MA13 -MA23 C-E15M T0G6402
1997 - LC8213K

Abstract: MA20 MA21 MA22 MA23 10D6B
Text: V 0.4 µA 25 10 V +10 ­10 MHz 20 mA Block Diagram MA23 to MA16 MA , to +75°C, VSS = 0 V I: Input pin O: Output pin B : Bi-directional pin P: Power supply pin NC: No , 6 A0 I 7 VDD 8 P Address inputs Power supply NC 9 D7 B 10 D6 B 11 D5 B 12 D4 B 13 VSS P 14 D3 B 15 D2 B 16 D1 B 17 D0 Data bus 18 Ground Data bus B NC 19 VDD P 20 IREQ


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PDF LC8213K LC8213K 3174-QFP80E LC8213K] MA20 MA21 MA22 MA23 10D6B
2004 - LC8213

Abstract: MA20 MA21 MA22 MA23
Text: image memory bus is performed. Pin Assignment I : Input pin O : Output pin B : Bidirectional pin P , 64 MA/MD14 B 5 A1 I 35 TEST0 I 65 MA/MD13 B 6 A0 I 36 NC 66 MA/MD12 B 7 VDD P 37 BREQ O 67 MA/MD11 B NC 38 BACK I 68 MA/MD10 B 8 9 D7 B 39 IDREQ I 69 MA/MD9 B 10 D6 B 40 IDACK O 70 MA/MD8 B 11 D5 B 41 AEN O 71 MA/MD7 B


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PDF LC8213 LC8213 3174-QIP80E LC8213] MA20 MA21 MA22 MA23
T23BH

Abstract: western digital 286 M10-286 FE5400 paradise 202L1 FE5020
Text: International B usiness M achines Corpora tion. Intel is a registered tradem ark of Intel Corporation. P aradise , Company. WESTERN DIGITAL CORP 21E D TVlfiEEñ D0DST3T b T -S 2 -û < } O o Release , FE5020 EIE D T71Ô22Ô 0005T42 b FARADAY T - 52.-0«} 2 Advance Information WESTERN , / 18 -c \ - y O y \ > 116 B FARADAY FE5020 50 -c > 84 132 PIN JEDEC FLAT , SA2 SA1 SAO MA23 MA22 MA21 Vss MA19 MA18 MA17 MA16 Vss MA15 MA14 MA13 Vss Advance Information 3


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PDF 00GSc FE5020 FE5400 FE5020 T23BH western digital 286 M10-286 paradise 202L1
jtag s29gl128p

Abstract: MT48LC32M16A2P-75 SDA14 MT48LC32M16A2P BYP52 SDD26 S29GL128P MT48LC32M16A2P-75 by 0/a7 moe MT48LC32M16A2P-75 cas
Text: SD3.3V GND B SDMDATA0 SDMDATA1 SDMDATA2 SDMDATA3 SDCMD SDMCLK SDMCD# SDMWP SDMGPO , GND B JTAG.Sch 3.3V 1.8V UVSS AVDD AVSS CM2DATA[7.0] TXD1/GPIOA0 RXD1/GPIOA1 , 3.3V R28 1K R37 R36 10K 10K FROM BUSY LED10 RED C GND MA23 MA22 MA21 MA20 MA19 , # MBEL# MBEH# 3.3V INIT RA3 10K SW11 16 15 14 13 12 11 10 9 B 1 2 3 4 5 6 7 8 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 B CHS-08B JTAG&RESET RESET# 3.3V


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PDF PCF8574 CHS-08B jtag s29gl128p MT48LC32M16A2P-75 SDA14 MT48LC32M16A2P BYP52 SDD26 S29GL128P MT48LC32M16A2P-75 by 0/a7 moe MT48LC32M16A2P-75 cas
2001 - LC8213

Abstract: MA20 MA21 MA22 MA23 11d5
Text: pin O : Output pin B : Bidirectional pin P : Power pin NC : Not connected No. Pin name , 63 VSS P 4 A2 I 34 TEST1 I 64 MA/MD14 B 5 A1 I 35 TEST0 I 65 MA/MD13 B 6 A0 I 36 NC 66 MA/MD12 B 7 VDD P 37 BREQ O 67 MA/MD11 B NC 38 BACK I 68 MA/MD10 B 8 9 D7 B 39 IDREQ I 69 MA/MD9 B 10 D6 B 40 IDACK O 70 MA/MD8 B


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PDF LC8213 LC8213 3174-QIP80E LC8213] MA20 MA21 MA22 MA23 11d5
1995 - DB25 Right Angle PCB Mount

Abstract: DB15 MALE TO DB9 FEMALE DB15 connector female elma E33 ED56 CX117 DB15 male connector orion crt monitor circuit diagram DB15 pcb connector female DB14 connector male
Text: or systems which (a) are intended for surgical implant into the body or ( b ) support or sustain life , DRAM DATA BUFFERS A B2 4 x 16501 RAS/CAS Address Muxes PD[31:0] B PA[31:0] PERIPHERAL ADDRESS BUFFERS A 64 B A 2 x 16501 A B 16260 x 6 OD[63:0] B2 B1 MD[63:0] A B2 B1 B SYSAD DATA BUFFERS PROM ADDRESS BUFFER 16841 16260 x 4 A BRCLK BRCLK B 32 64/32 BUS EXCHANGE 82C54 Timer Command/Status Registers CL-CD1284


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PDF IDT79S464 R4600 R4x00 DB25 Right Angle PCB Mount DB15 MALE TO DB9 FEMALE DB15 connector female elma E33 ED56 CX117 DB15 male connector orion crt monitor circuit diagram DB15 pcb connector female DB14 connector male
2008 - Magnetic

Abstract: bernstein magnetic MAK12 630.2111.047
Text: x 1 x 60 mm MA-23 M 12 x 1 x 80 mm 100 VA/3 A MA-33 M 12 x 1 x 80 mm MA-17 60 VA/1 A 250 , 7 mm T-62N/S (212) 100 VA (11) 250 V N.O. Standard Designation MAK-3012- B -1 MAK , change over plug Ø 6.5 18 mm T-62N/S (212) 10 VA (4) 250 V N.O. Standard Designation MAN-0812- B -1 MAN-0813-Y-1 MAN-0813-STK MAM-1812- B -1 MAM-1813-L-1 Part number 631.1208.596 631.0308.595 631.1218.294 Threaded barrels MA-28, M12 x 1 x 60 mm PA MA-23 , M12 x 1 x 80 mm


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PDF IP67/NEMA BWN-M06NI/40 BWN-M06NI/27 BWN-M36NI MA-06, MA-16, MA-26, MA-15 Magnetic bernstein magnetic MAK12 630.2111.047
Not Available

Abstract: No abstract text available
Text: €” — 20 ns Figures 8-9 8 -8 , BACKI setup time ts B A C K 40 — â , D 0 to M A/M D 1 5 M A 1 6 to MA23 MA/MD 0 to M A/M D 1 5 ¡OR IOW LEND Figure 8-1


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PDF
2005 - YGV6

Abstract: sy 166 MA10 MA11 YGV629 YGV629-VZ MA23 B
Text: 6 bits DAC for each R,G, and B 144 pin plastic LQFP, pin lead plating is Pb-free. (YGV629-VZ , Controller Processor Line Buffer F R, G, B IREF DR5-0 DG5-0 DAC DB5-0 DAC HCSYNC_N , Memory max 256Mbit MOE_N MWE_N VC1 XIN CSYNC_N XOUT R,G, B -3- 3 LCD Monitor , MWE_N 1 OT RAHZ_N 1 I Monitor Interface R,G, B 3 O IREF 1 DR5-0 6 O DG5-0 6 O DB5-0 6 , B Output Vertical Synchronizing Signal Output Horizontal Synchronizing / Composite Synchronizing


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PDF YGV629 4GV629A20 YGV6 sy 166 MA10 MA11 YGV629 YGV629-VZ MA23 B
2003 - Magnetic

Abstract: No abstract text available
Text: MA-18 Page 200 MA-23 Page 200 MA-26 Page 199 MA-28 Page 200 MA-30 Page 199


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PDF MA-04 MA-06 MA-08 MA-11 MA-12 MA-13 MA-16 MA-17 MA-18 MA-23 Magnetic
Supplyframe Tracking Pixel