The Datasheet Archive

M68Z512 datasheet (10)

Part Manufacturer Description Type PDF
M68Z512 STMicroelectronics 4 Mbit (512Kb x8) Low Power SRAM with Output Enable Original PDF
M68Z512 STMicroelectronics 4 MBIT (512KB X8) LOW POWER SRAM WITH OUTPUT ENABLE Original PDF
M68Z512-70NC1 STMicroelectronics 4 MBit (512 kBit x 8) Low Power SRAM with Output Enable Original PDF
M68Z512-70NC1 STMicroelectronics 4 Mbit (512Kb x 8) Low Power SRAM with Output Enable Scan PDF
M68Z512-70NC1T STMicroelectronics 4 Mbit 512Kb x8 Low Power SRAM with Output Enable Original PDF
M68Z512-70NC1T STMicroelectronics 4 Mbit (512Kb x 8) Low Power SRAM with Output Enable Scan PDF
M68Z512-70NC1TR STMicroelectronics 4 MBit (512 kBit x 8) Low Power SRAM with Output Enable Original PDF
M68Z512NC STMicroelectronics 4 Mbit 512Kb x8 Low Power SRAM with Output Enable Original PDF
M68Z512W STMicroelectronics 4 MBIT (512KB X8) LOW VOLTAGE LOW POWER SRAM WITH OUTPUT ENABLE Original PDF
M68Z512W-70NC1 STMicroelectronics 4 MBit (512 kBit x 8) Low Voltage, low Power SRAM with Output Enable Original PDF

M68Z512 Datasheets Context Search

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2000 - M68Z512

Abstract: No abstract text available
Text: M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT , INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS DESCRIPTION The M68Z512 is a 4 Mbit , automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z512 is , 19 8 A0-A18 W DQ0-DQ7 M68Z512 E Supply Voltage VSS VCC Write Enable , M68Z512 Table 2. Absolute Maximum Ratings (1) Symbol Parameter TA TSTG VIO (2) Input or


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PDF M68Z512 512Kb 100nA M68Z512
2000 - Not Available

Abstract: No abstract text available
Text: M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT , The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device , deselected. The M68Z512 is available in a 32 lead TSOP II (10 x 20mm) package. Table 1. Signal Names A0-A18 DQ0-DQ7 E G W VCC VSS Address Inputs VCC 19 A0-A18 8 DQ0-DQ7 W E G M68Z512 Data Input , M68Z512 Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG VIO (2) VCC IO (3) PD Parameter Ambient


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PDF M68Z512 512Kb 100nA M68Z512
M68Z512

Abstract: No abstract text available
Text: M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT , INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS DESCRIPTION The M68Z512 is a 4 Mbit , automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z512 is , 19 8 A0-A18 W DQ0-DQ7 M68Z512 E Supply Voltage VSS VCC Write Enable , M68Z512 Table 2. Absolute Maximum Ratings (1) Symbol Parameter TA TSTG VIO (2) Input or


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PDF M68Z512 512Kb 100nA M68Z512
2000 - Not Available

Abstract: No abstract text available
Text: M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT , INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS DESCRIPTION The M68Z512 is a 4 Mbit , automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z512 is , 19 8 A0-A18 W DQ0-DQ7 M68Z512 E Supply Voltage VSS VCC Write Enable , M68Z512 Table 2. Absolute Maximum Ratings (1) Symbol Parameter TA TSTG VIO (2) Input or


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PDF M68Z512 512Kb 100nA M68Z512
M68Z512

Abstract: No abstract text available
Text: READ MODE The M68Z512_ [s in the Read mode whenever Write Enable (W) is High_with Output Enable (G) Low , 51 M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable PRELIMINARY DATA ■ULTRA , DESELECTED ■INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER® CONTROLLERS DESCRIPTION The M68Z512 , . The M68Z512 is available in a 32 lead TSOP II (10 x 20mm) package. Table 1. Signal Names A0-A18 , M68Z512 DQ0-DQ7 vss May 1999 This is preliminary information on a new product now in development or


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PDF M68Z512 512Kb 100nA M68Z512
2002 - M68Z512

Abstract: No abstract text available
Text: M68Z512 4 Mbit (512 Kbit x 8) Low Power SRAM with Output Enable FEATURES SUMMARY s ULTRA LOW , ® CONTROLLERS May 2002 32 1 TSOP II 32 (NC) 10 x 20mm 1/15 M68Z512 TABLE OF CONTENTS , . . . . . . . 14 2/15 M68Z512 DESCRIPTION The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS , feature, reducing the power consumption by over 99% when deselected. The M68Z512 is available in a 32 , Enable W A0-A18 E Write Enable M68Z512 VCC Supply Voltage VSS Ground E G


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PDF M68Z512 100nA M68Z512
1999 - Not Available

Abstract: No abstract text available
Text: M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable PRELIMINARY DATA s ULTRA LOW DATA , DESCRIPTION The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The , deselected. The M68Z512 is available in a 32 lead TSOP II (10 x 20mm) package. Table 1. Signal Names A0-A18 DQ0-DQ7 E G W VCC VSS Address Inputs VCC 19 A0-A18 8 DQ0-DQ7 W E G M68Z512 Data Input , change without notice. 1/12 M68Z512 Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG VIO (2


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PDF M68Z512 512Kb 100nA M68Z512
2000 - Not Available

Abstract: No abstract text available
Text: M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT , The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device , deselected. The M68Z512 is available in a 32 lead TSOP II (10 x 20mm) package. Table 1. Signal Names A0-A18 DQ0-DQ7 E G W VCC VSS Address Inputs VCC 19 A0-A18 8 DQ0-DQ7 W E G M68Z512 Data Input , M68Z512 Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG VIO (2) VCC IO (3) PD Parameter Ambient


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PDF M68Z512 512Kb 100nA M68Z512
2001 - M48Z512A

Abstract: M48Z512AV M48Z512AY SOH28
Text: ) and a 32 pin TSOP Type II (10 x 20mm) LPSRAM ( M68Z512 /W) packages. Both 5V and 3V versions are , ) VCC E2 M40Z300/W M68Z512 /W DQ0-DQ7 E E1CON E E2CON E3CON E4CON A0-A18 A , individual data sheets for M40Z300/W and M68Z512 /W at www.st.com. Connect THS pin to VOUT if 4.2V VPFD , LPSRAM SUPERVISOR THS Pin (1) M48Z512A M68Z512 M40Z300 VSS M48Z512AY M68Z512 M40Z300 VOUT M48Z512AV M68Z512W M40Z300W VSS Note: 1. Connection of Threshold Select Pin


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PDF M48Z512A M48Z512AY, M48Z512AV 512Kb PMDIP32 M48Z512A: M48Z512AY: M48Z512AV: 28-PIN M48Z512A M48Z512AV M48Z512AY SOH28
2000 - Schottky Diode 75V 7A

Abstract: M48Z512A M48Z512AV M48Z512AY SOH28
Text: ) and a 32 pin TSOP Type II (10 x 20mm) LPSRAM ( M68Z512 /W) packages. Both 5V and 3V versions are , ) VCC E2 M40Z300/W M68Z512 /W DQ0-DQ7 E E1CON E E2CON E3CON E4CON A0-A18 A , individual data sheets for M40Z300/W and M68Z512 /W at www.st.com. Connect THS pin to VOUT if 4.2V VPFD , Mount Chip Set solution M40Z300/W (SOH28) + M68Z512 /W (TSOP II 32) Temperature Range 1 = 0 to 70 °C 9


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PDF M48Z512A M48Z512AY, M48Z512AV 512Kb PMDIP32 M48Z512A: M48Z512AY: M48Z512AV: 28-PIN Schottky Diode 75V 7A M48Z512A M48Z512AV M48Z512AY SOH28
2000 - M48Z512A

Abstract: M48Z512AY SOH28
Text: 28 pin 330mil SOIC NVRAM Supervisor (M40Z300) and a 32 pin TSOP Type II (10 x 20mm) LPSRAM ( M68Z512 , BATTERY(3) VOUT VCC E2 M40Z300 M68Z512 DQ0-DQ7 E E1CON E E2CON E3CON E4CON , data sheets for M40Z300 and M68Z512 at www.st.com. 2. Connect THS pin to VOUT if 4.2V VPFD 4.5V , 85ns Package PM = PMDIP32 CS (1) = Surface Mount Chip Set solution M40Z300 (SOH28) + M68Z512 (TSOP


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PDF M48Z512A M48Z512AY 512Kb PMDIP32 M48Z512A: M48Z512AY: 28-PIN 32-LEAD M48Z512A M48Z512AY SOH28
2002 - a7 surface mount diode

Abstract: SOH28 M48Z512A M48Z512AV M48Z512AY
Text: ) M48Z512A M68Z512 M40Z300 VSS M48Z512AY M68Z512 M40Z300 V OUT M48Z512AV M68Z512W , ( M68Z512 /W) packages. Both 5V and 3V versions are available (see Table 2, page 5). The unique design , M68Z512 /W DQ0-DQ7 E E1CON E E2CON E3CON E4CON A0-A18 A RST B W BL VSS VSS AI03631 Note: For pin connections, see individual data sheets for M48Z300/300W and M68Z512 /512W at


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PDF M48Z512A M48Z512AY, M48Z512AV* 32-pin M48Z512A: M48Z512AY: M48Z512AV: a7 surface mount diode SOH28 M48Z512A M48Z512AV M48Z512AY
2003 - M40Z300

Abstract: M48Z512A M48Z512AV M48Z512AY SOH28
Text: . Equivalent Surface-Mount (SMT) Solution NVRAM LPSRAM SUPERVISOR THS Pin(1) M48Z512A M68Z512 M40Z300 VSS M48Z512AY M68Z512 M40Z300 VOUT M48Z512AV M68Z512W M40Z300W VSS , ) and a 32-pin TSOP Type II (10 x 20mm) LPSRAM ( M68Z512 /W) packages. Both 5V and 3V versions are , THS(2,3) VOUT VCC E2 SNAPHAT BATTERY(4) M68Z512 /W M40Z300/W DQ0-DQ7 E E1CON E , connections, see individual data sheets for M48Z300/300W and M68Z512 /512W at www.st.com. 1. Connect THS pin


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PDF M48Z512A M48Z512AY, M48Z512AV* 32-pin M48Z512A: M48Z512AY: M48Z512AV: M40Z300 M48Z512A M48Z512AV M48Z512AY SOH28
2002 - M48Z512A

Abstract: M48Z512AV M48Z512AY SOH28 CP2022
Text: Solution NVRAM LPSRAM SUPERVISOR THS Pin(1) M48Z512A M68Z512 M40Z300 VSS M48Z512AY M68Z512 M40Z300 VOUT M48Z512AV M68Z512W M40Z300W VSS Note: 1. Connection of Threshold , NVRAM SUPERVISOR (M40Z300/W) and a 32-pin TSOP Type II (10 x 20mm) LPSRAM ( M68Z512 /W) packages. Both , SNAPHAT BATTERY(4) VCC E2 M40Z300/W M68Z512 /W DQ0-DQ7 E E1CON E E2CON E3CON , individual data sheets for M48Z300/300W and M68Z512 /512W at www.st.com. 1. Connect THS pin to VOUT if 4.2V


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PDF M48Z512A M48Z512AY, M48Z512AV 32-pin M48Z512A: M48Z512AY: M48Z512AV: M48Z512A M48Z512AV M48Z512AY SOH28 CP2022
2000 - Not Available

Abstract: No abstract text available
Text: AI03633 Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z512 /W at www.st.com. 2. For 5V, M48T129Y (M48T201Y + M68Z512 ). For 3.3V, M48T129V (M48T201V + M68Z512W ). 3. SNAPHAT , ) LPSRAM ( M68Z512 /W) packages. The 44 pin 330mil SOIC provides sockets with gold plated contacts at both , 5V LITHIUM CELL M48T201Y/V (2) VCC 0.1µF M68Z512 /W (2) E W ECON G E W , Surface Mount Chip Set solution M48T201Y/V (SOH44) + M68Z512 /W (TSOP32) Temperature Range 1 = 0 to 70 °C


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PDF M48T513Y M48T513V 512Kb M48T513Y: M48T513V: PMLDIP36
2000 - Not Available

Abstract: No abstract text available
Text: SOIC TIMEKEEPER Supervisor (M48T201V/Y) and a 32 pin TSOP Type II (10 x 20mm) LPSRAM ( M68Z512 /W , M68Z512 /W (2) VSS DQ0-DQ7 AI03633 Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z512 /W at www.st.com. 2. For 5V, M48T129Y (M48T201Y + M68Z512 ). For 3.3V, M48T129V (M48T201V + M68Z512W ). 3. SNAPHAT Top ordered separately. READ MODE The M48T513Y/V is in the Read Mode , M48T201Y/V (SOH44) + M68Z512 /W (TSOP32) Temperature Range 1 = 0 to 70 °C M48T513Y -70 PM 1 Note: 1. The


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PDF M48T513Y M48T513V 512Kb M48T513Y: M48T513V: PMDIP32
M48T513Y

Abstract: SOH44 44-PIN M48T513V
Text: AI03633 Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z512 /W at www.st.com. 2. For 5V, M48T129Y (M48T201Y + M68Z512 ). For 3.3V, M48T129V (M48T201V + M68Z512W ). 3. SNAPHAT , ) LPSRAM ( M68Z512 /W) packages. The 44 pin 330mil SOIC provides sockets with gold plated contacts at both , 5V LITHIUM CELL M48T201Y/V (2) VCC 0.1µF M68Z512 /W (2) E W ECON G E W , Surface Mount Chip Set solution M48T201Y/V (SOH44) + M68Z512 /W (TSOP32) Temperature Range 1 = 0 to 70 °C


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PDF M48T513Y M48T513V 512Kb PMDIP32 M48T513Y: M48T513V: M48T513Y SOH44 44-PIN M48T513V
2002 - Not Available

Abstract: No abstract text available
Text: NVRAM M48Z512A M48Z512AY M48Z512AV LPSRAM M68Z512 M68Z512 M68Z512W SUPERVISOR M40Z300 M40Z300 M40Z300W , Type II (10 x 20mm) LPSRAM ( M68Z512 /W) packages. Both 5V and 3V versions are available (see Table 2 , VSS W E M68Z512 /W DQ0-DQ7 A0-A18 VSS AI03631 Note: For pin connections, see individual data sheets for M48Z300/300W and M68Z512 /512W at www.st.com. 1. Connect THS pin to VOUT if 4.2V VPFD


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PDF M48Z512A M48Z512AY, M48Z512AV 32-pin M48Z512A: M48Z512AY: M48Z512AV: 28-PIN
M41Txx

Abstract: SO16 M48T35A M48Z35A M48Z58 M48Z512A M48Z35 M48Z2M1 M48Z129 "TOPS"
Text: -55N1 128Kbx8 5.0V 2µA Now M68Z128W-70N1 128Kbx8 3.0V 2µA Now M68Z512-70NC1 512Kbx8 5.0V 10µA Now M68Z512W-70NC1 512Kbx8 3.0V 10µA 4q00 LPSRAM MPG -


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PDF M48Zxxx M48Txxx M48STxxx M40Zxxx M40SZxxx M68Zxxx M41Txx M41STXX PTNV0013 M41Txx SO16 M48T35A M48Z35A M48Z58 M48Z512A M48Z35 M48Z2M1 M48Z129 "TOPS"
2002 - nvram

Abstract: M4T32-BR12SH1 M68Z128 M4T28-BR12SH1 M41ST85YMH6 M41ST85WMH6 M41ST85 M68Z512 SOH28 400khz xtal
Text: onit M E CON XTAL Fail Power- Protect Write CE LPSRAM M68Z128 (128Kx8) or M68Z512


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PDF M41ST85 M41ST85 48mAh 120mAh FLM41ST85/0602 nvram M4T32-BR12SH1 M68Z128 M4T28-BR12SH1 M41ST85YMH6 M41ST85WMH6 M68Z512 SOH28 400khz xtal
2001 - 44-PIN

Abstract: M48T513V M48T513Y SOH44
Text: DQ0-DQ7 AI03633 Note: For pin connections, see individual data sheets for M48T201Y/V and M68Z512 /W at www.st.com. 1. For 5V, M48T513Y (M48T201Y + M68Z512 ). For 3.3V, M48T513V (M48T201V + M68Z512W ). , TSOP Type II (10 x 20mm) LPSRAM ( M68Z512 /W) packages. The 44 pin 330mil SOIC provides sockets with , 0.1µF 5V or 3.3V LITHIUM CELL M48T201Y/V (2) VCC 0.1µF M68Z512 /W (2) E W ECON , M68Z512 /W (TSOP32) Temperature Range 1 = 0 to 70 °C Note: 1. The SOIC package (SOH44) requires the


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PDF M48T513Y M48T513V M48T513Y: M48T513V: 44-PIN M48T513V M48T513Y SOH44
2001 - Not Available

Abstract: No abstract text available
Text: ( M68Z512 /W) packages. The 44-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for , DQ0-DQ7 ECON E W G (1) M68Z512 /W VSS DQ0-DQ7 AI03633 Note: For pin connections, see individual data sheets for M48T201Y/V and M68Z512 /W at www.st.com. 1. For 5V, M48T513Y (M48T201Y + M68Z512 ). For 3.3V, M48T513V (M48T201V + M68Z512W ). 2. SNAPHAT ® Top ordered separately. 3. RSTIN input is the same , PLDIP36 CS (1) = Surface Mount Chip Set solution M48T201Y/V (SOH44) + M68Z512 /W (TSOP II 32


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PDF M48T513Y M48T513V 36-pin M48T513Y: M48T513V:
2001 - Not Available

Abstract: No abstract text available
Text: W G WDI RSTIN1 (3) RSTIN2 VSS G CON RST IRQ/FT SQW DQ0-DQ7 ECON E W G (1) M68Z512 /W VSS DQ0-DQ7 AI03633 Note: For pin connections, see individual data sheets for M48T201Y/V and M68Z512 /W at www.st.com. 1. For 5V, M48T513Y (M48T201Y + M68Z512 ). For 3.3V, M48T513V (M48T201V + M68Z512W ). 2 , (M48T201V/Y) and a 32-pin TSOP Type II (10 x 20mm) LPSRAM ( M68Z512 /W) packages. The 44-pin, 330mil SOIC , PLDIP36 CS (1) = Surface Mount Chip Set solution M48T201Y/V (SOH44) + M68Z512 /W (TSOP II 32


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PDF M48T513Y M48T513V 36-pin M48T513Y: M48T513V:
2001 - Not Available

Abstract: No abstract text available
Text: ) LPSRAM ( M68Z512 /W) packages. The 44-pin, 330mil SOIC provides sockets with gold plated contacts at , VOUT VCC 0.1µF 5V or 3.3V M48T201Y/V(1) LITHIUM CELL VCC 0.1µF (1) M68Z512 /W , and M68Z512 /W at www.st.com. 1. For 5V, M48T513Y (M48T201Y + M68Z512 ). For 3.3V, M48T513V (M48T201V + M68Z512W ). 2. SNAPHAT ® Top ordered separately. 3. RSTIN input is the same input as RSTIN2 of M48T201Y/V , (1) = Surface Mount Chip Set solution M48T201Y/V (SOH44) + M68Z512 /W (TSOP II 32) Temperature


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PDF M48T513Y M48T513V 36-pin M48T513Y: M48T513V:
2002 - 44-PIN

Abstract: M48T513V M48T513Y SOH44
Text: 20mm) LPSRAM ( M68Z512 /W) packages. The 44-pin, 330mil SOIC provides sockets with gold plated , VOUT VCC 0.1µF 5V or 3.3V M48T201Y/V(1) LITHIUM CELL VCC 0.1µF (1) M68Z512 /W E , and M68Z512 /W at www.st.com. 1. For 5V, M48T513Y (M48T201Y + M68Z512 ). For 3.3V, M48T513V (M48T201V + M68Z512W ). 2. SNAPHAT ® Top ordered separately. 3. RSTIN input is the same input as RSTIN2 of M48T201Y/V


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PDF M48T513Y M48T513V 36-pin M48T513Y: M48T513V: 44-PIN M48T513V M48T513Y SOH44
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