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Part ECAD Model Manufacturer Description Datasheet Download Buy Part
DSLVDS1047PWT DSLVDS1047PWT ECAD Model Texas Instruments 3.3-V LVDS Quad Channel High-Speed Differential Line Driver 16-TSSOP -40 to 85
EVK-DS40MB200 EVK-DS40MB200 ECAD Model Texas Instruments
DSLVDS1002DBVT DSLVDS1002DBVT ECAD Model Texas Instruments 400-Mbps LVDS single high speed differential receiver 5-SOT-23 -40 to 85
TVB1440RGZR TVB1440RGZR ECAD Model Texas Instruments 4-channel TV redriver with equalization 48-VQFN 0 to 85
5962-9762101QEA 5962-9762101QEA ECAD Model Texas Instruments Quad LVDS Transmitter 16-CDIP -55 to 125
5962-9762201VFA 5962-9762201VFA ECAD Model Texas Instruments Quad LVDS Receiver 16-CFP -55 to 125

M Meiko Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
M Meiko

Abstract: QTLP610CRAG
Text: multicolor illuminations. A B S O L U T E M A X IM U M R ATINGS Parameter Continuous Forward Current - lF , A L P ER F O R M A N C E CUR VES VF - FORWARD VOLTAGE (V) Fig. 1 Forw ard C u rre n t vs. F orw ard V oltage lF - DC FORWARD CURRENT (mA) Fig. 2 Relative L u m in o u s Intensity vs. DC Forw ard , P G reen Q TLP610C-RA G T Y P IC A L P E R F O R M A N C E CUR VES WAVELENGTH (nm) Fig. 3 R , AMBIENT TEMPERATURE ÇC) Fig. 5 C u rre n t Derating C urve M R IIG H T SURFACE MOUNT LED LAMP


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PDF TLP610C 178mm) M Meiko QTLP610CRAG
2008 - LEON3FT

Abstract: M Meiko multiplier accumulator MAC code VHDL algorithm leon3 leon processor interrupt vhdl fpu coprocessor IEEE-1754 vhdl code for simple radix-2 SPARC v8 architecture BLOCK DIAGRAM ASR-26
Text: the Meiko FPU core (available from Sun Microsystems). The floating-point processors and co-processor , LD FPU M V8 NWP 0 NWIN Figure 6. LEON3 configuration register (%asr17) Field Definitions , ]: FPU option. "00" = no FPU; "01" = GRFPU; "10" = Meiko FPU, "11" = GRFPU-Lite [9]: If set, the , M Figure 10. Cache configuration register [31]: Cache locking (CL). Set if cache locking is , these units. Two different FPU's can be interfaced: Aeroflex Gaisler's GRFPU, and the Meiko FPU from


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PDF 32-bit LEON3FT M Meiko multiplier accumulator MAC code VHDL algorithm leon3 leon processor interrupt vhdl fpu coprocessor IEEE-1754 vhdl code for simple radix-2 SPARC v8 architecture BLOCK DIAGRAM ASR-26
2006 - AMBA AHB memory controller

Abstract: ASR17 IEEE-1754 leon3 LEON3FT asr19 Can 2.0 controller sparc v8 Memtech vhdl code for floating point multiplier
Text: the Meiko FPU core (available from Sun Microsystems). The floating-point processors and co-processor , 8 7 5 4 NWIN 0 INDEX SV LD FPU M V8 NWP Figure 6. LEON3 configuration register , GRFPU; "10" = Meiko FPU, "11" = GRFPU-Lite [9]: If set, the optional multiply-accumulate (MAC , 28 27 26 25 24 23 REPL SN SETS SSIZE 20 19 18 LR 16 15 12 11 LRSIZE LRSTART 4 3 M 0 , : Gaisler Research's GRFPU, and the Meiko FPU from Sun. Selection of which FPU to use is done through the


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PDF 32-bit IEEE-STD-754 AMBA AHB memory controller ASR17 IEEE-1754 leon3 LEON3FT asr19 Can 2.0 controller sparc v8 Memtech vhdl code for floating point multiplier
2007 - M Meiko

Abstract: AT7913 AT7913E2U-E vhdl code 64 bit FPU AT7913E2H-SV EL B17
Text: caches ­ Meiko FPU ­ Interrupt Controller ­ Uart serial links ­ 32-bit Timers ­ Memory interface ­ , purpose LEON2-FT SPARC V8 core with a MEIKO FP unit (IEEE-754). This architecture provides the mixed , IM IN A R Y IN Figure 1. AT7913E SpaceWre RTC Block Diagram FO R M A TI , J6 K8 N5 TapTdo M A TapTms H15 TapTrstN VSB31 H19 J12 VSB32 TimeClk TimeTrig_1 TimeTrig_2 VDA0 , VDB8 TI O M2 V5 W8 W9 U10 V11 M11 W13 T14 N13 P18 M12 M13 K14 VDB9 M A VDB11 E13 VDB12 N15


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PDF 32-bit 8bit/16bit 200Mbit/s 7833C M Meiko AT7913 AT7913E2U-E vhdl code 64 bit FPU AT7913E2H-SV EL B17
FYPF2004DN

Abstract: FFPF30U60DN fairchild korea ffpf30u20s FFPF04F150S 81663-9 FYPF2006DN FFPF14X150S *F30U60DN
Text: 60 5 10 15 20 60 20 25 V r m a x ï (V) 1.2 1.2 1.2 1.4 1.4 2.3 2.2 2.2 2.3 1.2 1.2 1.2 1.4 1.4 2.3 , 200 400 TO-220 600 200 400 600 Dual Common Cathode è M A W A TO-3PF 1200 , for dam per diode: I f =20A and d i/d t = 200A/ys for m odulation diode Schottky Barrier Diodes , IL D SEMICONDUCTOR'" 15.87 (1.00x45°) + 0 20 ? m m D2 -PAK (FS PKG Code AB) EH nJ , : 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild Semiconductor Japan Ltd. Osaka Office Shin-Osaka Meiko Building 8F


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2000 - cd4xxx

Abstract: qsc 1110 SN74ACTXXXPW 74HCxx SN74LVCxxx semiconductor cross reference M74HCXXXB1R M74HCXXXM1R SN74ACTXXXN M-SD-DT
Text: P SOIC M , WM, SC SO, S1 D, DW S, W D M , MI D, DW FN, FW SOIC EIAJ SJ M NS F , Ltd. Osaka Office Shin-Osaka Meiko Building 8F 4-3-12, Miyahara, Yodogawa-ku Osaka, 532-0003 Japan


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PDF 300-mil N-1392 cd4xxx qsc 1110 SN74ACTXXXPW 74HCxx SN74LVCxxx semiconductor cross reference M74HCXXXB1R M74HCXXXM1R SN74ACTXXXN M-SD-DT
2002 - LQFP-48

Abstract: LQFP48 FMS9875KGC100 lqfp 52 M Meiko MQUAD 17148 45010 mQFP-80 to plcc 48 TMC1203KLC50
Text: K MQuad M MQFP N Plastic DIP P Americas Customer Response Center Fairchild , Temperature Range M -55 to +125°C I -25 to +85°C or -40 to +85°C C 0 to +70°C Electrical , Fairchild Semiconductor Japan Ltd. Osaka Office 8F Shin-osaka Meiko Building 4-3-12, Miyahara


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PDF FMS9874AKGC100 FMS9874AKGC140 MQFP-100 FMS9875KGC100 FMS9875KGC140 FMS9884AKAC100 LQFP-48 LQFP48 FMS9875KGC100 lqfp 52 M Meiko MQUAD 17148 45010 mQFP-80 to plcc 48 TMC1203KLC50
2003 - smps 1kW

Abstract: 1kw single phase IGBT inverter CIRCUIT 1.5KW vfo 2kw pfc 1kw single phase IGBT inverter IC Module half bridge converter 2kw FSAM15SM60A vfo 0.75kw Inverter Diagram FSAM15SH60A PFC 5kw
Text: + PFC Unit M O T O R DC/DC Converter SMPS Op-Amp CPU (a) Circuit Layout (b , : 81-3-5275-8380 Fax: 81-3-5275-8390 Fairchild Semiconductor Japan Ltd. Osaka Office Shin-Osaka Meiko Building


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PDF 60x31mm) Power247TM, smps 1kW 1kw single phase IGBT inverter CIRCUIT 1.5KW vfo 2kw pfc 1kw single phase IGBT inverter IC Module half bridge converter 2kw FSAM15SM60A vfo 0.75kw Inverter Diagram FSAM15SH60A PFC 5kw
2001 - qsc 1110

Abstract: demultiplexer FST3253 NC7SB3157 SSOP-48 IDTQS3245 NC7WB3125 demultiplexer 21 PI5C16211 FSTD3306
Text: Shin-Osaka Meiko Building 8F 4-3-12, Miyahara, Yodogawa-ku Osaka, 532-0003 Japan Tel: 81-6-6398-3670 Fax , United Kingdom Tel: 44-1793-856856 Fax: 44-1793-856857 G = Fine-Pitch Ball Grid Array (FBGA) M =


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PDF 48-Bit qsc 1110 demultiplexer FST3253 NC7SB3157 SSOP-48 IDTQS3245 NC7WB3125 demultiplexer 21 PI5C16211 FSTD3306
2004 - 120v ac to dc mobile charger circuit

Abstract: FGA25N120 TRANSISTOR FDD6685 fdd6685 1000V P-channel MOSFET p channel mosfet 100v n-Channel mosfet 400v china DVD player power circuit diagram Mosfet analog switch low voltage low resistance BI-DIRECTIONAL TRIODE THYRISTOR SILICON PLANAR
Text: /fdc6000nz_nph.html 125 KA5L0365RN TMC22091 100 TMC22191 75 A*RDS(on) [ m cm2] TMC2330A , Office Shin-Osaka Meiko Building 8F 4-3-12, Miyahara, Yodogawa-ku Osaka, 532-0003 Japan Tel


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PDF Power247TM, 120v ac to dc mobile charger circuit FGA25N120 TRANSISTOR FDD6685 fdd6685 1000V P-channel MOSFET p channel mosfet 100v n-Channel mosfet 400v china DVD player power circuit diagram Mosfet analog switch low voltage low resistance BI-DIRECTIONAL TRIODE THYRISTOR SILICON PLANAR
2002 - LF351 op-amp application

Abstract: LM324 Low Power Quad Op-amp L272 Circuit datasheets of op-amp LM 250 KA1458 LF351 op-amp LM319 AD9101 E220 L272 datasheet
Text: Package Designator P5: 5-lead SC70 MU8: 8-lead MSOP Industry Standard Series LM 358 A M , Temperature Range 0° to +70°C UC N M SO-16 QSC20: 20-lead QSOP A, B, C = Increasing Grade A or B = Impoved Electrical Specification M MTC14: 14-lead TSSOP Electrical Grade Part , Semiconductor Japan Ltd. Osaka Office Shin-Osaka Meiko Building 8F 4-3-12, Miyahara, Yodogawa-ku Osaka


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PDF KM4100IC8TR3 KM4100IT5TR3 KM4101IC8TR3 KM4101IT6TR3 KM4110IT5TR3 KM4111IT5TR3 KM4112IT5TR3 KM4120IT6TR3 KM4121IT6TR3 KM4170IS5TR3 LF351 op-amp application LM324 Low Power Quad Op-amp L272 Circuit datasheets of op-amp LM 250 KA1458 LF351 op-amp LM319 AD9101 E220 L272 datasheet
2010 - RTAX2000

Abstract: leon3 RTAX2000S LEON3FT vhdl code 64 bit FPU IEEE-1754 STK4050II ASR16 AX2000 RTAX*2000
Text: Research) and one for the Meiko FPU core (available from Sun Microsystems). The floating-point processors , LD FPU M V8 NWP 0 NWIN Figure 6. LEON3 configuration register (%asr17) Field Definitions , ]: FPU option. "00" = no FPU; "01" = GRFPU; "10" = Meiko FPU, "11" = GRFPU-Lite [9]: If set, the , LRSTART 0 M Figure 10. Cache configuration register [31]: Cache locking (CL). Set if cache


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PDF 32-bit RTAX2000 leon3 RTAX2000S LEON3FT vhdl code 64 bit FPU IEEE-1754 STK4050II ASR16 AX2000 RTAX*2000
2006 - piezo injector driver

Abstract: common rail piezo injector driver FDDS10H04 Common rail injector driver diesel piezo injector crdi driver amplifier common rail injector test COMMON RAIL SOLENOID DIRECT INJECTION common rail injector driver application str g 6551
Text: TJ = 150°C ( m ) IOUT(rev) (A) PD (V) Typ. Ton (s) Typ. Toff (s) Typ. Tr (s , Shin-Osaka Meiko Building 8F 4-3-12, Miyahara, Yodogawa-ku Osaka, 532-0003 Japan Tel: 81-6-6398-3670 Fax


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PDF Power247TM, piezo injector driver common rail piezo injector driver FDDS10H04 Common rail injector driver diesel piezo injector crdi driver amplifier common rail injector test COMMON RAIL SOLENOID DIRECT INJECTION common rail injector driver application str g 6551
2001 - circuit diagram of mosfet based smps power supply

Abstract: mosfet triggering circuit for inverter FDS6694 optocoupler pnp or npn phototransistor spice model computer smps circuit diagram optocoupler crossreference MOSFET cross-reference high gain low voltage NPN transistor triac spice model
Text: gate charge · Improved die size · Low RDS(ON) · 12-A, 30-V, 11- m , N-Channel MOSFET · Improved QG x , : 81-3-5275-8390 Fairchild Semiconductor Japan Ltd. Osaka Office Shin-Osaka Meiko Building 8F 4-3-12, Miyahara


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PDF Power247TM, circuit diagram of mosfet based smps power supply mosfet triggering circuit for inverter FDS6694 optocoupler pnp or npn phototransistor spice model computer smps circuit diagram optocoupler crossreference MOSFET cross-reference high gain low voltage NPN transistor triac spice model
sparc v8

Abstract: microsparc microsparc I SPARC T4
Text: S un M icro electro nics July 1997 microSPARCTM-llep DATA SHEET D e s c r ip t io n The , Block Diagram 28 S un M ic r o e l e c t r o n ic s July 1997 m icroSPARCw '-!Iep SPARC , transfers their exe cution to software. The FPU contains a floating-point core based on Meiko design, a , CAS-before-RAS refresh. July 1997 S un M ic r o e le c tr o n ic s 29 microSPARCTM-IIep SPARC v8 , board-level multiplexing. 30 S un M ic r o e le c tr o n ic s July 1997 microSPARCTM-IIep


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PDF 32-bit 32-entry 16-entry sparc v8 microsparc microsparc I SPARC T4
mb86904

Abstract: stp1012pga o124T SPARC v8 architecture BLOCK DIAGRAM nana lhc B235A
Text: P relim i iì u n Business SPARC Technology STP1012 June 1995 m ic r o S P A R C TM -I , Data cache · On-chip M em ory M anagem ent Unit Benefits · Compatible w ith 9400 SPARC applications , folding and single cycle Load/Store instructions. Floating Point Unit (FPU) The FPU (based on Meiko , Normal 10 - Level 15 interrupt 01 - Trap occurred, w hen trap disabled 00 - Reserved JTAG_CK JTA G . M , frequencies. Typically, for 60ns DRAMs: 00 = 70 MHz 01 = 85 MHz. (See Table I ` M em ory Interface Timing) 10 =


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PDF STP1012 32-Bit mb86904 stp1012pga o124T SPARC v8 architecture BLOCK DIAGRAM nana lhc B235A
mb86904

Abstract: MB8690 microsparc M Meiko microsparc I microsparc 1
Text: S un M icro electro nics July 19 97 microSPARCTM-ll DATA SHEET D e s c r ip t io n The , microSPARC-ll System Block Diagram 6 S un M icroelectronics July 1997 m icroSPARC TM -ïï , single cycle Load/Store instructions. Floating Point Unit (FPU) The FPU (based on Meiko design) fully , all the signals necessary to support up to 256 MBytes of system memory. July 1997 S un M icroelectronics 7 m ¡eroS PARCTM-II SPARC v8 32-Bit Microprocessor With DRAM Interface The DRAM bus is


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PDF 32-bit STP1012PGA-70A TP1012PG 1012PG STP1012 mb86904 MB8690 microsparc M Meiko microsparc I microsparc 1
2001 - OCX1601

Abstract: FIN1002 M24B SOT23 74VHC161284 Fairchild Switching Technologies FIN1001 FIN1031 FST3253 GX SOT23 8 bit wide 2 to 1 multiplexer
Text: / 5 5 8 8 14 16 SOIC- SOIC- Wide M M M M M M M MX MX MX MX MX MX MX 16 16 T&R MX MX MX MX 8 8 16 16 16 16 8 14 24 SOIC SOIC M M M M M M , 12-Bit to 24-Bit Multiplexer/Demultiplexer Bus Switch 16 16 M 56/54 48 48 56/54 56 56 48 , M QSCX QSC M MTCX GX M MX M M MX MX WM WM WM MTC WMX MTC WMX , MTDX MTD MTD MTDX MTDX QSCX M MX MTCX GX MTC MTD MTD MTD MTCX MTDX MTDX


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PDF Power247TM, OCX1601 FIN1002 M24B SOT23 74VHC161284 Fairchild Switching Technologies FIN1001 FIN1031 FST3253 GX SOT23 8 bit wide 2 to 1 multiplexer
mb86904

Abstract: microsparc SUN MICROELECTRONICS CPGA321 MB8690 STP1012PGA STP1012PGA-85 SPARC v8 architecture BLOCK DIAGRAM sparc v8 STP1012PGA-110
Text: (based on Meiko design) fully executes all single and double precision FP instructions as defined in the , col_addr (n+2) :Y çol_addr (n+4) Y col_addr ( m ) Figure 3. Page Mode Read Following a Read July 1997 Sun , -Bit Microprocessor With DRAM Interface MEMADDR[11:0 I col_addr ( m ) MEMDATA[63:0] I C f I I col_addr (ri) ï col_à ddr (p) iï col_addr (q) Ï I DC I r\ n I i r m RMRAMMpnÄMMMMMm IÖ a Figure 4. Page , \ / i! 1 m ,y n+1A m X ïf


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PDF 32-Bit STP1012 STP1012PGA-70A STP1012PGA-85 STP1012PGA-110 mb86904 microsparc SUN MICROELECTRONICS CPGA321 MB8690 STP1012PGA SPARC v8 architecture BLOCK DIAGRAM sparc v8
1997 - mb86904

Abstract: STP1012PGA STP1012PGA-85 microsparc RISC processor STP2001 SPARC v8 architecture BLOCK DIAGRAM MB8690 microsparc SPARC 7 sparc v8
Text: /Store instructions. Floating Point Unit (FPU) The FPU (based on Meiko design) fully executes all , MEMADDR[11:0 col_addr (n) col_addr (n+2) col_addr (n+4) col_addr ( m ) CAS_L MEMDATA[63:0] n n+ n+ m RAS_L MWE_L Figure 3. Page Mode Read Following a Read July 1997 7 , col_addr ( m ) col_addr (n) col_addr (p) col_addr (q) CAS_L m , m +1 MEMDATA[63:0] n p , col_addr ( m ) col_addr ( m ) CAS_L MEMDATA[63:0] m , m +1 m RAS_L MWE_L Figure 5. Page


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PDF STP1012 32-Bit STP1012PGA-70A STP1012PGA-85 STP1012PGA-110 mb86904 STP1012PGA STP1012PGA-85 microsparc RISC processor STP2001 SPARC v8 architecture BLOCK DIAGRAM MB8690 microsparc SPARC 7 sparc v8
qml-38535

Abstract: VDB25 AT7913 5962-E266-13 smd marking m11 MICROCIRCUIT ASIC MEMD9 VSA10 5962-10A03
Text: boilerplate in according with MIL-PRF-38535 requirement. - phn DATE (YR-MO-DA) 13-02-11 APPROVED Thomas M , Phu H. Nguyen APPROVED BY 10-01-12 DRAWING APPROVAL DATE Thomas M . Hess DLA LAND AND MARITIME , reliability (device classes Q and M ) and space application (device class V). A choice of case outlines and , letter identifying the product assurance level as follows: Device class M Device requirements , or MIL-PRF-38535, appendix A for device class M . STANDARD MICROCIRCUIT DRAWING DLA LAND AND


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PDF MIL-PRF-38535 7913E2U-MQ AT7913E2U-SV AT7913E2U-SR AT7913EYC-MQ AT7913EYC-SV AT7913EYC-SR F7400 qml-38535 VDB25 AT7913 5962-E266-13 smd marking m11 MICROCIRCUIT ASIC MEMD9 VSA10 5962-10A03
2001 - SPARC v9 architecture BLOCK DIAGRAM

Abstract: No abstract text available
Text: instructions and transfers their execution to software. The FPU contains a floating-point core based on Meiko , Seating Plane (Note 3) 0.15 C -C0.75 ±0.15 (Note 2) Y W V U T P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8


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PDF STP1100BGA 32-bit 32-entry 16-entry STP1100BGA-100 SPARC v9 architecture BLOCK DIAGRAM
1997 - instruction set Sun SPARC T3

Abstract: sparc v8 SPARC v8 architecture BLOCK DIAGRAM sun sparc v5 microsparc microsparc RISC processor SPARC 7 WD 969 microsparc I STP1100BGA-100
Text: software. The FPU contains a floating-point core based on Meiko design, a fast-multiplier, a 3 , 16.10 REF Y W V U T 1.27 REF R P N M L K J H G F E D Pin 1 Index Area C B


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PDF STP1100BGA 32-Bit 32-entry 16-entrNo instruction set Sun SPARC T3 sparc v8 SPARC v8 architecture BLOCK DIAGRAM sun sparc v5 microsparc microsparc RISC processor SPARC 7 WD 969 microsparc I STP1100BGA-100
1997 - sparc v8

Abstract: instruction set Sun SPARC T3 microsparc STP1100BGA-100 instruction set Sun SPARC T2 sun sparc v5 Sun Sparc II
Text: software. The FPU contains a floating-point core based on Meiko design, a fast-multiplier, a 3 , M L K J H G F E D Pin 1 Index Area C B A 1 2 3 4 5 6 7 8 9


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PDF STP1100BGA 32-Bit 32-entry 16-entry sparc v8 instruction set Sun SPARC T3 microsparc STP1100BGA-100 instruction set Sun SPARC T2 sun sparc v5 Sun Sparc II
1997 - STP1100BGA-100

Abstract: "32-Bit Microprocessor" SPARC v8 architecture BLOCK DIAGRAM SPARC V8
Text: contains a floating-point core based on Meiko design, a fast-multiplier, a 3-instruction deep instruction , 1.27 REF R P N M L K J H G F E D Pin 1 Index Area C B A 1 2 3 4 5


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PDF STP1100BGA 32-Bit 32-entry 16-entry STP1100BGA-100 STP1100BGA-100 "32-Bit Microprocessor" SPARC v8 architecture BLOCK DIAGRAM SPARC V8
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