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LSI CoreWare CW33300 Datasheets Context Search

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1998 - LSI Logic ASIC

Abstract: USB Hub LSI coreware library USB PANEL LSI LOGIC
Text: design of highly integrated hub-enabled system ASICs. As an element of LSI Logic's proven CoreWare , USB Hub Core Hub Core for Universal Serial Bus Solutions Overview LSI Logic's USB Hub Core, a component of LSI Logic's comprehensive Universal Serial Bus (USB) solution set, is a flexible and , Supports low- and full-speed data rates Gated clock option SCAN-inserted netlist Interfaces with LSI Logic's USB transceiver I/Os · Verified functionality and timing in LSI Logic's ASIC technologies


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1998 - LSI coreware library

Abstract: LSI LOGIC OakDSPCore "Hot Plug and Play"
Text: combining the USB Host Core and LSI Logic's USB transceiver I/Os with other CoreWare components and , , including peripherals and hub applications. As an element of LSI Logic's proven CoreWare library, it is , component of LSI Logic's comprehensive USB solution set, is a flexible and configurable core that manages , simplifies the design of USB-enabled embedded systems and system logic. As an element of LSI Logic's proven CoreWare ® library, the USB Host Core is fully supported by industry-leading design methodology


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2000 - EZ4021

Abstract: No abstract text available
Text: analysis and ATPG), the EZ4021 further enhances LSI Logic's MIPS-based embedded processor line. The EZ4021 EasyMACRO is designed for rapid system on a chip ASIC integration through LSI Logic's CoreWare ® design , : 44.1344.481039 ISO 9000 Certified LSI Logic logo design, CoreWare and MiniRisc are registered trademarks , Corporation. All rights reserved. CoreWare Design Program The EZ4021 MiniRISC is a member of the LSI , EZ4021 extends the LSI Logic MIPS MiniRISC® family with a high performance 64-bit microprocessor. The


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PDF EZ4021 64-bit 250MHz 64-bit
2002 - ARM926EJ-S

Abstract: ARM processor data flow ARM926EJScore embedded trace macrocell ARM926EJ etm lsi logic
Text: and CoreWare are trademarks or registered trademarks of LSI Logic Corporation. ARM is a registered , reserved. To further assist customers with their designs, LSI Logic provides specialized ARM CoreWare , 266/200MHz ARM926EJ-STM Cores with Linux and Java Support OVERVIEW FEATURES LSI Logic , core[1] [2] - LSI Logic Gflx 0.11 micron (drawn), 1.2V process technology The ARM926EJ-S is a , the multi-layer AMBA bus standard. LSI Logic offers both AMBA subsystem reference designs, and a


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PDF 266/200MHz ARM926EJ-STM ARM926EJ-S 266MHz ARM926EJ-S ARM processor data flow ARM926EJScore embedded trace macrocell ARM926EJ etm lsi logic
2001 - ARMv5TE instruction set

Abstract: ARM946E-STM ARMv5TE ARM946E-S ARM processor data flow design flow soc architecture ARM966E-S CW001100 TCMS
Text: their designs, LSI Logic provides specialized ARM CoreWare ® integration support through our team of regionally based field CoreWare engineers. For more information please call: LSI Logic Corporation North , , CoreWare and FlexStream are registered trademarks and G12 is a trademark of LSI Logic Corporation. ARM and , onto LSI Logic's G12P 0.18 micron high performance process technology. · 200 MHz operating frequency , into your System-on-Chip (SoC) design. · Implemented on LSI Logic's G12P 0.18 micron, 1.8 V


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PDF CW001100 ARM946E-STM ARM946E-STM, ARM946E-S, R20050 ARMv5TE instruction set ARMv5TE ARM946E-S ARM processor data flow design flow soc architecture ARM966E-S TCMS
2001 - diode E1110

Abstract: E1110 e110 GMII Block diagram of 8-1 multiplexer design logic Gigabit Logic LSI LOGIC GMII layout LSI Logic ASIC
Text: Gigabit Media Access Controller The E1110 complements LSI Logic's existing CoreWare portfolio that , site www.lsilogic.com LSI Logic logo design, ZSP and CoreWare are registered trademarks of LSI , . Designed on LSI Logic's 0.18micron G12 process technology, the E1110 can support applications requiring , integrated E110 Flow Control Module allows the E1110 CoreWare ® to interface directly with the E110 CoreWare , with LSI Logic, designers can have access to a variety of verified building blocks to quickly design


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PDF E1110 18micron C20041 diode E1110 e110 GMII Block diagram of 8-1 multiplexer design logic Gigabit Logic LSI LOGIC GMII layout LSI Logic ASIC
1999 - verilog code for 16 bit risc processor

Abstract: 4102TM verilog code for 32 bit risc processor mips vhdl code MIPS16 vhdl code mips code vhdl code for uart vhdl code for risc processor 32 bit risc processor using vhdl EZ4102
Text: for System-On-a-Chip integration through LSI Logic's CoreWare ® design methodology. Integration with other CoreWare library elements provides the flexibility to develop a variety of solutions from a , : 81.3.5463.7820 ISO 9000 Certified LSI Logic logo design, CoreWare and CoreWare logo design and G10 are , LSI Logic's embedded RISC processor family. This core is the second generation of the widely used , 0.25-micron (.18 Leff) technology, 2.5V process. As such power dissipation is .5mW/MHz. LSI


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PDF 4102TM MIPS16, 16-bit 32-bit MIPS16 MIPS16 85MHz TR4102 C20027 verilog code for 16 bit risc processor verilog code for 32 bit risc processor mips vhdl code vhdl code mips code vhdl code for uart vhdl code for risc processor 32 bit risc processor using vhdl EZ4102
2001 - design flow soc architecture

Abstract: ARM processor data flow ARM9E-S ARM9E-STM ARM966E-S CW001105 ARMv5TE instruction set ARMv5TE LSI cell library
Text: Engineers. www.lsilogic.com LSI Logic logo design, CoreWare and FlexStream are registered trademarks , CW001105 processor core is a 200 MHz implementation of the popular ARM966E-STM, synthesized onto LSI Logic , =1.8 V, slow process · Implemented on LSI Logic's G12P 0.18 micron, 1.8 V process · 0.9mW/MHz , portfolio of AMBA peripherals ETM (Embedded Trace Macrocell) · Regional ARM CoreWare design support , complete CPU subsystem design. LSI Logic offers both an AMBA subsystem reference design, and a library of


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PDF CW001105 ARM966E-S ARM966E-STM, ARM966E-S, C20042 design flow soc architecture ARM processor data flow ARM9E-S ARM9E-STM ARMv5TE instruction set ARMv5TE LSI cell library
2001 - Block diagram of 8-1 multiplexer design logic

Abstract: E1110 GMII layout
Text: E1110 MACs CoreWare , G12, the LSI Logic logo, The Communications Company and ZSP are trademarks or , . Designed on LSI Logic's 0.18-micron G12 process technology, the E1110 can support applications requiring , integrated E110 Flow Control Module allows the E1110 CoreWare ® to interface directly with the E110 CoreWare , applications PCS Optional Module E1110 Gigabit Media Access Controller The E1110 complements LSI Logic's existing CoreWare portfolio that includes E110, CAMs, embedded FPGA, high speed I/Os, ARM


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PDF E1110 18-micron C20041 Block diagram of 8-1 multiplexer design logic GMII layout
2005 - ARM1156T2-S

Abstract: AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture PL022 AXI-64 interface ARM processor data flow PL300 AMBA AHB to AXI AMBA AHB bus protocol ARM1156T2S
Text: design, RapidChip, the RapidChip logo, CoreWare , and ZSP are trademarks or registered trademarks of LSI , 450 MHz timing-closed hardmac OVERVIEW The LSI Logic implementation of the ARM1156T2-S processor , higher-performance option to the ARM966E-S processor with minimal increase in cost. As a member of the CoreWare ® IP , right-first-time SOC design. LSI Logic's ARM1156T2-S hardmac is already timing closed at 450 MHz, thereby , AMBATM 3.0 AXI bus specification for high-performance systems requiring high data throughput. · LSI


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PDF ARM1156T2-S CW001145 ARM966E-S C20069 AMBA AXI to APB BUS Bridge AMBA AXI to APB BUS Bridge architecture PL022 AXI-64 interface ARM processor data flow PL300 AMBA AHB to AXI AMBA AHB bus protocol ARM1156T2S
1999 - LSI LOGIC

Abstract: CW901101 8991K
Text: , memories and I/Os. Together with the CW90110, LSI Logic offers a complete digital CoreWare ® library of , predictable results when using LSI Logic's design methodology and the companion CoreWare library of , digital TVs (DTV). The core is compatible with LSI Logic's FlexStream® ASIC design environment to enable , for their target application prior to instantiating the core into the ASIC. LSI Logic uses a , transistor level up to system level. LSI Logic's wide portfolio of mixed-signal cores, including data


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PDF CW901101 10-Bit 45MSPS B20024 LSI LOGIC 8991K
1996 - LSI LOGIC

Abstract: "USB Transceiver" LSI coreware library "Hot Plug and Play"
Text: USB Function Core Overview LSI Logic's USB Function Core is a flexible and configurable core , peripheral single-chip systems. Combining the USB Function core and LSI Logic's USB transceiver I/Os with other CoreWare ® cores and customer-defined logic creates cost-effective solutions for USB peripherals , option SCAN inserted netlist Interfaces with LSI Logic's USB transceiver I/Os Verified functionality and timing for LSI Logic's ASIC technologies s s s s s s s s s s Ensures "hot plug


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PDF C20022 LSI LOGIC "USB Transceiver" LSI coreware library "Hot Plug and Play"
1999 - G11 transistor

Abstract: 6T SRAM LSI ASIC lsi gigablaze transceiver transistor G11 ADC Verilog Implementation
Text: Certified LSI Logic logo design, Coreware , MiniRISC, FlexStream and Gigablaze are registered trademarks , LSI Logic's G11 ASIC product family offers two distinct products-one optimized for high performance , combination of LSI Logic's G11 product family, advanced design methodology, extensive on-chip memory capabilities, mixed signal options, CoreWare ® design program and the industry's broadest package choices , implemented with nominal power dissipation as low as 0.03 uW/gate/MHz. LSI Logic's G11 family offers a


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PDF G11-p) G11-v 18-micron B20017 G11 transistor 6T SRAM LSI ASIC lsi gigablaze transceiver transistor G11 ADC Verilog Implementation
1999 - G12-l

Abstract: LSI Logic ASIC g12 High Voltage G12L g12 transistor G12 000
Text: optimization, CoreWare library, and extensive LSI Logic and EDA tool support for system, logic and physical , ASIC technology with 0.18 micron L-drawn Overview LSI Logic's G12 ASIC Cell-Based product, with its , 0.13 micron L-effective transistors The powerful combination of LSI Logic's G12 product , methodology, CoreWare ® design program and an industry-leading package offering, raises the bar on , +32.11.300.351 www.lsilogic.com LSI Logic Corporation North American Headquarters Milpitas, CA Tel


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PDF 18-micron 13-micron B20023 G12-l LSI Logic ASIC g12 High Voltage G12L g12 transistor G12 000
2002 - ARMv5TE

Abstract: ARMv5TE instruction set ARM966E-S ARMv5 ARM9E-STM
Text: Fax: 81 3 5463 7820 LSI Logic web site: www.lsilogic.com LSI Logic logo design, CoreWare , ZSP , FlexCore® ARM966E-S 32-bit RISC Processor Cores OVERVIEW FEATURES AND BENEFITS LSI Logic , needs. ® TM By choosing a FlexCore ARM966E-S processor core from LSI Logic, systemon-chip (SoC , week, and complete CoreWare ® deliverables within four weeks. The ARM966E-S, which is based on the five , Regional CoreWare Design Support Notes: [1] Worst case conditions [2] Core only, estimated 210


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PDF ARM966E-S 32-bit G12TM ARMv5TE ARMv5TE instruction set ARMv5 ARM9E-STM
2004 - ARM926EJ-S

Abstract: ARM926EJ-S Implementation Guide 011U LogicVision Preliminary Gflx-r RapidChip Cell Technology Data LSI Rapidchip cpdin ARM926EJ-S errata
Text: for complex, highperformance applications. 1.1.2 CoreWare IP Program The LSI Logic CoreWare IP , deliverables you receive with the ARM926EJ-S Processor. Using the LSI Logic design program and CoreWare IP , performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using production parts. This document contains proprietary information of LSI , without the express written permission of an officer of LSI Logic Corporation. Document DB08


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PDF ARM926EJ-STM cw001124 DB08-000262-00 DB08-000262-00, ARM926EJ-S ARM926EJ-S Implementation Guide 011U LogicVision Preliminary Gflx-r RapidChip Cell Technology Data LSI Rapidchip cpdin ARM926EJ-S errata
2002 - MIPS32 cache

Abstract: 4KEC MIPS32 Mips MIPS32 application MIPS64 MIPS32 memory interface MIPS32 instruction set
Text: , CoreWare , ZSP, and FlexStream are trademarks or registered trademarks of LSI Logic Corporation. MIPS is a , FlexCore® MIPS32TM 4KEcTM 32-bit RISC Processor Cores OVERVIEW FEATURES AND BENEFITS LSI , customer needs. · Up to 200 MHz performance on LSI By choosing a FlexCore MIPS32 4KEc processor core from LSI Logic, system-on-chip (SoC) designers can define their specific needs for instruction and , model can be provided within a week, and complete CoreWare ® deliverables within four weeks. · Power


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PDF MIPS32TM 32-bit MIPS32 G12TM MIPS32 cache 4KEC Mips MIPS32 application MIPS64 MIPS32 memory interface MIPS32 instruction set
2004 - 011U

Abstract: LSI coreware library ARM11 lsi logic ARM11 "instruction set summary" armv5te cp14 ARM coprocessor
Text: ACKNOWLEDGMENT LSI Logic, the LSI Logic logo design, CoreWare , G12, Gflx, GigaBlaze, HyperPHY, RapidChip , complex, high-performance applications. 1.1.2 CoreWare IP Program The LSI Logic CoreWare IP library , Introduction Copyright © 2003 by LSI Logic Corporation. All rights reserved. 1.3.1 CoreWare IP , performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using production parts. This document contains proprietary information of LSI


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PDF ARM966E-STM cw001163 DB08-000257-00 DB08-000257-00, ARM966E-S 011U LSI coreware library ARM11 lsi logic ARM11 "instruction set summary" armv5te cp14 ARM coprocessor
2004 - FCBGA-896

Abstract: B200-44 ARM966 B20044 serdes LSI RC11XT531 RC11XT432 RC11XT416 RC11XT404 ARM926
Text: CoreWare and CoreWare are trademarks or registered trademarks of LSI Logic Corporation. ARM is a , engineering costs that are common to all LSI Logic RapidChip Platform ASIC families, combined with , channels. LSI Logic has five generations of integrated SerDes proven in volume production. There are two , resource usage · Flexible user configurable I/Os with CoreWare IP can be combined with these diffused , a designer can efficiently implement an ARM966 at 212.5MHz. LSI Logic also provides System


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PDF 250MHz RC11XT531 FCBGA-896 B200-44 ARM966 B20044 serdes LSI RC11XT531 RC11XT432 RC11XT416 RC11XT404 ARM926
2001 - MIPS

Abstract: MIPS R4000 EZ4030 R4000 mips r4000 block diagram
Text: analysis and ATPG), the EZ4030 further enhances LSI Logic's MIPS-based embedded processor line. The EZ4030 EasyMACRO core is designed for rapid system-on-a-chip ASIC integration through LSI Logic's CoreWare ® design , chain, software examples and documentation. COREWARE DESIGN PROGRAM As part of LSI Logic's extensive , : Logic web site: www.lsilogic.com LSI Logic logo design, CoreWare , MiniRisc and EasyMACRO are , MICROPROCESSOR CORE OVERVIEW The EZ4030 extends the LSI Logic MIPS MiniRISC® family with a high performance 64


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PDF EZ4030 240MHz 64-bit MIPS MIPS R4000 R4000 mips r4000 block diagram
2002 - ARMv5TE instruction set

Abstract: ARM946E-S ARM9E-S ARMv5TE arm9e ARM946 ARMv5
Text: LSI Logic logo design, CoreWare , ZSP, and FlexStream are trademarks or registered trademarks of LSI , LSI Logic offers FlexCore ARM946E-S processor cores available on both our GflxTM 0.11 micron (drawn , customer needs. ® TM By choosing a FlexCore ARM946E-S processor core from LSI Logic, systemon-chip , application, a design simulation model can be provided within a week, and complete CoreWare ® The ARM946E-S , four weeks. ASIC library · Up to 250 MHz performance available on LSI Logic's GflxTM 0.11 micron


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PDF ARM946E-S 32-bit ARM946E-S G12TM ARMv5TE instruction set ARM9E-S ARMv5TE arm9e ARM946 ARMv5
2004 - transistor P2P

Abstract: FCBGA-896 LSI Rapidchip DDR PHY ASIC epbga RC1832 RC1812 RC1845 RC1847 RC1880
Text: CoreWare ® processor subsystem support - AMBA® subsystem - AMBA peripherals · Optimized package design , 200MHz. Soft processors can be implemented on any RapidChip Foundation slice. LSI Logic provides System , channels of high-speed GigaBlaze® SerDes operating at up to 3.2 Gb/s. LSI Logic has five generations of integrated SerDes proven in volume production. Soft CoreWare IP combined with these SerDes can support a , , which are available for other uses if DDR is not required. For more information please call: LSI


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PDF B20041 transistor P2P FCBGA-896 LSI Rapidchip DDR PHY ASIC epbga RC1832 RC1812 RC1845 RC1847 RC1880
2000 - cdma baseband processor

Abstract: LSI LOGIC modem LSI LOGIC QCELP-13 OakDSPCore QCELP13 F20031 cbp3.0 "single chip" cdma baseband rf
Text: arena, LSI Logic's unique CoreWare ® design methodology and library of building blocks provides system , CoreWare are registered trademarks and G11 is a trademark of LSI Logic Corporation. OakDSPCore is a , · An ARM7TDMI TM control processor (CP). Overview The LSI Logic CBP3.0 chip is the most , /ROM, data RAM, digital logic for most modem functions, accelerators and glue logic. · · LSI , size: The CBP at 16mm x 16mm with 0.8mm pitch, featuring LSI Logic's 280-pin Chip Scale Package (CSP


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PDF G11TM 18-micron F20031 cdma baseband processor LSI LOGIC modem LSI LOGIC QCELP-13 OakDSPCore QCELP13 F20031 cbp3.0 "single chip" cdma baseband rf
2002 - ARMv5TEJ

Abstract: ARM7EJ-S ARMv5T jazelle ARMv5 ARM processors LSI coreware library
Text: LSI Logic logo design, CoreWare and FlexStream are trademarks or registered trademarks of LSI Logic , BENEFITS LSI Logic offers FlexCore ARM7EJ-S processor cores available on both our GflxTM 0.11 micron , processor core from LSI Logic, system-onchip (SoC) designers can define their specific needs for target , configuration, a design simulation model can be provided within a week, and complete CoreWare ® deliverables , instruction set also includes the 16-bit Thumb instruction set and Java bytecode execution. LSI Logic is a


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PDF 32-bit G12TM ARMv5TEJ ARM7EJ-S ARMv5T jazelle ARMv5 ARM processors LSI coreware library
2001 - ARM7TDMI-S

Abstract: LSI LOGIC ARM7TDMI-S Datasheet CW001010 AMBA APB UART
Text: LSI Logic's G12P 0.18 micron high performance process technology. The ARM7TDMI-S, licensed from ARM , . · 100 MHz Operating frequency o Tj =115 C, Vdd =1.8 V, slow process · Implemented on LSI Logic , Extensive portfolio of AMBA peripherals · Regional ARM CoreWare design AMBATM AHB BUS AHB to APB , AMBA peripherals. LSI Logic offers both an AMBATM subsystem reference design, and a library of , widely used industry standard bus. The core is implemented in LSI Logic's G12P high performance 0.18


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PDF CW001010 32-bit 16-bit C20048 ARM7TDMI-S LSI LOGIC ARM7TDMI-S Datasheet AMBA APB UART
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