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Part Manufacturer Description Datasheet Download Buy Part
LT3439EFE#TRPBF Linear Technology LT3439 - Slew Rate Controlled Ultralow Noise 1A Isolated DC/DC Transformer Driver; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
LT3439EFE#PBF Linear Technology LT3439 - Slew Rate Controlled Ultralow Noise 1A Isolated DC/DC Transformer Driver; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
LT3439EFE Linear Technology LT3439 - Slew Rate Controlled Ultralow Noise 1A Isolated DC/DC Transformer Driver; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
LT3439EFE#TR Linear Technology LT3439 - Slew Rate Controlled Ultralow Noise 1A Isolated DC/DC Transformer Driver; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
PMP5660.1 Texas Instruments Multi-Transformer 2x25V (390V@192mA)
PMP5660.2 Texas Instruments Multi-Transformer 2x25V (50V@700mA)

LSE B9 transformer Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2001 - LSE B3 transformer

Abstract: LSE B10 transformer LSE B3 LSE B4 transformer LXT400NE LSE B6 transformer LSE B3 transformer datasheet LSE B3 transformer how to test LSE B9 transformer LXT400PE
Text: - LXT400 Figure 1. LXT400 Block Diagram TPOS TNEG TCLK LPBK + AMI Coder RESET LSE , Pin Assignments 28-Pin PLCC Table 1. TEST1 RRING RTIP VINT EQLOUT TEST2 LSE FP2 LPBK AGND RCLK RPOS RNEG FP3 5 6 7 8 9 10 11 4 3 2 1 28 27 26 EQLOUT TEST2 LSE , goes to a high impedance state when LSE is High. If LSE is tied Low, the LS output represents LOS only , driver ground. Tie to AGND, pin 7. 26 LSE I Line Status Enable. Active Low enable for the LS


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PDF LXT400 56/DDS LXT400 LXT400PE 28-Pin LXT400PE LSE B3 transformer LSE B10 transformer LSE B3 LSE B4 transformer LXT400NE LSE B6 transformer LSE B3 transformer datasheet LSE B3 transformer how to test LSE B9 transformer
1998 - LSE B10 transformer

Abstract: LSE B3 transformer LXT400NE LSE B3 LSE B9 transformer LSE B9 LSE B4 transformer LXT400PE LSE B6 transformer LSE -B3
Text: RESET LSE LS FP1-FP4 MCLK1 MCLK2 RCLK TTIP Driver ­ Control Logic TRING VREF , DESCRIPTIONS Figure 1: LXT400 Pin Assignments 28-Pin PLCC TEST1 RRING RTIP VINT EQLOUT TEST2 LSE EQLOUT TEST2 LSE FP4 TTIP DGND DVCC TRING AVCC FP1 RESET TCLK TPOS TNEG FP2 LPBK AGND , falling edges of RCLK. LS goes to a high impedance state when LSE is High. If LSE is tied Low, the LS , DGND - Driver Ground. Transmit driver ground. Tie to AGND, pin 7. 26 LSE I Line


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PDF LXT400 56/DDS LXT400 DS-T400-R3 LSE B10 transformer LSE B3 transformer LXT400NE LSE B3 LSE B9 transformer LSE B9 LSE B4 transformer LXT400PE LSE B6 transformer LSE -B3
1996 - LSE B3 transformer

Abstract: LSE B10 transformer LSE B3 LSE B4 transformer LSE B9 transformer multiplexers 74 LS 150 LSE B6 transformer LSE B10 AMI coder LSE B6
Text: PRODUCTS Transmit Filter ETHERNET HUB AND REPEATER PRODUCTS RESET LSE LS FP1-FP4PPLICATION , 28 27 26 25 24 23 22 21 20 19 18 17 16 15 EQLOUT TEST2 LSE FP4 TTIP DGND DVCC , RCLK RPOS RNEG FP3 LS MCLK1 MCLK2 EQLOUT TEST2 LSE 4 5 3 2 1 28 27 26 25 , impedance state when LSE is High. If LSE is tied Low, the LS output represents LOS only. Factory Test , . Transmit driver ground. Tie to AGND, pin 7. 9 to Low to read LS serial data. LSE is sampled on the


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PDF LXT400 SW56/DDS LXT400 16-bit LSE B3 transformer LSE B10 transformer LSE B3 LSE B4 transformer LSE B9 transformer multiplexers 74 LS 150 LSE B6 transformer LSE B10 AMI coder LSE B6
LSE B9 transformer

Abstract: LSE B9 valeo video auxiliary data 8110K 12 pin transformer sony 50/LSE B9 transformer
Text: CXA1389; The S B X 1 601 is a scrambler including the paral lel to serial transformer . The CXA1389 is a , M D0 AUDMD HPLN AUX0 AUX1 AU X2 AU X3 `O E P O L S E L ERROR VPU LSE IT R ST M G I I I I I I I I , -8) Bits 10 bits 9 bits Composite Digital Video Auxiliary Data (inverted AU X8 is added as b9 in the device , a s follows; Logic High: R E S E T Logic Low: VAREN , ENMOD, EXCH, SW CH, O EP O LSE L, D B N (at , R S Timing Composite Sync P ulse_ Data Start P u lse _ Data Insert P ulse_ NTSC/PAL


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PDF 8110K SBX1601 CXA1389; CXA1389 160mW 734MHz 105mW 145mW 318MHz LSE B9 transformer LSE B9 valeo video auxiliary data 8110K 12 pin transformer sony 50/LSE B9 transformer
LSE B3 transformer

Abstract: LSE B9 LSE B9 transformer ATIC 39 b4 ttp 916 LSE B4 transformer 62310
Text: EQLOUT TEST2 LSE FP4 TTIP DGND DVCC TRING AVCC FP1 RESET TCLK TPOS TNEG RTIP RRING TEST1 / EQLOUT TEST2 LSE m 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 25 24 FP2 LPBK AGND RCLK RPOS , impedance state when LSE is High. If LSE is tied Low, the LS output represents LOS only. 2 f r a LEVEL , enable for the LS serial port. This pin must transition from High to Low to read LS serial data. LSE is , 21 24 22 23 26 AVCC TRING TTIP DVCC DGND LSE I 0 0 I I IC Power Transmit Ring Transmit Tip


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PDF LXT400 LXT400 LSE B3 transformer LSE B9 LSE B9 transformer ATIC 39 b4 ttp 916 LSE B4 transformer 62310
LSE B3 transformer

Abstract: LSE B9 transformer mini equalizer LSE B9
Text: occur on falling edges of RCLK. LS goes to a high impedance state when LSE is High. If LSE is tied Low , must transi tion from High to Low to read LS serial data. LSE is sampled on the rising edges of RCLK , left open when not used. 20 21 24 22 23 26 AVCC TRING TTIP DVCC DGND LSE 0 0 I 27 28 , -bit serial word enabled by pulling LSE Low for 8 or 16 bit-periods as shown in Figures 12 and 13. Refer to , High Level Detection when High Receive Loss of Signal when High B it# b8 b9 blO b ll bl2 bl3 bl4 bl5


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PDF LXT400 LXT400 LXT400PE 28-Pin LXT400PE LSE B3 transformer LSE B9 transformer mini equalizer LSE B9
LSE B3 transformer

Abstract: LSE B3 transformer how to test LSE B3 LSE -B3 LSE B4 transformer LSE B6 transformer LSE B6 LSE transformer LSE B4
Text: J 2 3 3 EQLOUT TEST2 LSE TTIP DGND DVCC TRING AVCC RESET TCLK TPOS TNEG Table 1: Pin , impedance state when LSE is high. If LSE is tied low, the LS output represents LOS only and can be used as a , 17 21 18 19 20 22 23 TCLK RESET AVCC TTIP THING DVCC DGND LSË TEST2 I I I O 0 Transmit , enable for the LS serial port. This pin musttransition from high to low to read LS serial data. LSE is , 400 -400 -400 - | 400 400 - 40 LS delay from RCLK falling edge LSE setup to RCLK rising


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PDF LXT456 LXT456 pulse150 PDS-T456-0590-2k LSE B3 transformer LSE B3 transformer how to test LSE B3 LSE -B3 LSE B4 transformer LSE B6 transformer LSE B6 LSE transformer LSE B4
LSE B9

Abstract: LSE B6
Text: VCE = 40Vdct t : ; lse c 43 2N 5666 5 0.75 — mAdc B-6 3051 VCE = 200Vdc, t = lsec VCE = 3Vdc, t = lse c 's , 1 Unclam ped Reverse Biased Second Breakdown 4— Ade B-7 3051 — Ade B-7 3051 Vcs = 37.5Vdc, t = lse c 27 Clamped Reverse Biased Second Breakdown 5 0.4 — mAdc B-7 3051 VCE = 200Vdc, t = lse c S/8 U ES, E S/I 0.81 — mj B-8 3053 le = 5Adc, L = .065m h 500 - mj B-9 3053


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PDF T347Tb3 MIL-S-19500/455 LSE B9 LSE B6
LSE B10

Abstract: No abstract text available
Text: " _t0H " B C K IN Pu lse Cycle Tim e *ecv : 100ns (min) B C K IN Pu lse Width High •bch : 50n s (min) B C K IN Pu lse Width Low W : 50n s (min) B C K IN R isin g Edge to L R C IN , 3 1 ^ 4 407 ■MAPPING OF PROGRAM REG ISTERS B 14 B 13 B12 B11 B10 B9 B8 , 13B 1 2 B11 B10 B9 B8 res res res res res B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 LDR AR7 AR6 , (A1 = 1, AO = 0) B15 B14 B13 B12 B11 B10 B9 B8 res res res res res A1 B7 B6 B5 B4 B3


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PDF PCM1723 24-BIT PCM1723 256fs 384fs 27MHz 16kHz, 05kHz, LSE B10
Not Available

Abstract: No abstract text available
Text: IN P u lse C ycle T im e : 3 0n s (min) LB : 3 0n s (min) D IN S e t-up T im e DS , ® : 100 ns (m in) BCH B C K IN P u lse W idth Low FIGURE 3. Audio D ata Input Timing. BC Y B C K IN P u lse W idth High DH : 3 0n s (min) 1.4V X 2 DC \ 1 .4V TYPICAL , I res I res res B9 | LD L B8 | AL7 A6 |_ ÄL5 AL4 AL3 AL2 B1 , log A T T - 201os( ^ ) = B15 B 14B 13 B12 B11 B10 B9 res A1 - let x = 0 REGISTER 0 (A1


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PDF PCM1720 24-BIT PCM1720 256fs 384fs 16kHz 96kHz 256fs/384fs
Not Available

Abstract: No abstract text available
Text: Devices B8 B9 B9 B10 2 B7 BIO t These sym bols are in accordance with A N SI/IEEE , |*-«su-«l*~lh~*j Closed Closed V n ^-sv o D A TA INPUT V LO W -LEVEL PU LSE LSI , L T A G E W A VEFO R M S PU LSE D U RATIO N S 3V V 7 |\ 0 V I*- *f-< PHL H , H IG H-LEVEL PU LSE TIM ING INPUT IN-PHASE O U TPU T Open Closed


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PDF SN54ALS29861, SN54ALS29862 SN74ALS29861, SN74ALS29862 10-BIT D2915. AM29861
LSE B9

Abstract: No abstract text available
Text: ÛUALITY SEMICONDUCTOR INC LSE D 7m3bô03 OOGlMll 355 QS3384, QS32384 Q · · · High Speed CMOS 10-bit Bus Switches QS32384 FEATURES/BENEFITS 5£1 switches , 17 3 VCC B9 A9 A8 B8 B7 A7 BES AO B1 A2 B3 A4 O o U) Û. ·s Q CL A6 16 B6 15 B5 14 A5 13 BEB BEB B5 A6 B7 A8 ALL PINS TOP VIEW B9 ABSOLUTE MAXIMUM RATINGS Supply , C O N D U C T O R INC LSE D D 7Mbba03 0001414 QS3384, QS32384 0b4 H ( 2 S I POWER SUPPLY


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PDF QS3384, QS32384 10-bit 24-pin QS3384 QS32384 MDSL-00032-01 LSE B9
2005 - str 5 q 0765 POWER SUPPLY CIRCUIT

Abstract: zener diode ST 4148 zener T 4148 STR 4148 TRANSISTOR SE 135 magnetic amplifier saturable core diode LN 4148 on ic 4148 details ZENER 4148 SC4901
Text: all-MOSFET topology that allows synchronous rectification and post regulation of transformer isolated , sharing and hot swap features. All devices are synchronised to the transformer winding. The current , pulse transformer . SC4901 has an undervoltage lockout with typical turn-on threshold of 4.5V and is , . 7 XFRA Transformer connection for the gate driver of the bidirectional forward MOSFET pair , drive transformer to this pin. 8 PGND Ground return for gate drive currents. 9 PVC C


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PDF SC4901 SC4901 str 5 q 0765 POWER SUPPLY CIRCUIT zener diode ST 4148 zener T 4148 STR 4148 TRANSISTOR SE 135 magnetic amplifier saturable core diode LN 4148 on ic 4148 details ZENER 4148
2005 - str 5 q 0765 POWER SUPPLY CIRCUIT

Abstract: zener diode ST 4148 on ic 4148 details str 5 q 0765 ZENER 4148 STR 4148 TSSOP-16 schematic diagram 48v dc convertor zener T 4148 SC4901ITSTRT
Text: all-MOSFET topology that allows synchronous rectification and post regulation of transformer isolated , sharing and hot swap features. All devices are synchronised to the transformer winding. The current , pulse transformer . SC4901 has an undervoltage lockout with typical turn-on threshold of 4.5V and is , . 7 XFRA Transformer connection for the gate driver of the bidirectional forward MOSFET pair , drive transformer to this pin. 8 PGND Ground return for gate drive currents. 9 PVC C


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PDF SC4901 SC4901 TSSOP-16 str 5 q 0765 POWER SUPPLY CIRCUIT zener diode ST 4148 on ic 4148 details str 5 q 0765 ZENER 4148 STR 4148 TSSOP-16 schematic diagram 48v dc convertor zener T 4148 SC4901ITSTRT
Not Available

Abstract: No abstract text available
Text: □ EQLOUT TEST2 LSE FP4 TTIP DGND DVCC TRING AVCC FP1 &ESET TCLK TPOS TNEG FP4 , when LSE is high. If LSE is tied low, the LS output represents LOS only. 13 MCLK1 I M , Driver Ground Transmit driver ground. 26 LSE I Line Status Enable 27 TEST2 I , serial port. This pin must transition from high to low to read LS serial data. LSE is sampled on the , Serial Port Timing (Figure 4) LS delay from RCLK falling edge LSE setup to RCLK rising edge LSE hold


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PDF LXT400 LXT400is LXT400 LXT400,
LSE B3 transformer

Abstract: LSE B3 LSE B4 transformer LSE B6 transformer LSE B6 LSE -B3 shbb AMI coder LSE B4 shbt
Text: impedance state when LSE is high. If LSE is tied low, the LS output represents LOS only. 13 14 MCLK1 MCLK2 I , enable for the LS serial port. Thispinmusttransitionfromhigh Enable to low to read LS serial data. LSE , ns LS Serial Port Timing (Figure 4) LS delay from RCLK falling edge - - 200 ns 2 LSE setup to RCLK rising edge *lsu 200 - - ns LSE hold time from RCLK failing edge *lsh 0 - - ns LSE low to low Z state «lz - - 100 ns LSE high to high Z state - - 100 ns MCLK and Reset Timing (Figure 5


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PDF LXT400 SW56/DDS 56/DDS HC-49/U LSE B3 transformer LSE B3 LSE B4 transformer LSE B6 transformer LSE B6 LSE -B3 shbb AMI coder LSE B4 shbt
1999 - Not Available

Abstract: No abstract text available
Text: Drivers Receiver can either be transformer or capacitively-coupled to the line Detects and Clears LOS , (near-end) terminal equipment via CMOS level signals. The receiver input can be transformer or , transformer . The transmitter is coupled to the line using a 1:2 step-up transformer . This same configuration , transmit a bipolar line signal, via a 1:2 step-up transformer . Transmitter Power Supply Pin: 3.3V + 5 , signal, via a 1:2 step-up transformer . Transmitter Ground Pin 7 RxNEG O 8 RxLOS O 9


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PDF XRT59L91 048Mbps XRT59L91ID 16-lead XRT5997IV 100-pin XRT59L91ID-F SOIC16 01-Aug-09
1999 - PIN IC 7308

Abstract: Transpower Technologies 6 pin pulse transformer tg26-1205 transformer specification single line diagram PE-65835 XRT59L91 XRT59L91ID
Text: transformer or capacitively-coupled to the line l Detects and Clears LOS (Loss of Signal) per ITU-T G , ) terminal equipment via CMOS level signals. The receiver input can be transformer or capacitivelycoupled , transformer . The transmitter is coupled to the line using a 1:2 step-up transformer . This same configuration , a bipolar line signal, via a 1:2 step-up transformer . 14 TVDD - Transmitter Power Supply , , along with TTIP, to transmit a bipolar line signal, via a 1:2 step-up transformer . 16 TVSS -


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PDF XRT59L91 048Mbps PIN IC 7308 Transpower Technologies 6 pin pulse transformer tg26-1205 transformer specification single line diagram PE-65835 XRT59L91 XRT59L91ID
1999 - tip37

Abstract: PE65835 PE-65835 TG26-1205 XRT59L91 XRT59L91ID
Text: transformer or capacitively-coupled to the line l Detects and Clears LOS (Loss of Signal) per ITU-T G , equipment via CMOS level signals. The receiver input can be transformer or capacitivelycoupled to the line. The receiver input is transformercoupled to the line, using the 2:1 step-down transformer . The transmitter is coupled to the line using a 1:2 step-up transformer . This same configuration is applicable , a 1:2 step-up transformer . 14 TVDD - Transmitter Power Supply Pin: 3.3V + 5% 15


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PDF XRT59L91 048Mbps tip37 PE65835 PE-65835 TG26-1205 XRT59L91 XRT59L91ID
2011 - CR1220 holder

Abstract: STM32F2 FTSH-110-01-L-DV RM0033 STM32F207IGH6 STM32F20xxx STM3220G-EVAL STM32F20xxx reference manual STM32F217 WLCSP66
Text: crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 13 LSE OSC clock . . . . . . , 2.3 3 External source ( LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External crystal/ceramic resonator ( LSE crystal) . . . . . . . . . . . . . . . . . . 14 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LSE , . . . . . . . . . 14 LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . .


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PDF AN3320 STM32F20xxx/21xxx CR1220 holder STM32F2 FTSH-110-01-L-DV RM0033 STM32F207IGH6 STM32F20xxx STM3220G-EVAL STM32F20xxx reference manual STM32F217 WLCSP66
12v to 220v step-up transformer winding awg

Abstract: CD4013B IC PIN DETAILS HEXFETs FETs B66335
Text: is easier in the case of a resonant converter as the transformer only sees a sine wave at the funda , capaci tor via a transformer which provides isolation and a step-up or step-down capability. The , the transformer secondary voltage. The parallel reson ant converter should feed a current load, as , c o n d a r y , respectively. Po = 100A T1 - DRIVER TRANSFORMER CORE - MAGNETICS, INC. 41605 TC - , other secon dary losses. The turns ratio of the transformer is chosen to be 32. This gives R equal to


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PDF 500W100 AN-965A 12v to 220v step-up transformer winding awg CD4013B IC PIN DETAILS HEXFETs FETs B66335
Not Available

Abstract: No abstract text available
Text: INDUCTIVE LOAD (motor, transformer .) HIGH FREQUENCY OR HIGH (di/dt)c LEVEL CIRCUITS V rms DESC , -7 7 . ELECTRICAL CHARACTERISTICS Symbol Ig t Test Conditions T| = 25 °C Pu lse , l-ll-lll P u lse Duration > V gd Ih * II = = r l = 3 .3 k n l-ll-lll l-lil II 0.2 50 50


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PDF t1237 EB81734)
LSE POWER TRANSFORMER

Abstract: 3.579545 50hz generator 3.579545 50hz squarewave telephone ring generator
Text: primary side switches used to implement a push-pull resonant converter topology and transformer coupled , , DRV2, DRVS) P u lse d . 1,5A Operating Junction T e m p e ra tu re , the sampling switch(es). The pulse width of this output is 280ns. Typi cally, a pulse transformer is , generates the high frequency sinu soidal waveform across the transformer winding. The op eration of this , . Transformer turns ratio is deter mined by the required output voltage requirements. On the secondary side, the


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PDF UCC2752 UCC3752 UCC3752 LSE POWER TRANSFORMER 3.579545 50hz generator 3.579545 50hz squarewave telephone ring generator
1997 - TD300IN

Abstract: AN461 L6380 TD300
Text: TD300 15V TRIPLE IGBT/MOS DRIVER . . . . . . . . . . . . . THREE POWER IGBT/MOS OR PULSE TRANSFORMER DRIVERS CURRENT SENSE COMPARATOR WITH 1ms INHIBITION TIME FUNCTION , transformer . So it is perfectly suited to interface control IC with Power Switches in low side or half-bridge , drive. Positive and negative pulses are applied to the pulse transformer to charge and discharge the , 23Z284S MD ON Vz = 1 5 V P u lse co ntrolle d inp uts OFF 3 P h as e s moto r Leve l co n


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PDF TD300 200mA DIP14 TD300I TD300IN AN461 L6380 TD300
KA241V

Abstract: No abstract text available
Text: fa lse trig g e rin g an d rotary dial C H IR P S ' E x te n s io n to n e rin g e r m o d u le s , loudspeaker load is coupled through a 1300ft to 8ft transformer . The output coupling capacitor Cs is required with transformer coupled loads. W hen driving a piezo-ceram ic transducer type load, the coupling C 5 and transformer (1300ft: 80) are not required. However, a current limiting resistor is required. The


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PDF KA2410/1 8-DIP-300 KA2410/KA2411 A2410 KA2410) KA2411) KA2410/Í KA2410 KA241V
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