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LOGIC OF 74LS138 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
pin diagram of ic 74ls138

Abstract: 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function 74LS138 LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8
Text: Signetics 74LS138 , S138 Decoders/Demultiplexers 1- Of -8 Decoder/Demultiplexer Product Specification Logic Products FEATURES · Demultiplexing capability · Multiple input enable for easy expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138 , Decoders/Demultiplexers 74LS138 , S138 LOGIC DIAGRAM *2 A1 *© *1 *2 63 LD01M0S ( ) - Pin number , 5-231 Signetics Logic Products Product Specification Decoders/Demultiplexers 74LS138 , S138


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PDF 74LS138, 74LS138 74S138 N74S13BN, N74LS138N N74LS138D, N74S138D 1N916, 1N3064, 500ns pin diagram of ic 74ls138 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8
CI 74LS138

Abstract: 74LS138 pin configuration TTL 74ls138 74ls138 function 74 LS 138 DECODER intel 3205 74ls138 74l5138 of 74LS138 3 to 8 decoder 74ls138 configuration
Text: HIGH or active LOW state. 74LS138 , S138 Decoders/Demultiplexers 1- Of -8 Decoder/Demultiplexer Product , Signetics Logic Products FEATURES • Demultiplexing capability • Multiple input enable , HIGH. This multiple enable function allows easy parallel expansion of the device to a 1 - of -32 (5 lines , output demultiplexer by using one of the active LOW Enable inputs as the Data input and the remaining , LOGIC SYMBOL *oU m vcc *i E ü]ö0 *2 Œ 230, ïiŒ 13] ô2 ï2 (t «JSa e3[I ID 54 ôvq


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PDF -of-32 1N916, 1N3064, 500ns CI 74LS138 74LS138 pin configuration TTL 74ls138 74ls138 function 74 LS 138 DECODER intel 3205 74ls138 74l5138 of 74LS138 3 to 8 decoder 74ls138 configuration
LOGIC OF 74LS138

Abstract: pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder TTL 74ls138 74ls138 function 74LS138 3 to 8 decoder Pin
Text: Signetics 74LS138 , S138 Decoders/Demultiplexers 1- Of -8 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Demultiplexing capability • Multiple input enable for easy , Decoders/Demultiplexers 74LS138 , S138 LOGIC DIAGRAM a2 a, aq e, e2 e3 LD01Í ( ) = Pin number Vcc - P of the device to a 1- of -32 (5 lines to 32 , demultiplexer by using one of the active LOW Enable inputs as the Data input and the remaining Enable inputs as


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PDF 74LS138, 1-of-32 1N916, 1N3064, 500ns LOGIC OF 74LS138 pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder TTL 74ls138 74ls138 function 74LS138 3 to 8 decoder Pin
LOGIC OF 74LS138

Abstract: 74LS138 3 to 8 decoder notes 74LS138 pin configuration 74LS138 pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration
Text: Signetics 74LS138 , S138 Decoders/Demultiplexers 1- Of -8 Decoder/Demultiplexer Product Specification Logic Products FEATURES · Demultiplexing capability · Multiple input enable for easy expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138 , Decoders/Demultiplexers 74LS138 , S138 LOGIC DIAGRAM A2 A0 Ei E2 E3 L C O IS fe O S ( } = Pin , and E3 is HIGH. This multiple enable function al lows easy parallel expansion of the de vice to a 1- of


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PDF 74LS138, 74LS138 74S138 N74S138N, N74LS138N N74LS138D, N74S138D 1N916, 1N3064, 500ns LOGIC OF 74LS138 74LS138 3 to 8 decoder notes 74LS138 pin configuration pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration
FUNCTIONAL APPLICATION OF 74LS138

Abstract: 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes 74LS138 pin diagram 74ls138 function 74LS138 pin for 74LS138 LOGIC DESCRIPTION OF 74LS138 74LS138 application note
Text: input function is in the disable state, all eight Y outputs are HIGH regardless of the A, B and C select inputs. The Am54LS/ 74LS138 is a standard performance version of the Am25LS138. See appropriate , Am25LS138 • Am54LS/ 74LS138 3-Line To 8-Line Decoder/Demultiplexer DISTINCTIVE , — 440|UA source current • 100% product assurance screening to MIL-STD-883 requirements LOGIC , that are decoded to one of eight Y outputs. One active-HIGH and two active-LOW enables can be used for


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PDF Am25LS138 Am54LS/74LS138 Am25LS MIL-STD-883 LS/54 LS/74LS138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes 74LS138 pin diagram 74ls138 function 74LS138 pin for 74LS138 LOGIC DESCRIPTION OF 74LS138 74LS138 application note
74ls138 truth table

Abstract: 74LS138 74 LS 138 DECODER connection for 74LS138 74ls138 demultiplexer demultiplexer 3 to 8 truth table 74LS138 3 to 8 decoder Pin LS138 LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
Text: (g) MOTOROLA 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/ 74LS138 is a high speed 1- of , AND LS TTL DATA SN54/ 74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1- of -8 Decoder , decoding. The multiple input enables allow parallel ex pansion to a 1- of -24 decoder using just three LS138 devices or to a 1- of -32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , Dissipation of 32 mW Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination


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PDF SN54/74LS138 1-of-24 LS138 1-of-32 LS138s SN54/74LS138 74ls138 truth table 74LS138 74 LS 138 DECODER connection for 74LS138 74ls138 demultiplexer demultiplexer 3 to 8 truth table 74LS138 3 to 8 decoder Pin LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
1996 - 74LS138

Abstract: 74LS138 3 to 8 decoder Pin 74LS138 pin diagram ls138 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table
Text: SN54/ 74LS138 1- OF -8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1- of , decoding. The multiple input enables allow parallel expansion to a 1- of -24 decoder using just three LS138 devices or to a 1- of -32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , . · · · · · 1- OF -8 DECODER / DEMULTIPLEXER LOW POWER SCHOTTKY Demultiplexing Capability Multiple Input Enable for Easy Expansion Typical Power Dissipation of 32 mW Active Low Mutually Exclusive


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PDF SN54/74LS138 74LS138 1-of-24 LS138 1-of-32 LS138s 74LS138 3 to 8 decoder Pin 74LS138 pin diagram 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA HCTL1100
Text: such chip is the 74LS138 3-to-8 decoder which is capable of handling four HCTL-1100s. Read , subroutine overhead. The HCTL-1100 bus interface circuit is capable of supporting four HCTL-1100s with no additional logic . If an I/O port based design requires more than one HCTL-1100, the interface The choice of which interface is most appropriate for your application should be based on whether or not your , glue logic . Bus Interface The I/O routines are slightly more complicated for the I/O interface than


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL1100 HCTL1100. HCTL-1100s 74LS00 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA
2007 - 3 to 8 line decoder using 8051

Abstract: 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET HCTL-1100 74LS138 HCTL-1100 M-015 HCTL-1100s
Text: circuit is capable of supporting four HCTL-1100s with no additional logic . If an I/ O port based design , chip could be used. One such chip is the 74LS138 3-to-8 decoder which is capable of handling four , -1100 and the second approach uses the 8051's I/O ports to communicate with the HCTL-1100. The choice of , port interface. The I/O interface requires no additional glue logic . The I/O routines are slightly , . These lines would control OE (Output Enable) and CS (Chip Select) for each of the individual HCTL


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL-1100. WR1100: CS1100 3 to 8 line decoder using 8051 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET 74LS138 HCTL-1100 M-015 HCTL-1100s
block diagram of 74LS138 3 to 8 decoder

Abstract: block diagram of 74LS138 1 line to 16 line TTL 74ls138 74LS138 74LS138 3 to 8 74LS138 application note 74LS138 pin configuration 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74ls138 3-8
Text: GD54/ 74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature • Designed Specifically for High , used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit the delay times of this decoder and the enable time of the memory are usually less than the typical access times of the memory. This means that the effective system delay introduced by , Diagram and Logic Absolute Maximum Ratings • Supply voltage, Vcc


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PDF GD54/74LS138 block diagram of 74LS138 3 to 8 decoder block diagram of 74LS138 1 line to 16 line TTL 74ls138 74LS138 74LS138 3 to 8 74LS138 application note 74LS138 pin configuration 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74ls138 3-8
and gate 74LS138

Abstract: SP74HCT138N TTL 74ls138 LOGIC OF 74LS138 74LS138 pin configuration pin for 74LS138 74LS138 SP74HCT138J 74ls138 function 74ls138 PIN DIAGRAM
Text: with 74LS138 ■SPI CMOS technology ■Full TTL interface capability ■High noise immunity â , process: a silicon gate (with oxide isolation) complementary MOS technology. This provides the features of , pin compatibility with the 74LS138 . Speeds are comparable to the low power Schottky device family , €”1 ^ — 770 [19 5581 MAX T " 7WWÍ O LOGIC DIAGRAM FUNCTION TABLE □ ATA OUTPUTS INPUTS , an appropriate logic voltage level (either Vcc or GND). Symbol Parameter Conditions TA = 25Â


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PDF SP74HCT138 74LS138 SP74HCT138 74LS138. 20/iA and gate 74LS138 SP74HCT138N TTL 74ls138 LOGIC OF 74LS138 74LS138 pin configuration pin for 74LS138 74LS138 SP74HCT138J 74ls138 function 74ls138 PIN DIAGRAM
74LS138 3 to 8 decoder notes

Abstract: 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note LS138 Motorola 74ls138
Text: SN54/ 74LS138 1- OF -8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1- of , / 74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1- of -8 Decoder/Demultiplexer fabricated with , decoding. The multiple input enables allow parallel expansion to a 1- of -24 decoder using just three LS138 devices or to a 1- of -32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , . · · · · · 1- OF -8 DECODER/ DEMULTIPLEXER LOW POWER SCHOTTKY Demultiplexing Capability


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PDF SN54/74LS138 74LS138 1-of-24 LS138 1-of-32 LS138s 74LS138 3 to 8 decoder notes 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note LS138 Motorola
l381

Abstract: and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138
Text: 74LS138 ■SPI CMOS technology ■Full TTL interface capability ■High noise immunity ■Low , silicon gate {with oxide isolation) complementary MOS technology. This provides the features of , pin compatibility with the 74LS138 . Speeds are comparable to the low power Schottky device family , €”\ LOGIC DIAGRAM FUNCTION TABLE DATA OUTPUTS INPUTS OUTPUTS ENABLE SELECT G1 , appropriate logic voltage level (either Vcc or GND). Parameter Conditions SP74SC138 Unit Min. Typ. Max


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PDF SP74SC138 74LS138 SP74SC138 74LS138. 400//A l381 and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138
2014 - JM38510/01405BEA

Abstract: sn74ls138n LS138 texas M38510
Text: -1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 , -1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS138 SN74LS138NSRG4 ACTIVE SO NS 16


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PDF 25-Sep-2013 6005012A SNJ54LS 138FK 7600501EA SNJ54LS138J JM38510/01405BEA sn74ls138n LS138 texas M38510
2013 - JM38510/01405BEA

Abstract: M38510
Text: SN74LS138N SN74LS138N 74LS138 74LS138 74LS138 74LS138 74LS138 74LS138 S138A S138A S138A SN74S138AN , discontinued the production of the device. Addendum-Page 5 PACKAGE OPTION ADDENDUM www.ti.com 25 , Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do , is indented then it is a continuation of the previous line and the two combined represent the entire , page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge


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PDF 25-Sep-2013 6005012A SNJ54LS 138FK 7600501EA SNJ54LS138J 7600501FA JM38510/01405BEA M38510
pin diagram of ic 74ls138

Abstract: connection diagram of ic 74ls138 pin for 74LS138 74ls138 function SN54LS13B sn54ls138 ic 74ls138 74ls138 74S138A 74LS138 function table
Text: Performance SN 5 4 LS 1 38 , S N 54S 138 . . . J OR W PACKAG E SN 74LS138 , SN 74S138A . D OR N P A C K A G , to minimize the effects of system decoding. When employed with high speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. Th is means that the effective system delay introduced by the , of eight lines dependent on the conditions at the three binary select inputs and the three enable


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PDF SN54LS13B, SN54S138, SN74LS138, SN74S13BA 74LS138, 74S138A SN74S138A 54S138 74S138A pin diagram of ic 74ls138 connection diagram of ic 74ls138 pin for 74LS138 74ls138 function SN54LS13B sn54ls138 ic 74ls138 74ls138 74LS138 function table
64LS138

Abstract: No abstract text available
Text: connection logic symbols^ All of these decoder/demultiplexers feature fully buffered inputs, each of , docoders can be used to minimize the effects of system decoding. When employed with high­ speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay , decode one of eight lines dependent on the conditions at the three binary select inputs and the three


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PDF 54S138, 64LS138
transistor d133

Abstract: ttl 7442 Decoder BCD 7 seg transistor 6B 7-seg ANODE COMMON 74LS247 74155 pin diagram of 74LS247 ttl 74191 75491
Text: ns (Typ) Power Dissipation mW (Typ) Fan-Out (UL)* Logic /Connection Diagram Package(s) 1 1 - of , D135 4L,6B,9B 5 1 - of -8 54LS/74LS42 3 1 8 — 17 17 35 5.0 D135 4L,6B,9B 6 1- of -8 54LS/ 74LS138 3 3 8 , FAIRCHILD LOGIC /CONNECTION DIAGRAMS DIGITAL-TTL D130 54/74190, 74LS190 54/74191, 74LS191 0131 , 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/ 74LS138 1 2 3 4 5C ■Iii- e , 0 ■> Q 01 o _i 'in "3T Ol n je o of -10 Cold Cathode TTL Yes No No 7.0 55 L Gas


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PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 transistor d133 ttl 7442 Decoder BCD 7 seg transistor 6B 7-seg ANODE COMMON 74LS247 74155 pin diagram of 74LS247 ttl 74191 75491
74LS138 pin diagram

Abstract: ASTAS MD74HCT138RE 74HCT138 74ls138 MD54HCT138 Hll logic 74HCT138 DIP
Text: €¢ Fully TTL compatible ijiputs and outputs • Pin compatible with 54/ 74LS138 types Description This , MD54/74HCT138 will decode 3 binary inputs (Aq, A1(A2> to select one of eight mutually exclusive outputs , external gates in an expanded system. A 1 of 32 decoder requires only four of these devices and one , = logic "1 ", L » logic "0~'x » don't care 3-1 This Material Copyrighted By Its Respective


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PDF 54/74LS138 MD54/74HCT138 MD54HÃ T138RC, MD74HCT138RE, 74LS138 pin diagram ASTAS MD74HCT138RE 74HCT138 74ls138 MD54HCT138 Hll logic 74HCT138 DIP
1983 - 74LS138 decoder

Abstract: pin for 74LS138
Text: a percent of FSR output change per percent of change in either the positive, negative, or logic , when the control signals are logic 0 will enter the latch. When any one of the control signals returns , Rotates the Line All Bits Logic 0 Range of Offset Adj. All Bits Logic 1 Digital Input Offset , Others Off All Bits Logic 1 Range of Offset Adjust Offset Adj. Translates the Line ±0.4% ­ Full , . Left-Justified Data Bus Interface. ® DAC811 8 DAC811 8-BIT INTERFACE The control logic of DAC811


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PDF DAC811 12-BIT 74LS138 decoder pin for 74LS138
ic 74 LS 138 DECODER

Abstract: IC 74ls138 74LS138 3 to 8 decoder notes 74LS138 1 to 8 decoder notes ic 74 138 DECODER
Text: / 74LS138 F U N C T IO N A L D E S C R IP T IO N - The LS138 is a high speed 1- of -8 D eco d e r/D em u , /7 4 L S 1 38 is a high speed 1 - of -8 D ecoder/D em ultiplexer. This device is ideally suited for , N A B LE FOR E A S Y E X P A N S IO N T Y P IC A L POW ER D IS S IP A T IO N OF 3 2 m W A C T IV E , C O N N E C T IO N D IA G R A M D IP (TOP VIEW) LOGIC D IA G R A M *0 * "1 v'c c ' 3 , 6 ÖQ 3 , 5 , th e device to a 1- of -32 <5 lines to 3 2 lines) decoder w ith ju s t fo u r L S I 38s and one


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PDF LS138s ic 74 LS 138 DECODER IC 74ls138 74LS138 3 to 8 decoder notes 74LS138 1 to 8 decoder notes ic 74 138 DECODER
1983 - 74LS138 decoder

Abstract: 74LS138 pin diagram block diagram of 74LS138 3 to 8 decoder DAC811JP DAC811J DAC811BH DAC811AH DAC811A DAC811 ic 74ls138 pdf datasheet
Text: logic 1, the data is latched in the D/A latch and held until LDAC and WR go to logic 0. Percent of , level-triggered. Data present when the control signals are logic 0 will enter the latch. When any one of the , of offset and gain adjustments to unipolar and bipolar D/A converter output. INTERFACE LOGIC , 1LSB Range of Offset Adj. LOGIC INPUT COMPATIBILITY The DAC811 digital inputs are TTL, LSTTL , Bits Logic 1 Range of Offset Adjust VDD 28 V DD 2 ­ Full Scale Offset Adj


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PDF DAC811 12-BIT DAC811 74LS138 decoder 74LS138 pin diagram block diagram of 74LS138 3 to 8 decoder DAC811JP DAC811J DAC811BH DAC811AH DAC811A ic 74ls138 pdf datasheet
of 74LS138 3 to 8 decoder

Abstract: MD74HCT138
Text: 1 of a Ocial D *m >d«/P!«n^i|p^ar wmmwttw CONNECTION DIAGRAM OH> (TOP VIEW) Features · High , / 74LS138 types , c : T3 3'oa Ë2 c 5 E, C 6 o7 c 7 GNO E 12 = I o3 11 3 o 4 U) 9 1o5 3 o6 , address decoding systems. The MD54/74HCT138 will decode 3 binary inputs (Ag, A i# A 2 ) to select one of , active HIGH (E3 ), reduce the need for exterrtal gâtés in an expanded system. A 1 of 32 decoder requires only four of these devices and one external inverter. The enable inputs can be used as the data input


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PDF 54/74LS138 MD54/74HCT138 MD54H T138RC, MD74HCT138RE, of 74LS138 3 to 8 decoder MD74HCT138
ic 74ls138

Abstract: 74LS138M 74LS139C N74LS139
Text: , Y7 'JL T QND positive logic : see function table description These Schottky-clamped T T L , to minimize the effects of system decoding. When employed with high-speed memories utilizing a fastenable circuit the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the , used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully


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PDF SN54LS138. SN54LS139. SM54S13I, SNS4S139, SN74LS138. SM74LS139, SN74SB8. SN74S139 LS138 LS139 ic 74ls138 74LS138M 74LS139C N74LS139
1999 - 74LS138 pins

Abstract: 02830
Text: comparable to low power Schottky TTL logic . The MM74HCT138 have 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally HIGH outputs will go LOW. Two , equivalent to the 74LS138 . All inputs are protected from damage due to static discharge by diodes to VCC and , quiescent current: 80 µA maximum (74HCT Series) s Low input current: 1 µA maximum s Fanout of 10 LS-TTL , Logic Diagram www.fairchildsemi.com 2 MM74HCT138 Absolute Maximum Ratings(Note 2) (Note 3


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PDF MM74HCT138 MM74HCT138M MM74HCT138SJX MM74HCT138SJ MM74HCT138MTC MM74HCT138MTCX MM74HCT138N 74LS138 pins 02830
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