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Part Manufacturer Description Datasheet Download Buy Part
J2007001L006Z GE Critical Power IEC-320 SHELF / CONTROLLER
J2007001L006 GE Critical Power IEC-320 SHELF / CONTROLLER
TD1000V3025RMDC GE Critical Power SPD DIN RAIL 1000 PV 25KA IEC
ADC10D1500CIUT/NOPB Texas Instruments 10-Bit, Dual 1.5-GSPS or Single 3.0-GSPS Analog-to-Digital Converter (ADC) 292-BGA -40 to 85
ADC12D1600CIUT Texas Instruments 12-Bit, Dual 1.6-GSPS or Single 3.2-GSPS Analog-to-Digital Converter (ADC) 292-BGA -40 to 85
ADC12D1600CIUT/NOPB Texas Instruments 12-Bit, Dual 1.6-GSPS or Single 3.2-GSPS Analog-to-Digital Converter (ADC) 292-BGA -40 to 85

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msm 8255

Abstract: 4953 ic 8 pin
Text: U lk A # A * Corporation* C irs A v SIGNAL PROCESSING EXCELLENCE SP490E/SP491E Enhanced , 3015.7 b) IEC 1000-4-2 Air-Discharge c) IEC 1000-4-2 Direct Contact The Human Body Model has been the , exposed to the outside environment and human presence. The premise with IEC 1000-4-2 is that the system is , current when the ESD source is applied to the connector pins. The test circuit for IEC 1000-4-2 is shown on Figure 10. There are two methods within IEC 1000-4-2, the Air Discharge method and the Contact


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PDF SP490E/SP491E RS-485 SP491E) RS-422 LTC490 SN75179 SP490E) LTC491 SN75180 msm 8255 4953 ic 8 pin
Not Available

Abstract: No abstract text available
Text: U lk A # A * Corporation* C irs A v SIGNAL P R O C E S S IN G EXCELLENCE SP490E/SP491E , 3015.7 b) IEC 1000-4-2 Air-Discharge c) IEC 1000-4-2 Direct Contact The Human Body Model has been the , exposed to the outside environment and human presence. The premise with IEC 1000-4-2 is that the system is , current when the ESD source is applied to the connector pins. The test circuit for IEC 1000-4-2 is shown on Figure 10. There are two methods within IEC 1000-4-2, the Air Discharge method and the Contact


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PDF SP490E/SP491E RS-485 SP491) RS-422 LTC490 SN75179 SP490) LTC491 SN75180
msm 8255

Abstract: No abstract text available
Text: U lk A # A * Corporation* C irs A v SIGNAL PROCESSIN G EXCELLENCE SP490E/SP491E Enhanced , testing ap plied: a) MIL-STD-883, Method 3015.7 b) IEC 1000-4-2 Air-Discharge c) IEC 1000-4-2 Direct , . The premise with IEC 1000-4-2 is that the system is required to withstand an amount of static , to the connector pins. The test circuit for IEC 1000-4-2 is shown on Figure 10. There are two methods within IEC 1000-4-2, the Air Discharge method and the Contact Discharge method. With the Air Discharge


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PDF SP490E/SP491E RS-485 SP491) RS-422 LTC490 SN75179 SP490) LTC491 SN75180 msm 8255
Not Available

Abstract: No abstract text available
Text: ) IEC1000-4-2 Air-Discharge c) IEC 1000-4-2 Direct Contact equipment that are accessible to personnel , applied to the connector pins. The test circuit for IEC 1000-4-2 is shown on Figure 10. There are two methods within IEC 1000-4-2, the Air Discharge method and the Contact Discharge method. The Human , outside environment and human presence. The premise with IEC 1000-4-2 is that the system is required to , lower Rs value in the IEC 1000-4-2 model are more stringent than the Human Body Model. The larger


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PDF SP490E/SP491E RS-485 SP491E) RS-422 LTC490 SN75179 SP490E) LTC491 SN75180
Not Available

Abstract: No abstract text available
Text: . MAX .UNIT Acquisition Tim e (tA) (2 SC LK Periods) 400 Conversion Tim e (tC) (31 SCLK Periods) 7.75 SC LK Low Pulse W idth (tSKL) 110 125 ns SC LK High Pulse Width (tSKH) 110 125 ns SC LK Period (tSKT) 250 COND. US 500 ns US ns Buss Access Tim , Falling (tCSSU) 0 90 CSN Low Before SCLK Rises (tCS) ns ns SC LK Falling to Data Valid (tSD) 50 ns CSN Falling to status Rising (tDCS) 69 ns SC LK 33 Falling to Status Rising Free


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PDF SP8530 10jaW) SP8530 12-Bit P8530D
Not Available

Abstract: No abstract text available
Text: methods of ESD testing ap­ plied: a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC , circuit for IEC 1000-4-2 is shown on Figure 10. There are two methods within IEC 1000-4-2, the Air , presence. The premise with IEC 1000-4-2 is that the system is required to withstand an amount of static , Inputs HUMAN BODY MODEL ±15kV ±15kV The higher Cs value and lower Rs value in the IEC , -m a il: m lk e b @ s ip e x .c o .u k N ip p on S ip e x C o rp o ra tio n Y a h a g i No. 2 B


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PDF SP490E/SP491E RS-485 SP491) RS-422 LTC490 SN75179 SP490) LTC491 SN75180
Not Available

Abstract: No abstract text available
Text: LK Periods) 3.75 S C LK Low Pulse W idth (tSKL) 110 125 ns S C LK High Pulse Width (tSKH) 110 125 ns S C LK Period (tSKT) 250 COND. US 500 ns US ns Bus , CSN Falling (tCSSU) 0 90 CSN Low Before SC LK Rises (tCS) ns ns S C LK Falling to Data Valid (tSD) 50 ns CSN Falling to status Rising (tDCS) 69 ns S C LK 17 Falling to Status Rising Free Run (tDSS) 70 ns S C LK 16 Falling to Status Falling ( tDSE) 45 ns


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PDF SP8531 12-Bit 10jaW) TheSP8531 SP8531 16-pin P8531D
7402 ic description

Abstract: No abstract text available
Text: ) SC LK High Pulse Width (tSKH) SC LK Period (tSKT) Min. Setup Tim e DIN to SC LK Rising (tDlSU) Min Hold Tim e from SC LK Rising to DIN (tDIH). Buss Relinquish Tim e (tBR) Setup Tim e -SCLK Falling to CSN Falling (tCSSU) CSN Low Before SCLK Rises (tCS) SC LK Falling to Data Valid (tSD) CSN Falling to status Rising (tDCS) SC LK 17Falling to Status Rising Free Run (tDSS) SCLK16 Falling to Status Falling


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PDF SP8544 12-Bit 18-pin 7402 ic description
Not Available

Abstract: No abstract text available
Text: (positive logic) 'A S 8 2 5 F U N C T IO N T A B L E OUTPUT IN P U T S C LR C LK EN C LK D , IEC Publication 6 1 7 -1 2 . Pin num bers are for DW , JT, and N T packages. 2-644 2922 i , (18) 8Q *T h is sym bol is in accordance with A N SI/IEEE Std 9 1 - 1 9 8 4 and IEC Publication , low 9 8 E l R inactive 8 8 Oata 7 6 C LK E N high or low 7 V 6 th Hold time, CLKEfJ or data after C LK t Ta Operating free-air temperature ns ns 0


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PDF SN54AS825, SN54AS826 SN74AS825, SN74AS826 D2826, 1984-REVISED SN74AS825 SN54AS825
Not Available

Abstract: No abstract text available
Text: E X C LK T P O S /T N E G T C L K All O nes TCLK AJI O nes TCLK TC L K T P O S /T N E G , , the clock recov­ ery PLL1 locks to EXC LK or the crystal-based clock source for training. After , ci 331 IBRK Line Interface Unit (LIU) RNEG are clocked out on the falling edge of R C LK , of TXOUTP/N is RXINP/N. RPOS and RNEG are clocked out on the falling edge of R C LK The source of , of R C LK The source of RPOS/RNEG is RXINP/N. SLAVE TIMING MODES Normal Operation without EXCLK


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PDF R8069B R8069B R8070 RT9170 PCM30
Not Available

Abstract: No abstract text available
Text: input. TPO S and T N EG are sam pled on the falling edge of TCLK . If T C LK is grounded, the output , outputs are stable and valid on the rising edge o f RCLK. L X T 300Z only: In the H ost Mode. C LK E , the L X T 300Z H ost Mode. If C LK E is High. SD O is valid on the rising edge o f SCLK. If C LK E is , 3 0 IZ . Setting L L O O P High enables the Local L oopback Mode. Setting C LK E High causes RPO S , . W hen C LK E is Low , RPOS and RNEG are valid on the rising edge o f RCLK, and SDO is valid on the


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PDF LXT300Z/LXT301Z T300Z T300/301 T301Z DS-T300Z-0696-5K
Not Available

Abstract: No abstract text available
Text: (tTP=tA+tC) 4.25 Acquisition Tim e (tA) (2 SCLK Periods) 400 Conversion Tim e (tC) (15 SC LK , ) 110 125 ns SCLK Period (tSKT) 250 ns Setup Tim e DIN to SC LK Rising (tDlSU) 0 ns Hold Tim e from SC LK Rising to DIN (tDIH). 5 ns Buss Relinquish Tim e (tBR) TYP , (tCSSU) 10 ns CSN Low Before SC LK Rises (tCS) 90 ns SCLK Falling to Data Valid (tSD , 7 F A X : 4 4 -1 4 2 0 -5 4 2 7 0 0 e -m a il: m lk e b @ s lp e x .c o .u k N ip p o n S lp e


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PDF SP8542/SP8544 12-Bit 10jaW) TheSP8542 SP8544 542/8544D
c5057

Abstract: No abstract text available
Text: TSX UCC t132Z 1C5B54FN -B3 UBB GNDA nCLKX MCLKR/ PDN BCLKX B C LK R / CLKSEL FSR , . Must be 1.536 MFIz, 1.544 MHz or 2.048 MHz. May be asynchronous with M C LK r . Shifts out the PCM data , 4/1 T SGS-THOMSON ^7# M ncBSELiscm siM nes ETC5 05 4 - ETC5054-X - ETC5 05 7 - ETC5057-X , 10 10 HA HA HA 5/18 SGS-THOMSON M D C B S E LIS C m S lN neS ETC5054 - ETC5054-X - ETC5057 , master clocks Depends on the device used and the BCLK r/C LK S E L Pin M C L K xan d M CLK r W idth of


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PDF ETC5057FN, ETC5054FN, c5057
Not Available

Abstract: No abstract text available
Text: SYMBOL Supply Voltage *C LK Clock Frequency W : Total Cycle Time 40 'hDI Hold , *"w C H LK CLK Low Time 1 1.4 us "^ V C VHS CS High Time between Data Transfers


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PDF 12-Bit 250pA SP8538 TheSP8538 BBIgr/SP9838/9410R0
M54683FP

Abstract: m54683 M54671SP M54684SP m54670 polygon mirror motor motor control IC
Text: ) O ne-S hot M u lti Tim e C onstant (1) O utput C urrent D ire ctio n S w itc h in g (1 ) M-.l u , Power S u p p ly (2) 1 ] V p Boot Strap Power S u p p ly (2) :J Pow er S u p p ly (2) O ne-S hot M u , J In ] | j 8] l l 3] i ] 4j []5j [161 [17] l]8 10k : 0.47^ - + - + Hv - + 77r lk 77T


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PDF M54670P M54671SP 54670P M54671SP F/50V M54670P M54683FP m54683 M54684SP m54670 polygon mirror motor motor control IC
controller LTA 702 N

Abstract: LXT305A
Text: LK I M aster C lock A 1.544 o r 2.048 M H z clock input used to generate internal clocks. U pon L oss o f Signal (LO S), R C L K is derived from M C LK . I f M C L K is not applied, th is pin , . Input for positive pulse to be transm itted on the tw isted-pair line. 2 T C LK I T , outputs are N on-R etum -to-Z ero (N RZ). B oth outputs are stable and valid on (he rising edge o f R C LK , valid. In the H ardw are m ode both outputs are stable and valid on the rising edge o f RC LK . T his is


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PDF LXT305A T305A LXP2181 LXT305A LXP2180A. DS2181, R8070. controller LTA 702 N
diagram LG led TV circuits

Abstract: LG t300
Text: valid on the rising edge o f RCLK. L X T 300Z only: In the H o st mode, C LK E d eterm ines the clock , ) L ocal L oopback (H /W M ode) SC LK 27 I LLOOP I CLKE 28 I C lock Edge (H ost M ode) TAOS I T ransm it All O nes (H /W M ode) 6 flVESLEVEL |lg O N E ® LXT300Z/301Z , to T C L K setup tim e T C L K to T PO S /T N E G H old tim e Sym M C LK M C LK M C LK t M C LK d , to RC LK rising setup time RCLK rising to RPOS / R N EG hold tim e DSX-1 El DSX-1 El Sym RC L K d


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PDF LXT300Z/301Z T300/301 T300Z T301Z 195-1KR diagram LG led TV circuits LG t300
ADK21

Abstract: 2920P
Text: 8 3 3 OF RST/ÈÔP C 9 10 20 I ] RUN/PRÔS 19 CC LK IS 3 VCC IN O C IN 3 C 11 VBB C IN 2 C IN 1 C 12 13 14 17 GRDD 16 15 R U N /P R O G R S T/Ë Ô P 3 X2/C LK 3x, Figure 2 , s ta lk , the fo llo w in g fo rm u la can be used: # IN 's = (TIAm ax x fo s c )^ w here T IA is th


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PDF 2920--User-Programmable/Erasable 2921--Mask-Programmable ADK21 2920P
Not Available

Abstract: No abstract text available
Text: Pin# Sym I/O1 Name Description 1 M C LK DI M aster C lock A 1.544 or 2.048 , from M C LK . If M C L K is not applied, this pin should be grounded. 2 TC LK DI T ransm , loopback, the transm itter rem ains pow ered dow n if T C LK is not supplied. S etting M O D E H igh , DO R eceive P ositive D ata 8 R C LK DO R ecovered C lock R eceived data outputs , C lock (H ost M ode) L LO O P DI C LK E DI C lock E dge (H ost M ode) TAOS


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PDF LXT305 LXT305
Not Available

Abstract: No abstract text available
Text: r 4 3 2 D C B A THIS DRAWING IS UNPUBLISHED. RELEASED FOR PUBLICATION AUG ,2004. COPYRIGHT 2004 BY TYCO ELECTRONICS CORPORATION. ALL RIGHTS RESERVED. LOO J REC-CONTACT PLUG-H.S 30,34,50 POS 40,48,60,96 POS E <ñ> 4 # <ñ> # — BSC — # 1 D B REVISIONS LTR A A1 DESCRIPTION REVISED ECR —09 —01 5031 REVISED PER EC0-09-024927 DATE 200CT09 09NOV09 DWN A.Z KK APVD S.Y AEG MATCHING EACE Lk ^ TINE 905 TI NE-PLATE CONNECTOR MOUNTING SUREACE LD O LO O +|o Gì -BSC- (UNACCUMULATE TOLERANCE) ,27Xn


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PDF EC0-09-024927 200CT09 09NOV09 31MAR2000
Not Available

Abstract: No abstract text available
Text: speed. The IEC -1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and , system itself is exposed to the outside environment and human presence. The premise with IEC 1000-4-2 , test circuit for IEC 1000-4-2 is shown on Figure 7. There are two methods within IEC 1000-4-2, the , device under test receives a duration of voltage. The higher Cs value and lower Rs value in the IEC , (Rs) and the source capacitor (Cs) are 1.5kW an lOOpF, respectively. For IEC -1000-42, the current


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PDF SP486E SP487E RS-485/RS-422 RS-485 RS-422 SN75172, SN75174, LTC486, LTC487 IEC1000-4-2
HDB3 AMI ENCODER DECODER

Abstract: cs2180b CS61577 G742
Text: TC LK TC LK RTIP & RR IN G (RCLK) Notes: 1. X = Don't care. T he identified All O nes S e lect , CLOCK & « O ·4- P R A C K ,1 0 R L O O P X T A L IN X T A L O U T A C LK I (C S) 1 L DATA J IT T E R , ) T A O S LENO L E N I L E N 2 28 j 23 124 Í2 5 ^ TG ND Í1 4 TV+ £l TC LK TPOS [T D A T A ] L IN E D R IV E R 14 TN EG 1 [T C O D E ] R C LK RPOS V [R D A T A ] 6 RNEG r - [B P V] 27 LLO O P (SC LK ) 12 LO S 21 Î 2 2Î RGND RV+ Preliminary Product Information


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PDF CS61577 CS61574 EN60950, EN41003 DS155PP1 CS61577 CS2180B CS2180B, CS2180B. HDB3 AMI ENCODER DECODER G742
Not Available

Abstract: No abstract text available
Text: ) Setup Tim e -SCLK Falling to CSN Falling (tCSSU) CSN Low Before SC LK Rises (tCS) SCLK Falling to Data


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PDF SP8531 12-BifSamping SP8531 12-Bit 16-pin SP8531DS/01 SP853FAX: SP8531DS/
2002 - 8031 microprocessor

Abstract: No abstract text available
Text: DISPLAY BE BLANK - - 1 uA FSDCLK V C C = 5V 500 - - KHz FC LK V C C = , CONTENTS OF THE 8 BI T SERI AL SHI FT REGI STER WI LL BE EVALUATED BY THE I NTERNAL CI RCUI TRY. C LK , THE BLANK DISPLAY MODE, THE RAM CAN BE LOADED WITH DATA. D I S P L AY BR I G H T NES S OP CODE D4 D3 D2 D1 D0 CH AR ACT ER BR I G H T NES S 1 1 1 X 0 0 0 0 100% BRI GHTNESS


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PDF XMMYK50/IC XDSA3171 8031 microprocessor
dd127d

Abstract: D0127D
Text: iSBA- -o - — 2S B A 2C LK A B 1C L K A B —£ > - , iS A B — [ > 9Ã


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PDF 16-BIT IDT54/74FCT16651T/AT/CT/ET 4AE5771 DD127D4 4fl2S771 MIL-STD-883, S056-1) S056-2) E56-1) 16651T dd127d D0127D
Supplyframe Tracking Pixel