The Datasheet Archive

LH5420 datasheet (7)

Part Manufacturer Description Type PDF
LH5420 Sharp 256 x 36 x 2 Bidirectional FIFO Scan PDF
LH5420P-25 Sharp SRAM FIFO Original PDF
LH5420-P-25 Sharp 256 x 36 x 2 Bidirectional FIFO Scan PDF
LH5420P-30 Sharp SRAM FIFO Original PDF
LH5420-P-30 Sharp 256 x 36 x 2 Bidirectional FIFO Scan PDF
LH5420P-35 Sharp SRAM FIFO Original PDF
LH5420-P-35 Sharp 256 x 36 x 2 Bidirectional FIFO Scan PDF

LH5420 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
D22A

Abstract:
Text: : LH5420P-25 (256 x 36 x 2 Bidirectional FIFO, 25 ns, 132-Lead, Plastic Quad Flat Package) m SHA RP , LH5420 / FEATURES · · · · · · · Fast Cycle Times: 25/30/35 ns Two 256 x 36-bit FIFO Buffers Full , Functionally Equivalent 256 X 36 X 2 Bidirectional FIFO FUNCTIONAL DESCRIPTION The LH5420 , bidirectional data buffering. FIFO #1 and FIFO #2 each are organized as 256 words by 36 bits. The LH5420 is , count and board area are reduced. The LH5420 has two 36-bit ports, Port A and Port B. Each port has its


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PDF LH5420/ 36-bit 36/18/9-bit Oct91 LH5420 132-Lead. PQFP132-P-S950) 120-Lead, PGA120-C-S1360) D22A
d358

Abstract:
Text: (PQFP132-P-S950) - 256 x 36 x 2 Bidirectional FIFO Example: LH5420P-25 (256 x 36 x 2 Bidirectional FIFO, 25 ns , would be permissible for that speed grade of LH5420. When a FIFO full condition is reached, write ,  LH5420 256 X 36 X 2 Bidirectional FIFO FEATURES • Fast Cycle Times: 25/30/35 ns • Two , €¢ Space-Saving PQFP Package • PQFP to PGA Package Conversion * FUNCTIONAL DESCRIPTION The LH5420 contains , bidirectional data buffering. FIFO#1 and FIFO #2 each are organized as 256 words by 36 bits. The LH5420 is ideal


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PDF LH5420 36-bit 36/18/9-bit 132pqfp 132-pin 001LS73 LH5420 132-Pin, d358 pitch 0.4 QFP 256p D35B LH543620 D28B D268 D24B D22B D20B
1995 - D35B 60 74

Abstract:
Text: -Technology Replacements for Sharp LH5420 and LH543601 · Functionally Upwards-Compatible from LH5420 and LH543601 · Two , initializes the LH543611/21 Control Register for LH5420 /LH543601compatible operation, but it may be , Street, Pomona, CA 91766, (909) 469-2900. BOLD = Improved or added features over SHARP's LH5420 , 5-6 7 8 9 10 11 12 13 14-15 16 17 NOTE: 1. LH5420 /LH543601 also have this , E V E N O D D 35 0 1 LH5420 /LH543601 CONTROL REGISTER (WRITE-ONLY) (FOR COMPARISON


Original
PDF LH543611/21 LH5420 LH543601 36-bit 36/18/9-bit LH5420/LH543601 D35B 60 74 D35B 60 D33A D26A D28B D31A D35B d22a D11A LH543621
u29a

Abstract:
Text: (PGA120-C-S1360) Example: LH5420P-25 (256 x 36 x 2 Bidirectional FIFO, 25 ns, 132-Lead, Plastic Quad Flat , permis sible for that speed grade of LH5420. When a FIFO full condition is reached, write operations are , LH5420 FEATURES · Fast Cycle Times: 25/30/35 ns · Two 256 x 36-bit FIFO Buffers · Full 36-bit Word , Pin-Compatible and Functionally Equivalent 256 x 36 x 2 Bidirectional FIFO FUNCTIONAL DESCRIPTION The LH5420 , bidirectional data buffering. FIFO #1 and FIFO #2 each are organized as 256 words by 36 bits. The LH5420 is


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PDF LH5420 36-bit 36/18/9-bit 132-Lead, PQFP132-P-S950) 120-Lead, PGA120-C-S1360) LH5420P-25 u29a bd248 MS76542-SSFC
Not Available

Abstract:
Text: -Lead, Pin-Grid-Array Package (PGA120-C-S1360) Example: LH5420P-25 (256 x 36 x 2 Bidirectional FIFO, 25 ns, 132 , would be permissible for that speed grade of LH5420. SHARP 5-135 LH5420 256 x 36 x 2 , LH5420 FEATURES · · · · · Fast Cycle Times: 25/30/35 ns Two 256 x 256 x 36 x 2 Bidirectional FIFO FUNCTIONAL DESCRIPTION The LH5420 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate , are organized as 256 words by 36 bits. The LH5420 is ideal either for wide unidirectional applications


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PDF LH5420 LH5420 36-bit 132-Lead, PQFP132-P-S9501 120-Lead, PGA120-C-S1360) LH5420P-25
D2SB 73

Abstract:
Text: - 132-Pin, Plastic Quad Flat Package (PQFP132-P-S950) O C Û v OC w O C IC r V Example: LH5420P-25 , grade of LH5420. When a FIFO full condition is reached, write operations are locked out. Following the , LH5420 FEATURES · Fast Cycle Times: 25/30/35 ns · Two 256 x 256 x 36 x 2 Bidirectional FIFO , . FUNCTIONAL DESCRIPTION The LH5420 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel , as 256 words by 36 bits. The LH5420 is ideal either for wide unidirectional applications or for


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PDF LH5420 36-bit 36/18/9-bit 132-pin 132-Pin, PQFP132-P-S950) LH5420P-25 D2SB 73
Not Available

Abstract:
Text: (PGA120-C-S1360) Example: LH5420P-25 (256 x 36 x 2 Bidirectional FIFO, 25 ns, 132-Lead, Plastic Quad Flat , LH5420 FEATURES · · · · · · · Fast Cycle Times: 25/30/35 ns Two 256 x 256 x 36 x 2 Bidirectional FIFO FUNCTIONAL DESCRIPTION The LH5420 contains two FIFO buffers, FIFO #1 and FIFO #2. These , each are organized as 256 words by 36 bits. The LH5420 is ideal either for wide unidirectional applications or for bidirectional data applications; component count and board area are reduced. The LH5420 has


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PDF LH5420 LH5420 36-bit 132-Lead. PQFP132-P-S950) 120-Lead, PGA120-C-S1360) LH5420P-25
lj26

Abstract:
Text: ) 256 x 36 x 2 Bidirectional FIFO Example: LH5420P-25 (256 x 36 x 2 Bidirectional FIFO, 25 ns, 132 , speed grade of LH5420. Whena FIFO full condition is reached, write operations are locked out. Following , LH5420 FEATURES • Fast Cycle Times: 25/30/35 ns • Two 256 x 36-bit FIFO Buffers • Full 36 , * FUNCTIONAL DESCRIPTION The LH5420 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel , 256 words by 36 bits. The LH5420 is ideal either for wide unidirectional applications or for


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PDF LH5420 36-bit 36/18/9-bit 132-pin 0D1L273 132-Pin, PQFP132-P-S950) LH5420P-25 lj26 D35B D35A
1995 - D35B 60

Abstract:
Text: slightly below the value which otherwise would be permissible for that speed grade of LH5420. When a FIFO , LH5420 256 × 36 × 2 Bidirectional FIFO FEATURES · TTL/CMOS-Compatible I/O · Fast Cycle , , Pomona, CA 91766, (909) 469-2900. 6-208 FUNCTIONAL DESCRIPTION The LH5420 contains two FIFO , data buffering. FIFO #1 and FIFO #2 each are organized as 256 words by 36 bits. The LH5420 is ideal , board area are reduced. The LH5420 has two 36-bit ports, Port A and Port B. Each port has its own


Original
PDF LH5420 36-bit 36/18/9-bit 132-pin 132-Pin, PQFP132-P-S950) LH5420P-25 D35B 60 D35B D35B 60 37 LH543620 D35A D26B9 D17b D15A D12A D11A
Not Available

Abstract:
Text: , Deeper 0.7|i-Technology Replacements for Sharp LH5420 and LH543601 · Functionally Upwards-Compatible from LH5420 and LH543601 · Two 512 x 36-bit or 1024 x 36-bit FIFO Buffers · Full 36-bit Word Width · , LH5420 /LH543601compatible operation, but it may be reprogrammed at will at any time during LH543611/21 , A 91766, (909) 469-2900. BOLD = Improved or added features over SHARP'S LH5420 architecture , functionality. LH5420 /LH543601 CONTROL REGISTER (WRITE-ONLY) (FOR COMPARISON PURPOSES) LH543611/21 CONTROL


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PDF LH543611/21 LH5420 LH543601 36-bit 36/18/9-bit 9/18-Bit
Not Available

Abstract:
Text: LH5494 M ! C FP 32 PGA LH5420 132 120


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PDF LH5481 LH5491 LH5496 LH5497 LH540202 LH5498 LH540203 LH5499 LH540204 LH540205
organizational structure samsung

Abstract:
Text: FIFO Cross Reference FIFO CROSS REFERENCE ORGANIZATIONAL STRUCTURE 256 X 36 X 2 SHARP MODEL * LH5420 COMPETITIVE VENDOR Mosel/Vitel ic National COMPETITIVE MODEL MS76542 NMF256X36X2 CY7C408 NMF64X8 CY7C409 NMF64X9 MS76492 NMFC5492 MS76493 NMFP5493 MS76494 NMFS5494 Am7201 CY7C420 CY7C421 ACCESS TIME 25/30/35 ns 35/25/15 MHz PACKAGE OPTIONS PQFP/PGA 64 X 8 64 X 9 LH5481 Cypress National DIP/PLCC LH5491 Cypress National 35/25/15 MHz DIP/PLCC PLCC PLCC 4,096 X 9 4,096


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PDF LH5420 MS76542 NMF256X36X2 CY7C408 NMF64X8 CY7C409 NMF64X9 MS76492 NMFC5492 MS76493 organizational structure samsung CYPRESS SAMSUNG CROSS REFERENCE DALLAS cross reference ic cross reference book KM75C02 MK4501 mosel VITELIC
vhdl code for fifo

Abstract:
Text: VHDL Behavioral FIFO Models VHDL BEHAVIORAL FIFO MODELS DEVICES SUPPORTED PART NUMBER MODEL INCLUDES · Source Code · Test Bench · User's Documentation · Free Technical Support · Sample Test Vectors FEATURES · Programmability for FIFO's Memory · Register · Depth · Offset Values · Error Reporting on Invalid Conditions · Built-In System Debugging Features · IEEE 1076-Compatible · VIEWIogic VHDL-Compatible ALL FROM ORGANIZATION LH5420 LH543620 LH540215 LH540225 256 x 36 x 2 1K x 36 5 12 x 18 1Kx18


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PDF 1076-Compatible LH5420 LH543620 LH540215 LH540225 1Kx18 1-800-RAVICAD vhdl code for fifo free vhdl code sample vhdl code for memory write
Not Available

Abstract:
Text: LH543620 FEATURES · Fast Cycle Times: 20/25/30 ns · Selectable 36/18/9-Bit Word Width on Both Input Port and Output Port · `Synchronous' Enable-Plus-Clock Control at Both Ports · Independently-Synchronized Operation of Input Port and Output Port · Pinout Similar to LH5420 256 x 36 x 2 Bidirectional FIFO · Most Control Input Signals are Synchronous, and are Assertive-LOW for Noise Immunity · High-Drive Three-State Outputs · Device Comes Up Into Known Default State at Reset; Programming is Allowed, but is not


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PDF LH543620 36/18/9-Bit LH5420 LH543620 36-bit
Not Available

Abstract:
Text: LH543620 FEATURES · Fast Cycle Times: 15/20/25/30 ns · Selectable 36/18/9-Bit Word Width on Both Input Port and Output Port · `Synchronous' Enable-Plus-Clock Control at Both Ports · Independently-Synchronized Operation of Input Port and Output Port · Pinout Similar to LH5420 256 x 36 x 2 Bidirectional FIFO · Control Inputs Sampled on Rising Clock Edge (Except RS and AOE) · Most Control Signals Assertive-LOW for Noise Immunity · High-Drive TTiree-State Outputs · Device Comes Up Into Known Default State at


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PDF LH543620 36/18/9-Bit LH5420 LH543620 36-bit
Not Available

Abstract:
Text: LH543620 FEATURES · Fast Cycle Times: 20/25/30 ns · Selectable 36/18/9-Bit Word Width on Both Input Port and Output Port · `Synchronous' Enable-Plus-Clock Control at Both Ports · Independently-Synchronized Operation of Input Port and Output Port · Pinout Similar to LH5420 256 x 36 x 2 Bidirectional FIFO · Most Control Input Signals are Synchronous, and are Assertive-LOW for Noise Immunity · High-Drive Three-State Outputs · Device Comes Up Into Known Default State at Reset; Programming is Allowed, but is not


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PDF LH543620 36/18/9-Bit LH5420 LH543620 36-bit LH543620S
1996 - D35B 60

Abstract:
Text: · · · · · · Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Expanded Control , operation initializes the LH543611/21 Control Register for LH5420 /LH543601-compatible operation, but it


Original
PDF LH543611/21 LH543611 LH543621 LH5420 LH543601, LH5420/LH543601 LH543611/21 D35B 60 D35B D35A D3A transistor datasheet D35B 60 89 D34B D33A D15A D12A
HD68HCOOOY12

Abstract:
Text: RN P/N PGA-072AH3-S PGA-124AH3-S Sharp P/N LH9124 LH5420 RN P/N PGA-262CH3-S PGA


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PDF AM29030 AM29117 AM29325 AM29331 AM80186 AM80286 A9850 AM95C60 AM29050 PGA-146CH3-S HD68HCOOOY12 HD64400 8207 siemens ad 7137 CY7C9101 MOTOROLA 68012
DNA 1001 DL

Abstract:
Text: LH543611/21 512x36x2/1024x36 x2 Synchronous Bidirectional FIFO FEATURES • Pin-Compatible and Functionally Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper • Expanded Control Register that is Fully Readable as well as Writable • Fast Cycle Times: 18/20/25/30/35 ns • Improved Input Setup and Flag Out Timing • Two 512 x 36-bit FIFO Buffers (LH543611) or Two 1024 x 36-bit FIFO Buffers , initializes the LH543611/21 Control Register for LH5420 /LH543601-compatible operation, but it may be


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PDF LH543611/21 512x36x2/1024x36 LH5420 LH543601, 36-bit LH543611) LH543621) 36/18/9-bit DNA 1001 DL D-33A D35B 60 74 DSB45
lh57257

Abstract:
Text: LH5420 LH543620P LH5481 LH5491 LH5492 LH5493 LH5494 LH5496 LH5497 LH5498 LH5499 LH571000 LH571000J


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PDF IR2E201 IR2E24 IR2E27/A IR2E28 IR2E29 IR2E30 IR2E31/A IR2E32N9 IR2E34 IR2E41 lh57257 IR2E31 IR2E01 IR2C07 IR2E27 IR2E19 IR3n06 IR2E31A IR2C36
Not Available

Abstract:
Text: Pin-Compatible and Functionally Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Expanded Control , ontrol R egister fo r LH5420 /LH543601-compatible operation, but it may be reprogrammed at will at any , 2 3 4 5 -6 7 8 NOTE: 1. LH5420 /LH543601 also have this Control-Register function. The same Control-Register bit, bit 00, controls both Port A and Port B functionality. LH5420 /LH543601 CO NTRO L REGISTER , ) 543611-12 Figure 10. LH5420 /LH543601 and LH543611/21 Control-Register Formats 2-390 SHARP


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PDF 512x36x2/1024x36x2 LH543611 LH543621 36-bit risi/21 144-pin,
D35B 60

Abstract:
Text: · · · · · Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper Expanded Control , operation initializes the LH543611/21 Control Register for LH5420 /LH543601-compatible operation, but it


Original
PDF LH543611/21 LH543611 LH543621 LH5420 LH543601, 144-pin, TQFP144-P-2020) 132-pin, D35B 60 D35B 60 74 D35B D35B 80 D35B 60 89 D35B 60 50 D26A D12A D11A
hitachi ic 29050 h

Abstract:
Text: G A -179C H 3-S LH5420 P G A -121A H 3-S X C 3064 PG A -132A H 3-S X C 30 90 P G A


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PDF -064A B2000 -135A -145AH C440H -120B -169B hitachi ic 29050 h 0/hitachi ic 29050 h semiconductor cross reference
D35B

Abstract:
Text: for LH5420 /LH543601-compatible operation, but it may be reprogrammed at will at any time during


Original
PDF LH54V3611/21 LH543611/21 36-bit LH54V3611) LH54V3621) 36/18/9-bit 144TQFP 144-pin D35B D35B 60 D20A D22A D35B 60 74
a04l

Abstract:
Text: for LH5420 /LH543601 -compatible operation, but it may be reprogrammed at will at any time during , NOTE: 1. LH5420 /LH543601 also have this Contra I-Register function. The same Control-Register bit, bit 00, controls both Port A and Port B functionality. LH5420 /LH543601 CONTROL REGISTER (WRITE-ONLY , ) 5 4 V 3 6 1 1 -4 Figure 9. LH5420 /LH543601 and LH54V3611/21 Control-Register Formats 20


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PDF LH54V3611/21 LH543611/21 36-bit LH54V3611) LH54V3621) 36/18/9-bit Almost-Full611/21 144-pin a04l aei cr
Supplyframe Tracking Pixel