The Datasheet Archive

LCHD-10 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2002 - Not Available

Abstract: No abstract text available
Text: Included MODEL NO. LCHD-5 LCHD-10 LCHD-25 LCHD-50 LCHD-100 LCHD-250 LCHD-500 LCHD-1K LCHD , ) LCHD-10K is a 10 ,000 lb capacity load cell, $935. Mating connector, (included) MS3102E-14S-6S. F , ±5 ± 10 ±25 ±50 ±100 ±250 ±500 ±1 K ±2 K ±3 K ±4 K ±5 K ±7.5 K ± 10 K ±15 K  , Style Load Cell SPECIFICATIONS: Excitation: 10 Vdc (15 V max) Output (FSO): ≤25 lb: 2 mV/V  , Capacity Input Resistance: 350 ± 10 Ω Output Resistance: 350 ± 10 Ω FS Deflection: .001 to .003"


Original
PDF LCHD-10 LCHD-25 LCHD-50 LCHD-100 LCHD-250 LCHD-500 LCHD-10K LCHD-15K LCHD-20K LCHD-30K
2005 - REQ60

Abstract: spru755c OMAP5912
Text: Figures Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 MPU GDMA Handler . . . . . . . . . . . . , 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 , 84 85 86 87 88 89 90 91 92 93 94 95 96 97 10 DMA LCD Bottom Address B1 L Register , 0xEC FUNC_MUX_MPU_DMA_B Controls mapping for system DMA requests 6 to 10 . R/W 0xF0 , CONF_ARM_DMA_REQ_ 10 Writing value n in this register maps DMA request source n+1 to system DMA controller


Original
PDF OMAP5912 SPRU755C OMAP5910/5912 SPRU890) REQ60 spru755c
LCHB

Abstract: A1046 DIP42S ILV00257 SSOP44
Text: 2.05.5 V L VIL 0.01.0 V tw 1.0 s thold 1.0 s fopg 100 , EQR(,0dB,0dB) GeqB max.Boost/Cut EstepB ±17 ±20 ±23 dB 1.0 2.0 3.0 dB EQR(,0dB,0dB) GeqT EstepT max.Boost/Cut ±15 ±18 ±21 dB 1.0 2.0 , =1% THDF DIN AUDIO 0.03 0.1 % VNOF DIN AUDIO -99 -85 dBV 0.3 V 1.0 , 38 Lch-D 7 8 ST-1 Stereo DC R-DC 35 ST-2 Pseud DC 36 L-DC 10


Original
PDF LV1117N/NV LV1117N/NVIC 0dB-14dB 1dB/-14-80dB2dB /--82dB) 20051207-S00008 A1046-1/19 LV1117N/1117NV A1046-18/19 LCHB A1046 DIP42S ILV00257 SSOP44
2008 - A1046

Abstract: transistor A1046 A1046 transistor R821 LV1117 DIP42S i2c tone volume dip
Text: data "H" level voltage VIH 2.0 to 5.5 V "L" level voltage VIL 0.0 to 1.0 V s Pulse width tw 1.0 Hold time thold 1.0 s Operating frequency fopg 100 kHz , 2.0 3.0 dB ±18 ±21 dB 1.0 2.0 3.0 dB -2.3 -1.3 -0.3 2.0 EstepB ±23 ±15 Max. Boost/Cut ±20 1.0 GeqB 2.5 Treble band EQ (Matrix through , noise voltage VNOF DIN AUDIO -99 -85 dBV 0.3 V 1.0 mA THD=1% dB Vrms


Original
PDF ENA1046 LV1117N/NV LV1117N/NV -14dB: step/-14dB -80dB: -82dB) A1046-18/18 A1046 transistor A1046 A1046 transistor R821 LV1117 DIP42S i2c tone volume dip
2004 - SPI NAND FLASH

Abstract: OMAP camera module hwa camera OMAP5912 OMAP5910 ARM926EJS omap1611 omap gpio OMAP 4 datasheet
Text: Contents 3.2 3.3 10 Constant Fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 199 199 199 200 200 SPRU755A Figures Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 , . . . . . . 187 SPRU755A OMAP5912 13 Tables Tables 1 2 3 4 5 6 7 8 9 10


Original
PDF OMAP5912 SPRU755A OMAP5912 SPI NAND FLASH OMAP camera module hwa camera OMAP5910 ARM926EJS omap1611 omap gpio OMAP 4 datasheet
Not Available

Abstract: No abstract text available
Text: V VIH 2.0 to 5.5 V “L” level voltage VIL 0.0 to 1.0 V Pulse width tφw 1.0 μs Hold time thold 1.0 μs Operating frequency fopg 100 kHz , 2.0 3.0 dB ±18 ±21 dB 1.0 2.0 3.0 dB -2.3 -1.3 -0.3 2.0 EstepB ±23 ±15 Max. Boost/Cut ±20 1.0 GeqB 2.5 Treble band EQ (Matrix through , noise voltage VNOF DIN AUDIO -99 -85 dBV 0.3 V 1.0 mA THD=1% dB Vrms


Original
PDF ENA1046 EN8263A LV1117N/NV LV1117N/NV A1046-18/18
Not Available

Abstract: No abstract text available
Text: V VIH 2.0 to 5.5 V “L” level voltage VIL 0.0 to 1.0 V Pulse width tφw 1.0 µs Hold time thold 1.0 µs Operating frequency fopg 100 kHz , resolution Max. Boost/Cut ±17 EstepB ±20 ±23 dB 1.0 2.0 3.0 dB ±15 ±18 ±21 dB 1.0 2.0 3.0 dB -2.3 -1.3 -0.3 2.0 2.5 Treble band EQ , Output noise voltage VNOF DIN AUDIO -99 -85 dBV 0.3 V 1.0 mA THD=1% dB


Original
PDF ENA1046 EN8263A LV1117N/NV LV1117N/NV A1046-18/18
Not Available

Abstract: No abstract text available
Text: Û0 Q C3 c D1 C ' C DO A3 A 2 C V ee C 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V , OUTPUT Dn L H ó Ò v OL V |H V |L TR U TH TABLE E a c n M E C L 10 K H s e r ie s c i r c u i t


OCR Scan
PDF MC10H145
ras 1210

Abstract: ras- 1210
Text: -, 10 column-addresses) · Optional SELF REFRESH m ode, with Extended Refresh rate (4X) 2 MEG x 8 DRAM , (DC-8) Vcc ( 1 DQ1 ( 2 DQ2 [ 3 DQ3C 4 DQ4 [ 5 WE C 6 RAS [ 7 NC [ B A1Q [ 9 A0 [ 10 A1 ( 11 A2 [ 12 , a ; A3 a Vcc a (DD-3) 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 , S is d esign ed to operate in a 3.3V + 10 % m em ory system . Each byte is uniquely a d d re sse d , latching 11 b its (A0-A10) an d then C A S latching 10 b its (A0-A9). The C A S control also determines


OCR Scan
PDF 200mW 048-cycle 28-Pin A0-A10; ras 1210 ras- 1210
Not Available

Abstract: No abstract text available
Text: V53C816L has asymmetric address 10 -bit row and 9-bit column. All inputs are TTL compatible. Fast Page Mode , I/06 I/07 I/08 c L C C 3 4 5 6 7 8 C 9 C 10 H Vss 1/016 1/015 1/014 3 1/013 Vss 1 , VITELIC Absolute Maximum Ratings* Ambient Temperature Under B ias.- 10 , - 1.0 V to +4.6 V Data Output Current. 50 mA Power Dissipation. 1.0 W 'N ote: Operation above Absolute Maximum Ratings can adversely affect device reliability


OCR Scan
PDF V53C816L 16-bit 256Kx16 40/44L-pin 0a04kfl3
Not Available

Abstract: No abstract text available
Text: DRAM FEATURES * * » * « • Single +5V ± 10 % power supply JEDEC-standard pinout and , the 20 address bits, w hich are entered 10 bits (A0 -A9) at a time. RAS latches the first 10 bits and CAS latches the latter 10 bits. A READ or WRITE cycle is selected w ith the WE input. A logic , A2 A3 V cc £ 9 r 10 C 11 C 12 [ 13 26 25 24 23 22 J } ] ] ] V ss DQ 4 DQ , Low (Logic 0) Voltage, all inputs VlL - 1.0 0.8 V INPUT LEAKAGE CURRENT Any input 0V


OCR Scan
PDF 024-cycle 128ms 25-35ns 128ms MT4C4007J 001E024
micron DRAM

Abstract: No abstract text available
Text: DQ23 DQ4 — » 10 -6 -7 -> 55 NC — » NC — » 56 Vss AO , —► DQ25 DQ27 38 D Q 10 -> r 39 D Q 11 -> D Q 12 41 D Q 13 42 , Address Inputs: These inputs are multiplexed and clocked by RAS and CAS. 2-8, 10 , 34, 36, 38-43 , entered 10 bits (A0-A9) at a time. RAS is used to latch the first 10 bits, and CAS latches the latter 10 , 10 10 20 20 ■H i li lB iï ll i! NC 2 NC m 3 4 5 NC NC NC


OCR Scan
PDF MT8D88C132H MT16D88C232H micron DRAM
Not Available

Abstract: No abstract text available
Text: columnaddresses • High-performance CMOS silicon-gate process • Single +5V ± 10 % power supply • All device , DQ6 c D DQ8 Vcc 10 DQ4 14 WE 16 NC A9 13 RÄS DQ2 12 ] NC 15 A9 [ 9 20 ] A8 A0 [ 10 19 ] A7 A1 [ 11 18 ] A6 A2 AO , cycles. The address is entered first by RAS latching 10 bits (A0-A9) and then CAS latching 9 bits , . MT4C8512/3S REV. 3/93 5 CÄS 4 8 WE [ MARKING 2 AO Œ CÜ 22 21 20 10


OCR Scan
PDF MT4C8513 024-cycle 128ms 350mW 28-Pin CYCLE24 MT4C851Z/3S
TT-612

Abstract: No abstract text available
Text: access cycles · 1,024-cycle refresh ( 10 row, 10 column addresses) · Extended Data-Out (EDO) PAGE MODE , 3 OE 4 5 X 9 IX 7 = a g 10 x 11 50 49 49 47 49 45 44 43 42 41 40 XI X X XI X X X X X X XI Vss DÛ) 5 , uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered 10 bits (A0 -A9) at a time. RAS# is used to latch the first 10 bits and CAS#, the latter 10 bits. The CAS , CASLffCASrtf V | /_ 'W ///////////i//////'/Y \ cau i,M 10 W ////////////K The DQs goto H itji-Z I W


OCR Scan
PDF 024-cycle 44/50-Pin 42-PIN TT-612
MT4LC2M8E7

Abstract: No abstract text available
Text: silicon-gate process · Single power supply (+3.3V ±0.3V or +5V ± 10 %) · All inputs, outputs and clocks are , low-power data retention · 11 row , 10 column addresses · Extended Data-Out (EDO) PAGE MODE access cycle · , DQ1 c 2 DQ2C 3 03 £ 4 DQ4C 5 WE# C 6 RAS# C 7 NCC 8 A 10L 9 A0 C 10 A l C 11 A2C 12 A3 13 Vcc 14 28 , A10 E 9 A0E 10 A1 [ 11 A2 E 12 A3 E 13 Vcc E 14 28 I Vss 27 3 DQB 26 ] 0 0 7 25 ] DQ6 24 ] 0 0 5 23 , OQ4 or 5 WE# c r 6 RAS# c r 7 NCOE 8 A10 ix l 9 A0 cxj 10 A1 CD 11 A2 eri 12 A3 c r 13 Vcc OE 14 n Vss


OCR Scan
PDF 28-Pin MT4LC2M8E7
Not Available

Abstract: No abstract text available
Text: A10 A0 A1 A2 A3 Vcc • [ 8 c9 [ 10 [ 11 [ 12 [ 13 VSS DQ4 26 25 24 23 22 , E ID n n A10 A0 A1 A2 A3 Vcc a Œ Œ ex Œ 8 9 10 11 12 13 19 18 17 , supply (+3.3V +0.3V or +5V ± 10 %) • All inputs, outputs and clocks are TTL-compatible • Refresh , retention • 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) â , the latter 10 bits for 4K, address pins A10 and A ll are "don't care"). READ and WRITE cycles are


OCR Scan
PDF 24/26-Pin NC/A11
Not Available

Abstract: No abstract text available
Text: ( 10 row-, 10 column-addresses) • Low power, 3mW standby; 225mW active, typical • Optional SELF , [ c [ c c 3 4 5 6 7 8 9 10 1 1 I I { [ [ 12 13 14 15 16 t 17 I 18 , „5 NC NC A0 A1 A2 A3 Vcc DQ4 7 Œ 3 Œ 9 Œ 10 Œ 1 1 50 49 48 47 46 45 44 43 , +1 V Input Low (Logic 0) Voltage, all inputs VlL - 1.0 0.8 V ll -2 2 ma loz - 10 10 ma VOH 2.4 PARAMETER/CONDITION INPUT LEAKAGE CURRENT Any input OV s


OCR Scan
PDF MT4LC1M16C3 024-cycle 225mW
PC06A

Abstract: COP311C COP410C COP411C carry skip adder 2 digit BCD adder ckt with display
Text: °C to + 70°C Storage Temperature Range -65°C to +150*0 Lead Temperature (Soldering, 10 sec.) 300 , time) HALT Mode Current2 Vcc= 5.0V, F|N = 0 kHz 30 tx A Vcc = 2.4V, Fin = 0 kHz 10 /xA Input , Output Voltage Levels Standard Outputs LSTTL Operation Vcc = 5.0V ± 10 % Logic High Ioh = -25 /xA 2.7 V Logic Low Iql = 400 jllA 0.4 V CMOS Operation Logic High l0h= - 10 mA Vcc-0.2 V Logic Low l0l= 10 jliA 0.2 V Output Current Levels4 (Except CKO) Sink VCC = 4.5V, V0ut = Vcc 1.2


OCR Scan
PDF C0P410C/COP411C/C0P310C/COP311C COP410C, C0P411C, CC5P310C, C0P311C PC06A COP311C COP410C COP411C carry skip adder 2 digit BCD adder ckt with display
Not Available

Abstract: No abstract text available
Text: PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 , through the address bits. RAS# is u sed to latch the first 12 bits and CAS# the latter 10 bits. READ and , 0 0 1 0 0 0 0 10 0 0 0 0 0 0 0 0 00 TOTAL NUMBER , INTERFACE 9 RAS# ACCESS TIME ('RAC) 128 12 10 NONE LVTTL 10 CAS# ACCESS TIME (>CAC , Input Low (Logic 0) Voltage, all inputs V VlL - 1.0 0.8 V INPUT LEAKAGE CURRENT RASO


OCR Scan
PDF MT4LDT464H 144-pin, 096-cycle 256ms
Not Available

Abstract: No abstract text available
Text: ance CM OS silicon-gate process · Single +5V ± 10 % power supply · Low power, lm W standby; 500mW active , 40 39 38 znvss 3DDQ16 HID Q15 ID D Q 14 XDDQ13 H Vss I3 D Q 12 H ID Q 1 1 36 ID D Q 10 X ID Q 9 2 4 6 8 DQ10 DQ12 DQ13 DQ15 10 Vss 12 DQ1 16 Vcc 18 DQ6 20 DQ8 22 WEL/NC" OPTIONS · , 16258 S 16259 S OË ·NC/CASL 7 g 10 3 7 3 5 DJ TG Z Part Number Example: M T4C16256DJ-7 S , , 10 , 31 NC Vcc Vss - Supply Power Supply: +5V ± 10 % Supply Ground 1-98 Micron


OCR Scan
PDF 500mW 512-cycle
LC7869E

Abstract: LC7867
Text: Chôme, Ueno, Taito-ku, T O K Y O , 1 10 JA P A N i 93Û96HA (OT) No. 5467-1/29 f LC70622E , : Figure 5 EFMIN: Slice level control X !N: Capacitor-coupled input EFMIN X|N, X qut 16,9344 1.0 1.0 10 400 , General-Purpose Port Output Timing No. 5467-6/29 LC78622E Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 1 , Applications 1. HF Signal Input Circuit; Pin 10 : EFMIN, pin 9: EFMO, pin 1: DEFI, pin 12: CLV+ An EFM signal , /P High High Low · Rough servo gain switching M SB 1 0 1 0 0 10 0 10 LSB 0 0 0 1 Command DISC 8 S


OCR Scan
PDF LC78622E LC78622E LC7869E LC7867
Not Available

Abstract: No abstract text available
Text: IN : Slice level control 1.0 V in (2) Input level ns 1200 X in : Capacitor-coupled input 1.0 Operating frequency range fop Crystal oscillator frequency fx Vp-p EF M IN 10 16.9344 X|N- *OUT ns Vp-p MH z MHz Text readout time tew D Q S Y , 0 V. 9 EFM O 0 10 E F M IN I E F M signal output 11 TEST2 I 12 , V qd and X V qo - Pin Applications H F Signal Input Circuit; Pin 10 : EFM IN , pin 9: EFM O , pin


OCR Scan
PDF EN5811 LC78624E LC78624E QFP64E QFP80E OFP64E
2004 - LCD for mobile phone

Abstract: LED display single color module circuit for p10 lpg 889 Microcontroller AT89C51 used in display bus LCD 8 pin Microcontroller AT89s52 connections with lcd 24 pin stn lcd pinout details different types of lcd display lpp 68 g1 8 Pinout monochrome lcd
Text: Contents 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 10 LCD TFT (LcdTFT) . . . . . . . , 79 82 84 106 107 108 108 108 11 Figures Figures 1 2 3 4 5 6 7 8 9 10 11 , 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33


Original
PDF OMAP5912 SPRU764A LCD for mobile phone LED display single color module circuit for p10 lpg 889 Microcontroller AT89C51 used in display bus LCD 8 pin Microcontroller AT89s52 connections with lcd 24 pin stn lcd pinout details different types of lcd display lpp 68 g1 8 Pinout monochrome lcd
2004 - transistor c900

Abstract: microcontroller based traffic light control OMAP5912 OMAP5910 OMAP4 OMAP 4 ND3N nand flash sdio nand flash MPU 131
Text: 3.4 3.5 3.6 3.7 3.8 3.9 4 10 3.2.15 External Device Reset Control . . . . . . . . . . . , 11 Figures Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 12 OMAP3 , . . . . . . . 194 OMAP5912 SPRU749A Tables Tables 1 2 3 4 5 6 7 8 9 10 11


Original
PDF OMAP5912 SPRU749A ARM926EJS OMAP5912 transistor c900 microcontroller based traffic light control OMAP5910 OMAP4 OMAP 4 ND3N nand flash sdio nand flash MPU 131
2006 - 0C00

Abstract: ARM926EJS OMAP5912
Text: . 7. 8. 9. 10 . 11. 12. 13. 14. 15. 16. 17. 18. 8 OMAP3.2 Gigacell . . . . . . . . . . , 59 60 61 62 63 64 65 66 67 9 Figures 37. 38. 39. 40. 41. 42. 43. 10 , . 2. 3. 4. 5. 6. 7. 8. 9. 10 . 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23


Original
PDF OMAP5912 SPRU749B 0C00 ARM926EJS
Supplyframe Tracking Pixel