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JESD51

Abstract: JEDEC51-12 JESD51-12 JESD51-1 JESD51-4 JESD51-7 JESD-51 JESD51-8 APP4083 AN4083
Text: Packages JESD51-4 : Thermal Test Chip Guideline (Wire Bond Type Chip) JESD51-5 : Extension of Thermal Test , thermal-characterization parameter, measured in units of °C/W. The JESD51-12 , Guidelines for Reporting and Using Package , package, a fact that makes JB more useful for customer applications. Refer to the JEDEC standards JESD51-8 and JESD51-12 for more detailed specifications on this parameter. Designers can determine JB and JB , Semiconductor Device) JESD51-1 : Integrated Circuit Thermal Measurement Method-Electrical Test Method (Single


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PDF com/an4083 AN4083, APP4083, Appnote4083, JESD51 JEDEC51-12 JESD51-12 JESD51-1 JESD51-4 JESD51-7 JESD-51 JESD51-8 APP4083 AN4083
2005 - JEDEC JESD51-8 BGA

Abstract: JESD51-8 jesd51 8 JESD51-5 800E-02 JESD51-7 G38-87 JEDEC JESD51-8 JESD51-3 MO-166
Text: is designed per JEDEC JESD51-3 and JEDEC JESD51-5. 3. Per JEDEC JESD51-6 with the board horizontal. 2s2p board is designed per JEDEC EIA/ JESD51-5 and JEDEC JESD51-7. 4. Thermal resistance between the , convection environment. The 1s test board is designed per JEDEC JESD51-3 [6] and JEDEC JESD51-5 [7]. Another , two internal planes (2s2p). The 2s2p test board is designed per JEDEC JESD51-5 [7] and JEDEC JESD51-7 , surface of the board near the package. 2s2p board is designed per JEDEC JESD51-5 and JEDEC JESD51-7. 5


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PDF AN2388 JEDEC JESD51-8 BGA JESD51-8 jesd51 8 JESD51-5 800E-02 JESD51-7 G38-87 JEDEC JESD51-8 JESD51-3 MO-166
2002 - JESD51-5

Abstract: JESD-51-5 JEDEC JESD51-8 BGA MO-166 outline of the heat slug for JEDEC JESD51-8 JESD-51 800E-02 jesd51 8 HSOP 30
Text: board horizontal. Single layer board is designed per JEDEC JESD51-3 and JEDEC JESD51-5. 3. Per JEDEC JESD51-6 with the board horizontal. 2s2p board is designed per JEDEC EIA/ JESD51-5 and JEDEC JESD51-7. 4 , . Junction-to-ambient thermal resistance (Theta-JA or RJA per JEDEC JESD51-2 [5]) is a one-dimensional value that , a natural convection environment. The 1s test board is designed per JEDEC JESD51-3 [6] and JEDEC JESD51-5 [7]. Another thermal resistance that is commonly reported is Theta-JMA or RJMA on a board with


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PDF AN2388/D JESD51-5 JESD-51-5 JEDEC JESD51-8 BGA MO-166 outline of the heat slug for JEDEC JESD51-8 JESD-51 800E-02 jesd51 8 HSOP 30
2002 - JEP140

Abstract: JESD51-9 pcb board 0.035mm JESD51-10 PCB 1.2mm FR4 1oz cu JEP-140 JESD51-11 JESD51-X jesd51 6 JESD51-1
Text: specs: - JESD51-5 add-on to JESD51-7 : Most surface mount packages. - JESD51-9 : Area array (e.g. BGA). , surface mount packages. - JESD51-9 : Area array (e.g. BGA). - JESD51-10 : Through-hole perimeter leaded , style). · Applicable JEDEC board specs: - JESD51-7 : Most surface mount packages. - JESD51-9 : Area array (e.g. BGA). - JESD51-10 : Through-hole perimeter leaded (e.g. DIP, SIP). - JESD51-11 , PCB's. · Optional test in JESD51-2 and JESD51-6 JA standards. · For plastic packages, depends mainly


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PDF TB379 JEP140 JESD51-9 pcb board 0.035mm JESD51-10 PCB 1.2mm FR4 1oz cu JEP-140 JESD51-11 JESD51-X jesd51 6 JESD51-1
2002 - JESD51-9

Abstract: JEP140 JEP-140 JESD51-10 JEDEC JESD51-8 JESD51-5 JESD51-3 JC JB jt thermal resistance standards Reliability Test Methods for Packaged Devices
Text: specs: - JESD51-5 add-on to JESD51-7 : Most surface mount packages. - JESD51-9 : Area array (e.g. BGA). , surface mount packages. - JESD51-9 : Area array (e.g. BGA). - JESD51-10 : Through-hole perimeter leaded , style). · Applicable JEDEC board specs: - JESD51-7 : Most surface mount packages. - JESD51-9 : Area array (e.g. BGA). - JESD51-10 : Through-hole perimeter leaded (e.g. DIP, SIP). - JESD51-11 , calculation of TJ rise above Tt for devices on application PCB's. · Optional test in JESD51-2 and JESD51-6


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PDF TB379 JESD51-9 JEP140 JEP-140 JESD51-10 JEDEC JESD51-8 JESD51-5 JESD51-3 JC JB jt thermal resistance standards Reliability Test Methods for Packaged Devices
2010 - dap 010

Abstract: JESD51-3 dap11 "thermal via" AN-1378 JESD22-A114 JESD-51 100K adj dap 11
Text: ) JEDEC EIA/ JESD51-3 Figure 1 4 PCB DAP TO-263 JA DAP JEDEC EIA/ JESD51-5 EIA/ JESD51-7 Figure 3 4 PCB DAP DAP JEDEC EIA/ JESD51-5 EIA/ JESD51-7 FIGURE 1 , : (TA) (PD) (TJ(MAX) (JA) JA 2 PCB (EIA/ JESD51-3 ) Note 5: VADJ Note 6 , /W JA 67 /W DAP PCB 1 0.055 (0.22 × 0.25 ) JEDEC EIA/ JESD51-3 PSOP-8 PSOP


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PDF LP38511-ADJ 800mA 100kHz O-263 DS300408-04-JP dap 010 JESD51-3 dap11 "thermal via" AN-1378 JESD22-A114 JESD-51 100K adj dap 11
2005 - JESD51-5

Abstract: JESD-51-5 JESD-51 JEDEC JESD51-8 JESD51-7 JESD51-3 JESD51-2 jesd51 8 JESD51 MC33886
Text: NOTES: Soldermast openings 1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3.Per JEDEC JESD51-8 , with the board temperature on the center trace near the center lead. 4.Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5.Thermal resistance between the die junction and the exposed pad surface; cold plate , Direct Thermal Attachment According to JESD51-5 A AGND FS IN1 V+ V+ OUT1 OUT1 DNC PGND


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PDF MC33886DHTAD 33886DH MC33886 20-TERMINAL 98ASH70such JESD51-5 JESD-51-5 JESD-51 JEDEC JESD51-8 JESD51-7 JESD51-3 JESD51-2 jesd51 8 JESD51
2005 - 33186DH

Abstract: JESD51
Text: Pattern for Direct Thermal Attachment According to JESD51-5 1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3.Per JEDEC JESD51-8 , per JEDEC JESD51-3 and JESD51-5. 5.Thermal resistance between the die junction and the exposed pad


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PDF MC33186DHTAD MC33186 33186DH 20-TERMINAL 98ASH70273A 33186DH JESD51
1999 - JESD51-7

Abstract: JESD51-1 JESD-51 G30-88 JESD-51-1 JESD51 JESD51-5 TB379 thermal resistance standards
Text: the "JEDEC 1S" board. In addition to the above mentioned JEDEC specifications, JESD51-5 should be , will result in lower (better) thermal resistance values than a 1S or SEMI board. [3] EIA/ JESD51-2 , provided. [2] EIA/ JESD51-1 Integrated circuit thermal measurement method - electrical test method. [4] EIA/ JESD51-6 Integrated circuit thermal test method environmental conditions - forced convection (moving air). [5] EIA/ JESD51-3 Low effective thermal conductivity test board for leaded surface mount


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PDF TB379 JESD51-7 JESD51-1 JESD-51 G30-88 JESD-51-1 JESD51 JESD51-5 thermal resistance standards
1999 - GR-1089-CORE

Abstract: I3124 LITTELFUSE PTC TISP4360H3BJ
Text: current ratings at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB with standard , VGEN = 600 Vrms, 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 , TISP4360H3BJ IT(OV)M Figure 8. VDRM DERATING FACTOR 1.00 EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB , PARAMETER TEST CONDITIONS MIN EIA/ JESD51-3 PCB, IT = ITSM(1000), RJA Junction to free air , ) 265 mm x 210 mm populated line card, UNIT °C/W 50 6: EIA/ JESD51-2 environment and PCB has


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PDF TISP4360H3BJ GR-1089-CORE K20/21 GR-1089 GR-1089-CORE I3124 LITTELFUSE PTC TISP4360H3BJ
1997 - GR-1089-CORE

Abstract: TISP4070H3BJ TISP4095H3BJ TISP4125H3BJ TISP4200H3BJ TISP4240H3BJ TISP4400H3BJ 4145H3 tisp4300h3bj
Text: at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB with standard footprint , TI4HAC 30 VGEN = 600 Vrms, 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 , MIN TEST CONDITIONS TYP MAX EIA/ JESD51-3 PCB, IT = ITSM(1000), RJA 265 mm x 210 mm , ) Junction to free air thermal resistance °C/W 50 7: EIA/ JESD51-2 environment and PCB has standard , 30 20 15 10 7 5 4 3 1 0·1 1000 ITSM(t) APPLIED FOR TIME t EIA/ JESD51-2 ENVIRONMENT


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PDF TISP4070H3BJ TISP4095H3BJ, TISP4125H3BJ TISP4200H3BJ, TISP4240H3BJ TISP4400H3BJ K20/21 GR-1089-CORE TISP4095H3BJ TISP4200H3BJ TISP4400H3BJ 4145H3 tisp4300h3bj
1997 - GR-1089-CORE

Abstract: I3124 TISP4165H4BJ TISP4200H4BJ TISP4265H4BJ TISP4350H4BJ
Text: /ITSM(t) 20 EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C 15 10 9 8 7 6 5 4 3 , Applications Information and Figure 11 for current ratings at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring track , Junction to free air thermal resistance Test Conditions Min. EIA/ JESD51-3 PCB, IT = ITSM(1000 , °C 113 °C /W 50 7: EIA/ JESD51-2 environment and PCB has standard footprint dimensions


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PDF TISP4165H4BJ TISP4200H4BJ, TISP4265H4BJ TISP4350H4BJ GR-1089-CORE I3124 TISP4200H4BJ TISP4350H4BJ
1999 - Not Available

Abstract: No abstract text available
Text: . EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB with standard footprint dimensions connected with 5 A , VGEN = 600 Vrms, 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C , = VGEN/IT(OV)M EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C TISP4360H3BJ IT(OV)M UL , Coff Off-state capacitance pF Thermal Characteristics Parameter Test Conditions EIA/ JESD51-3 , resistance NOTE 6: EIA/ JESD51-2 environment and PCB has standard footprint dimensions connected with 5


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PDF TISP4360H3BJ TISP4360H3BJ GR-1089-CORE GR-1089-CORE TISP4360H3BJR-S TISP4360H3BJ-S
2006 - JESD-51-5

Abstract: JESD51-5 JESD-51 HSOP 30 JESD51-7 JESD51-2 JESD51-3 MC33887 jesd51 8
Text: Soldermast openings NOTES: 1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3.Per JEDEC JESD51-8 , with the board temperature on the center trace near the center lead. 4.Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5.Thermal resistance between the die junction and the exposed pad surface; cold plate , Thermal Attachment According to JESD51-5 A Tab AGND FS IN1 V+ V+ OUT1 OUT1 FB PGND PGND


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PDF MC33887DHTAD 33887DH 20-TERMINAL MC33887 JESD-51-5 JESD51-5 JESD-51 HSOP 30 JESD51-7 JESD51-2 JESD51-3 jesd51 8
2005 - JESD51

Abstract: JESD51-2 MC33486 MC33486A JEDEC JESD51-8 JESD51-5
Text: JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8 , with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between , Figure 1. Thermal Land Pattern for Direct Thermal Attachment per JESD51-5 A VBAT GND 1 20


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PDF MC33486ADHTAD 33486ADH MC33486 20-TERMINAL MC33486A JESD51 JESD51-2 JEDEC JESD51-8 JESD51-5
1997 - TISP4080H3BJ

Abstract: TISP4350H3BJ TISP4240H3BJ TISP4220H3BJ TISP4125H3BJ TISP4115H3BJ TISP4070H3BJ TISP4070H3 GR-1089-CORE TISP4400H3BJ
Text: 11 for current ratings at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB with , /60 Hz RGEN = 1.4*VGEN/ITSM(t) 20 EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C 15 , ) APPLIED FOR TIME t EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C 2 1.5 1 0·1 1000 t , / JESD51-3 PCB, IT = ITSM(1000), TA = 25 °C, (see Note 7) 265 mm x 210 mm populated line card, 4-layer PCB, IT = ITSM(1000), TA = 25 °C 113 °C/W 50 7: EIA/ JESD51-2 environment and PCB has standard


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PDF TISP4070H3BJ TISP4115H3BJ, TISP4125H3BJ TISP4220H3BJ, TISP4240H3BJ TISP4400H3BJ GR-1089-CORE, UL1950, TISP4350H3BJ TISP4080H3BJ TISP4220H3BJ TISP4115H3BJ TISP4070H3 GR-1089-CORE TISP4400H3BJ
JESD51-2

Abstract: JESD-51 JESD51-9 JESD51-6 G30-88 JESD51-3 JESD51 thermal resistance jesd51 6 SAMSUNG TSOP
Text: Thermal Conductivity Test Board : JESD51-3 /7 Area Array Thermal Test Board : JESD51-9 The Leader in , Resistance, ja - Natural Convection(using test chamber) : JEDEC Standard JESD51-2 - Forced Convection(using wind tunnel) : JEDEC Standard JESD51-6 Junction-to-Case Thermal Resistance, jc - Cold Plate Method


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PDF JESD51-2 JESD51-6 G30-88 JESD51-3/7 JESD51-9 JESD51-2 JESD-51 JESD51-9 JESD51-6 G30-88 JESD51-3 JESD51 thermal resistance jesd51 6 SAMSUNG TSOP
1997 - GR-1089-CORE

Abstract: TISP4070M3BJ TISP4095M3BJ TISP4125M3BJ TISP4200M3BJ TISP4240M3BJ TISP4400M3BJ
Text: at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB with standard footprint , , 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C 20 15 , 0·1 ITSM(t) APPLIED FOR TIME t EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C 1 10 , MIN TEST CONDITIONS TYP MAX EIA/ JESD51-3 PCB, IT = ITSM(1000), RJA 265 mm x 210 mm , ) Junction to free air thermal resistance °C/W 52 7: EIA/ JESD51-2 environment and PCB has standard


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PDF TISP4070M3BJ TISP4095M3BJ, TISP4125M3BJ TISP4200M3BJ, TISP4240M3BJ TISP4400M3BJ K20/21 GR-1089-CORE TISP4095M3BJ TISP4200M3BJ TISP4400M3BJ
1997 - Not Available

Abstract: No abstract text available
Text: at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB with standard footprint , 5 4 3 2 1.5 0·1 1 10 100 1000 RGEN = 1.4*VGEN/ITSM(t) EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = , CONDITIONS EIA/ JESD51-3 PCB, IT = ITSM(1000), RJA Junction to free air thermal resistance TA = 25 °C, (see , MAX 113 °C/W UNIT 7: EIA/ JESD51-2 environment and PCB has standard footprint dimensions connected , 100 70 50 40 30 20 15 10 7 5 4 3 2 1.5 1 0·1 1 TI4HAE ITSM(t) APPLIED FOR TIME t EIA/ JESD51-2


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PDF TISP4070H3BJ TISP4115H3BJ, TISP4125H3BJ TISP4220H3BJ, TISP4240H3BJ TISP4400H3BJ
2006 - JESD-51-5

Abstract: JESD51-5 JESD51 JESD-51 JESD51-7 JESD51-2 jesd51 8 JEDEC JESD51-8 MC33186 JESD51-3
Text: ), (3) 9.0 RJA (1), (4) 69 RJC (5) 1.0 2.0 Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3. Per JEDEC JESD51-8 , with the board temperature on the center trace near the center lead. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the , Thermal Attachment According to JESD51-5 A AGND SF IN1 VBAT VBAT OUT1 OUT1 COD PGND PGND


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PDF MC33186DHTAD 33186DH MC33186 20-TERMINAL JESD-51-5 JESD51-5 JESD51 JESD-51 JESD51-7 JESD51-2 jesd51 8 JEDEC JESD51-8 JESD51-3
2009 - SAC1205

Abstract: IPC-A-600G IPC-6012 WLCSP stencil design JESD-B111 AN3846 sac105 WLCSP smt IPC 6012 IPC-6016
Text: Internal Planes - 2s2p (designed per JEDEC EIA / JESD51-5 [14] and JEDEC EIA / JESD51-7 [15] Thermal , designed per JEDEC EIA/ JESD51-3 and JEDEC EIA/ JESD51-5. R JA helps estimate the thermal performance of the , internal planes (2s2p). The 2s2p test board is designed per JEDEC EIA/ JESD51-5 and JEDEC EIA/ JESD51-7. R , resistance. JEDEC EIA/ JESD51-2 with the single layer board horizontal. Board conforms to JEDEC EIA/ JESD51-3 and JEDEC EIA/ JESD51-5. Per JEDEC JESD51-6 [19] with the board horizontal. Board conforms to JEDEC


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PDF AN3846 SAC1205 IPC-A-600G IPC-6012 WLCSP stencil design JESD-B111 AN3846 sac105 WLCSP smt IPC 6012 IPC-6016
1999 - GR-1089-CORE

Abstract: I3124 TISP4360H3BJ TISP4360H3BJR TISP4350H3BJ
Text: Information and Figure 10 for current ratings at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 , RGEN = 1.4*VGEN/ITSM(t) 20 EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C 15 I - , Information 10 9 8 7 6 5 4 3 1.5 0·1 10 100 EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB , NOTE 230 Junction to free air thermal resistance Test Conditions Min. EIA/ JESD51-3 PCB , ITSM(1000), TA = 25 °C 113 °C/W 50 6: EIA/ JESD51-2 environment and PCB has standard footprint


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PDF TISP4360H3BJ TISP4360H3BJ GR-1089-CORE GR-1089-CORE I3124 TISP4360H3BJR TISP4350H3BJ
1997 - Not Available

Abstract: No abstract text available
Text: and Figure 11 for current ratings at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB , RGEN = 1.4*VGEN/ITSM(t) EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C TI4HAC THERMAL , 3 2 1.5 1 0·1 1 TI4HAE ITSM(t) APPLIED FOR TIME t EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA , characteristics PARAMETER TEST CONDITIONS EIA/ JESD51-3 PCB, IT = ITSM(1000), RJA Junction to free air thermal , 25 °C NOTE 50 MIN TYP MAX 113 °C/W UNIT 7: EIA/ JESD51-2 environment and PCB has standard footprint


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PDF TISP4070H3BJ TISP4095H3BJ, TISP4125H3BJ TISP4200H3BJ, TISP4240H3BJ TISP4400H3BJ K20/21
1997 - Not Available

Abstract: No abstract text available
Text: at other temperatures. EIA/ JESD51-2 environment and EIA/ JESD51-3 PCB with standard footprint , 70 71 60 65 55 30 24 28 22 pF thermal characteristics PARAMETER TEST CONDITIONS EIA/ JESD51-3 , NOTE 6: EIA/ JESD51-2 environment and PCB has standard footprint dimensions connected with 5 A rated , 20 15 10 9 8 7 6 5 4 3 2 1.5 0·1 1 10 100 1000 RGEN = 1.4*VGEN/ITSM(t) EIA/ JESD51-2 ENVIRONMENT EIA/ JESD51-3 PCB TA = 25 °C TI4HAC THERMAL IMPEDANCE vs POWER DURATION 150 ZJA(t) - Transient Thermal


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PDF TISP4165H4BJ TISP4200H4BJ, TISP4265H4BJ TISP4350H4BJ K20/21
2001 - JESD51-8

Abstract: JESD51-2 JEDEC JESD51-8 surface mount package dimensions qfn 44 PACKAGE footprint 9mm FREESCALE PACKING jesd51 8 JEDEC-STD-020 JEDEC-STD020 tqfp 44 PACKAGE footprint
Text: Test Condition JESD51-2 JESD51-8 JESD51-5 GUIDELINES FOR SOLDERING: The Motorola portfolio of , Test Condition JESD51-2 JESD51-8 JESD51-5 Power Dissipation: 2.0 W to 5.0 W For More , 80°C/W 12°C/W - 55°C/W 1°C/W - 2°C/W Test Condition JESD51-2 JESD51-8 JESD51-5 Power , JESD51-2 JESD51-8 GUIDELINES FOR SOLDERING: Motorola's broad array of Small Outline IC's (SOIC , 100°C/W RJA 10°C/W - 40°C/W RJL 1°C/W - 2°C/W RJC* *SOICW-Exposed Pad Test Condition JESD51-2


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PDF BR1568/D JESD51-8 JESD51-2 JEDEC JESD51-8 surface mount package dimensions qfn 44 PACKAGE footprint 9mm FREESCALE PACKING jesd51 8 JEDEC-STD-020 JEDEC-STD020 tqfp 44 PACKAGE footprint
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