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Part Manufacturer Description Datasheet Download Buy Part
TS3DDR4000ZBAR Texas Instruments 12-Bits 1:2 High Speed DDR2/DDR3/DDR4 Switch/Multiplexer 48-NFBGA -40 to 85
CAB4AZNRR Texas Instruments DDR4RCD01 JEDEC compliant DDR4 Register for RDIMM and LRDIMM operation up to DDR4-2400 253-NFBGA 0 to 0
SN74SSQE32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
SN74SSQEA32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
SN74SSQEB32882ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
HPA00441ZALR Texas Instruments JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85

JEDEC DDR4 pcb layout Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2014 - 78730-1002

Abstract:
Text: forklocks for robust PCB retention Underside of SMT version DDR4 DIMM Socket showing housing and , Available in Press-fit, SMT and Through-hole mounting, DDR4 DIMM sockets offer significant assemblyprocessing compatibility and cost savings in high-speed server memory applications Meeting JEDEC specifications, Molex’s Vertical Press-fit, SMT and Through hole DDR4 DIMM sockets support *UDIMMs, RDIMMs and , data speed and lower operating voltage than DDR3. DDR4 DIMM Sockets, Halogen-free 78726 Vertical


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PDF PS-78730-001 PS-78731-001 USA/KC/2014 78730-1002 78726-1005
JESD79-3D

Abstract:
Text: levels • The first QorIQ device with DDR4 is expected by end of 2013 (T1040). TM 4 • Supported by all major memory vendors TM 5 100% 80% DDR4 60% DDR3 DDR2 40% DDR 20% 0% 2010 DDR DDR2 DDR3 DDR4 TM 2011 2010 9% 37% 54% 0% 2012 2011 7% 23 , TM 8 Feature/Category DDR3 DDR4 Package BGA only BGA only Densities 512Mb , -2/ AL+CL/ AL +CWL Same as DDR3 TM 9 Feature/Category DDR3 DDR4 CRC Data Bus No


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PDF
Not Available

Abstract:
Text: PI2DDR3212 1.35V/ 1.5V/1.8V 14 bit 2:1 DDR3/ DDR4 Switch Features Description ÎÎ bit 2:1 switch that supports DDR3 800 2133Mbps, DDR4 14 This 14-bit DDR3/ DDR4 switch is designed for 1.35V , signals. It is designed for DDR3 or DDR4 memory bus with speed up to 5Gbps. It supports DDR3 800 2133Mbps and DDR4 1600~4266 Mbps. 1600~4266 Mbps ÎÎ VDD 1.35V/ 1.5V/ 1.8V ÎÎ Flow through pinout option for easy layout ÎÎ SEL and Global Enable PI2DDR3212 has a 1:2 demux or 2:1 mux


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PDF PI2DDR3212 2133Mbps, 14-bit 2133Mbps PI2DDR3212 14-bit MO-220 52-Pin, PD-2102
Not Available

Abstract:
Text: PI2DDR3212 1.35V/ 1.5V/1.8V 14 bit 2:1 DDR3/ DDR4 Switch Features Description ÎÎ bit 2:1 switch that supports DDR3 800 2133Mbps, DDR4 14 This 14-bit DDR3/ DDR4 switch is designed for 1.35V , signals. It is designed for DDR3 or DDR4 memory bus with speed up to 5Gbps. It supports DDR3 800 2133Mbps and DDR4 1600~4266 Mbps. 1600~4266 Mbps ÎÎ VDD 1.35V/ 1.5V/ 1.8V ÎÎ Flow through pinout option for easy layout ÎÎ SEL and Global Enable PI2DDR3212 has a 1:2 demux or 2:1 mux


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PDF PI2DDR3212 2133Mbps, 14-bit 2133Mbps PI2DDR3212 14-bit MO-220 52-Pin, PD-2102 PI2DDR3212ZLE
2013 - MT40A512M8

Abstract:
Text: ). The device complies with the JEDEC DDR4 Register Specification. The register section of the , programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR4 , 4GB (x72, ECC, SR) 284-Pin DDR4 RDIMM Features DDR4 SDRAM RDIMM MTA9ASF51272PZ ­ 4GB Features · DDR4 functionality and operations supported as defined in the component data sheet · 284 , °C T A +95°C) · Package ­ 284-pin DIMM (halogen-free) · Frequency/CAS latency ­ 0.83ns @ CL = 16 ( DDR4


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PDF 284-Pin MTA9ASF51272PZ 284-pin, PC4-2400, PC4-2133, PC4-1866 125mV 09005aef85197107 asf9c512x72pz MT40A512M8 DDR4 PC4-2133 MTA9ASF51272PZ-2G1 DDR4 DIMM SPD JEDEC micron ddr4 DDR4 jedec MTA9ASF51272PZ DIMM DDR4 connector MO-309
2013 - EE1004

Abstract:
Text: comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The , 8GB (x64, DR) 288-Pin DDR4 UDIMM Features DDR4 SDRAM UDIMM MTA16ATF1G64AZ – 8GB Features Figure 1: 288-Pin UDIMM (MO-309, R/C-B) • DDR4 functionality and operations supported as defined in , latency – 0.83ns @ CL = 16 ( DDR4 -2400) – 0.93ns @ CL = 15 ( DDR4 -2133) – 1.07ns @ CL = 13 ( DDR4 , by Micron without notice. 8GB (x64, DR) 288-Pin DDR4 UDIMM Features Table 2: Addressing


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PDF 288-Pin MTA16ATF1G64AZ MO-309, 288-pin, PC4-2400, PC4-2133, PC4-1866 09005aef85202c0f atf16c1gx64az EE1004 MT40A512M8
2014 - SC2597SETRC

Abstract:
Text: ® The SC2597 is designed to meet the latest JEDEC specification for low power DDR3 and DDR4 , while also , effecting to the loop stability is parasitic inductance in PCB layout and output capacitor ESL. The gain , Model PCB Layout Input Capacitor The primary purpose of input capacitance is to provide the charge , ): 0.5V to 1.8V Bias Voltage (VDD): 2.35V to 3.6V Up to 3A sink or source from VTT for DDR through DDR4 , with industry leading specifications make SC2597 an attractive solution for DDR through DDR4


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PDF SC2597 SC2597 SC2597SETRC
2013 - DDR4

Abstract:
Text: 4GB (x72, ECC, SR) 284-Pin DDR4 UDIMM Features DDR4 SDRAM UDIMM MTA9ASF51272AZ ­ 4GB Features · DDR4 functionality and operations supported as defined in the component data sheet · 284 , °C T A +95°C) · Package ­ 284-pin DIMM (halogen-free) · Frequency/CAS latency ­ 0.83ns @ CL = 16 ( DDR4 -2400) ­ 0.93ns @ CL = 15 ( DDR4 -2133) ­ 1.07ns @ CL = 13 ( DDR4 -1866) Marking None Z -2G4 -2G1 -1G9 , without notice. © 2013 Micron Technology, Inc. All rights reserved. 4GB (x72, ECC, SR) 284-Pin DDR4


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PDF 284-Pin MTA9ASF51272AZ 284-pin, PC4-2400, PC4-2133, PC4-1866 512Meg 125mV 09005aef8519d7ca asf9c512x72az DDR4 DDR4 DIMM SPD JEDEC MTA9ASF51272AZ-2G1A1 DDR4 jedec MO-309 micron ddr4 DDR4-2133 MTA9ASF51272AZ-2G4 MT40A512M8 MTA9ASF51272AZ
2012 - Not Available

Abstract:
Text: clock, electrical and timing parameters of the JEDEC JESD794 DDR4 SDRAM Specifications. The application , N6462A DDR4 Compliance Test Application for Infiniium Series Oscilloscopes Data Sheet Introduction The Agilent Technologies N6462A DDR4 compliance test application provides a fast and easy way to test, debug and characterize your DDR4 designs. The tests performed by the N6462A software are based on the JEDEC1 JESD79-4 DDR4 SDRAM Specification. In addition, the application features Custom


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PDF N6462A N6462A JESD79-4 5991-0853EN
2013 - DIMM DDR4 connector

Abstract:
Text: CARD SYSTEMS DDR4 MEMORY MODULE SOCKETS DESCRIPTION Vertical DDR4 DIMM sockets from FCI provide 284 contacts on 0.85mm pitch and are designed to accept DDR4 memory modules that conform to JEDEC , stubbing and supports high-speed serial differential signaling at data rates extending to 6.4 Gb/s for DDR4 , Switches · Routers · Wireless Infrastructure Industrial · Embedded Systems DDR4 MEMORY MODULE SOCKETS , -12-1092 · Packaging specification: GS-14-2267 JEDEC · Module Outline: MO-309 · Socket Outlines: · PTH solder


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PDF MO-309. ELXDDR4MMS0113EA4 DIMM DDR4 connector DDR4 GS-12-1092 DIMM DDR4 socket GS-14-2267 MO-309 DDR4 DIMM socket vertical DDR4 DIMM DDR4 jedec SO-016
2013 - Not Available

Abstract:
Text: operation on DDR4 registered DIMMs with a 1.2 V VDD mode. 1 23 • DDR4RCD01 JEDEC Compliant DDR4 RDIMM and LRDIMM up to DDR4 -2400 32 Bits 1-to-2 Register Outputs 1-to-4 Differential Clock , CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 CAB4A - DDR4 Register 32 , Programmable Latency Output Driver Calibration Address Mirroring and Inversion DDR4 Full-Parity Operation , CMOS drivers optimized to drive 15 to 50 Ω effective terminated traces in DDR4 RDIMM, LRDIMM and


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PDF SNAS630B 32-Bit DDR4RCD01 DDR4-2400
2013 - Not Available

Abstract:
Text: operation on DDR4 registered DIMMs with a 1.2 V VDD mode. 1 23 • DDR4RCD01 JEDEC Compliant DDR4 RDIMM and LRDIMM up to DDR4 -2400 32 Bits 1-to-2 Register Outputs 1-to-4 Differential Clock , CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 CAB4A - DDR4 Register 32 , Programmable Latency Output Driver Calibration Address Mirroring and Inversion DDR4 Full-Parity Operation , CMOS drivers optimized to drive 15 to 50 Ω effective terminated traces in DDR4 RDIMM, LRDIMM and


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PDF SNAS630B 32-Bit DDR4RCD01 DDR4-2400
2013 - DDR4 pcb layout guidelines

Abstract:
Text: high-performance, DDR2, DDR3, and low power DDR4 JEDEC VTT requirements. Advanced circuit techniques and high , is compliant with DDR2/3/QDR and low power DDR4 JEDEC memory termination requirements. The EV1320QI , Required JEDEC Compliant DDR2/3/QDR and Low Power DDR 4 Solution Enable Pin with Output Discharge to , €¢ VTT Bus Termination for DDR2, DDR3, Low Power DDR4 , and QDR Memories Efficiency vs. Output Current , is not to be mechanically or electrically connected to the PCB . Refer to Figure 10 for details


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PDF EV1320QI 16-pin DDR4 pcb layout guidelines
2012 - DDR4 pcb layout guidelines

Abstract:
Text: present and future high-performance, DDR2, DDR3, and low power DDR4 JEDEC VTT requirements. Advanced , ±40mV accuracy and is compliant with DDR2/3/QDR and low power DDR4 JEDEC memory termination requirements , External Inductor Required JEDEC Compliant DDR2/3/QDR and Low Power DDR 4 Solution Enable Pin with Output , Termination for DDR2, DDR3, Low Power DDR4 , and QDR Memories Efficiency vs. Output Current 98 96 94 , connected to the PCB . Refer to Figure 10 for details. NOTE B: White `dot' on top left is pin 1 indicator on


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PDF EV1320QI 16-pin DDR4 pcb layout guidelines DDR4 jedec EV1320 JEDEC DDR4 pcb layout DDR4 "application note" EV1320QI-E
2013 - Not Available

Abstract:
Text: DDR4RCD01 JEDEC Compliant DDR4 RDIMM and LRDIMM up to DDR4 -2400 32 Bits 1-to-2 Register Outputs 1 , CAB4A www.ti.com SNAS630A ­ JULY 2013 ­ REVISED AUGUST 2013 CAB4A - DDR4 Register 32-Bit 1:2 , Driver Programmable Latency Output Driver Calibration Address Mirroring and Inversion DDR4 Full-Parity , for operation on DDR4 registered DIMMs with a 1.2 V VDD mode. All inputs are pseudo-differential using , effective terminated traces in DDR4 RDIMM, LRDIMM and 3DStacked DIMM applications. The clock outputs


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PDF SNAS630A 32-Bit DDR4RCD01 DDR4-2400 16-Logical
2013 - Not Available

Abstract:
Text: operation on DDR4 registered DIMMs with a 1.2 V VDD mode. 1 23 • DDR4RCD01 JEDEC Compliant DDR4 RDIMM and LRDIMM up to DDR4 -2400 32 Bits 1-to-2 Register Outputs 1-to-4 Differential Clock , CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 CAB4A - DDR4 Register 32 , Programmable Latency Output Driver Calibration Address Mirroring and Inversion DDR4 Full-Parity Operation , CMOS drivers optimized to drive 15 to 50 Ω effective terminated traces in DDR4 RDIMM, LRDIMM and


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PDF SNAS630B 32-Bit DDR4RCD01 DDR4-2400
2013 - Not Available

Abstract:
Text: on DDR4 registered DIMMs with a 1.2 V VDD mode. 23 • DDR4RCD01 JEDEC Compliant DDR4 RDIMM and LRDIMM up to DDR4 -2400 32 Bits 1-to-2 Register Outputs 1-to-4 Differential Clock Buffer , © to ground. Do not connect on PCB . Reserved; must be left floating on DIMM and in DDR4 register , CAB4A www.ti.com SNAS630A – JULY 2013 – REVISED AUGUST 2013 CAB4A - DDR4 Register 32 , Programmable Latency Output Driver Calibration Address Mirroring and Inversion DDR4 Full-Parity Operation


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PDF SNAS630A 32-Bit DDR4RCD01 DDR4-2400
JESD209-2E

Abstract:
Text: DDR4 and LPDDR3 Selectable Speed Grades: Support for JEDEC defined speed grades as well as custom , support for multiple memory standards at JEDEC defined speed grades as well as custom speeds. The following Memory standards are supported by DDRA: DDR, DDR2, DDR3, DDR3L, DDR4 Features and Benefits , Verification versus debug DDRA provides a comprehensive set of JEDEC measurements for different memory , not defined by the JEDEC specification using new user specified test limits. Also features like


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PDF MSO5000 MSO70000 DSO/MSO5000, DPO7000 DPO/DSA/MSO70000 5W-22329-8 JESD209-2E MSO UPGRADE PACKAGE
DDR4 DIMM SPD JEDEC

Abstract:
Text: Rev. 1.1, Feb. 2014 K4A4G045WD K4A4G085WD 4Gb D-die DDR4 SDRAM 78FBGA with Lead-Free & , Rev. 1.1 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM Revision History Revision No , Rev. 1.1 DDR4 SDRAM Table Of Contents 4Gb D-die DDR4 SDRAM 1. Ordering Information , .8 5. DDR4 SDRAM Addressing , . 34 11.2 4Gb DDR4 SDRAM D-die IDD Specification Table


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PDF K4A4G045WD K4A4G085WD 78FBGA DDR4 DIMM SPD JEDEC k4a4g085wd SAMSUNG DDR4 SAMSUNG ELECTRONICS ddr4
SAMSUNG ELECTRONICS ddr4

Abstract:
Text: Rev. 0.5, Feb. 2014 K4A4G165WD Preliminary 4Gb D-die DDR4 SDRAM x16 only 96FBGA with , discussion in JEDEC . Therefore, those may be changed without pre-notice based on JEDEC progress. In , K4A4G165WD Rev. 0.5 DDR4 SDRAM Revision History Revision No. 0.5 History Draft Date -2- , Preliminary DDR4 SDRAM Table Of Contents 4Gb D-die DDR4 SDRAM x16 only 1. Ordering Information , .7 5. DDR4 SDRAM Addressing


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PDF K4A4G165WD 96FBGA SAMSUNG ELECTRONICS ddr4
2014 - K4A4G045WD

Abstract:
Text: Rev. 1.21, Jun. 2014 K4A4G045WD K4A4G085WD 4Gb D-die DDR4 SDRAM 78FBGA with Lead-Free & , Rev. 1.21 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM Revision History Revision No , Corrected typo. -2- K4A4G045WD K4A4G085WD datasheet Rev. 1.21 DDR4 SDRAM Table Of Contents 4Gb D-die DDR4 SDRAM 1. Ordering Information , .8 5. DDR4 SDRAM Addressing


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PDF K4A4G045WD K4A4G085WD 78FBGA K4A4G045WD k4a4g085wd SAMSUNG ELECTRONICS ddr4
2014 - k4A4G165

Abstract:
Text: Rev. 0.9, Aug. 2014 K4A4G165WD 4Gb D-die DDR4 SDRAM x16 only 96FBGA with Lead-Free & , Rev. 0.9 datasheet K4A4G165WD DDR4 SDRAM Revision History Revision No. 0.9 History , K4A4G165WD datasheet Rev. 0.9 DDR4 SDRAM Table Of Contents 4Gb D-die DDR4 SDRAM x16 only 1 , .7 5. DDR4 SDRAM Addressing , . 33 11.2 4Gb DDR4 SDRAM D-die IDD Specification Table


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PDF K4A4G165WD 96FBGA k4A4G165 K4A4G165WD-BCRC
2010 - CEL9220HF13

Abstract:
Text: original JEDEC - 3.0 to 3.6V ­ Intel approved ­ SE97B ­ new JEDEC - 3.0 to 3.6V ­ Intel approved Updates ­ JEDEC specification changes · SMBus Timeout 25 ­ 35 ms · Event pin operation deasserted when TS , FEATURES Temp Sensor with integrated new JEDEC compliant SPD (2kbit EEPROM) JEDEC Grade B accuracy ­ ±0.5 , temperature range from ­40 °C to +125 °C 0.3 mm min vs 0.2 mm JEDEC JEDEC compliant package from APB ­ SE97BTP , registers used for TS trim. SPD is disconnected on the TS only version. Sales/Public 6 JEDEC Temp


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PDF SE97BTP PCA9541 CEL9220HF13 DDR4 DIMM SPD JEDEC CEL9220 CEL9220HF CEL-9220HF13 SE97B DDR4 spd DDR4 jedec cel-9220 SE98B
2012 - Micron Technology

Abstract:
Text: . | 5 LPDDRx versus DDRx SDRAM ? • DDRx – often referred to as ( JEDEC ) standard or commodity DRAM or just DRAM (DDR, DDR2, DDR3. etc.) JEDEC standard JESD79E, etc • LPDDRx – Referred to as low power, mobile or wireless DRAM (LPDDR, LPDDR2, LPDDR3). Also defined by JEDEC standard , Feature Comparison Type LPDDR(1) LPDDR2 LPDDR3 DDR2 DDR3/DDR3L DDR4 Die Density , optional feature only full, ¾, half, ¼, 1/8 array, if supported Removed by JEDEC Output Driver


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PDF 20Note/DRAM/TN4102 TN-41-04: TN-41-13: TN-46-02: TN-46-06: TN-46-11: TN-46-14: TN-47-19: TN-47-20: Micron Technology
2013 - H5TAN4G4NMFR

Abstract:
Text: 4Gb DDR4 SDRAM 4Gb DDR4 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TAN4G4NMFR-xx , , H5AN4G8NMFR-xxC and H5AN4G6NMFR-xxC are a 4Gb CMOS Double Data Rate IV ( DDR4 ) Synchronous DRAM, ideally suited , DDR4 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock , supported • CA parity (Command/Address Parity) mode is supported • JEDEC standard 78ball FBGA(x4/x8 , internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n


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PDF 96Ball H5TAN4G4NMFR H5AN4G8N
Supplyframe Tracking Pixel