The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LT6300CGN#TRPBF Linear Technology LT6300 - 500mA, 200MHz xDSL Line Driver in 16-Lead SSOP Package; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LT6300CGN#PBF Linear Technology LT6300 - 500mA, 200MHz xDSL Line Driver in 16-Lead SSOP Package; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
LT6300IGN#TR Linear Technology LT6300 - 500mA, 200MHz xDSL Line Driver in 16-Lead SSOP Package; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
LT6300IGN#PBF Linear Technology LT6300 - 500mA, 200MHz xDSL Line Driver in 16-Lead SSOP Package; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
LT6300IGN#TRPBF Linear Technology LT6300 - 500mA, 200MHz xDSL Line Driver in 16-Lead SSOP Package; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
LT6300CGN Linear Technology LT6300 - 500mA, 200MHz xDSL Line Driver in 16-Lead SSOP Package; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C

J4 Package datasheet (1)

Part Manufacturer Description Type PDF
J4 Package WSI 32-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) Original PDF

J4 Package Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
112KJ4C

Abstract: MPY112K 112kj4 trw mpy 16 MPY112 MPY112KJ4C MPY112KJ4A MPY012H TRW LSI Products 112kj
Text: 22 i I 27 P,e P20 23 [ I 26 P17 P,. 24 I 1 2B P18 48 Lead DIP - J4 Package 30 TRW LSI , for proper operation over the ground lines must be connected. Name Function Value J4 Package Vcc , , respectively. Name Function Value J4 Package *11 X Data MSB TTL Pin 2 X1Q TTL Pin 1 *9 m Pin 48 x8 TTL , .) Name Function Value J4 Package Y11 Y Data MSB TTL Pin 16 *10 TTL Pin 15 TTL Pin 14 y8 TTL Pin , . Name Function Value J4 Package p23 Product MSB TTL Pin 20 P22 TTL Pin 21 P21 TTL Pin 22 p20 TTL


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PDF MPY112K 12x12 MPY112K 20MHz 16-bit 112KJ4A 112KJ4C 112kj4 trw mpy 16 MPY112 MPY112KJ4C MPY112KJ4A MPY012H TRW LSI Products 112kj
TDC1021

Abstract: TDC1028 equivalent tdc 1021 TDC1028J4A TDC1028 TRW LSI Products TDC1028J4C TRW tdc DL021 pipelined adder
Text: 27 DO, Dl2 23 [ 1 26 002 Dh 24 [ 1 25 003 48 Lead DIP - J4 Package 4 TRW LSI Products Inc , supply. All power and ground lines must be connected. Name Function Value J4 Package % Positivs Supply , data, coefficients, and sum (cascadingl inputs. Name Function Value J4 Package 0I3 Signal Data Input , and signal output. Name Function Value J4 Package soI2 Sum Output MSB TTL Pin 34 SO, TTL Pin 35 , the next rising edge of CLK, as shown in Figure 4. Name Function Value J4 Package CLK Clock TTL Pin


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PDF TDC1028 10MHz TDC1028 1028J4A TDC1021 TDC1028 equivalent tdc 1021 TDC1028J4A TRW LSI Products TDC1028J4C TRW tdc DL021 pipelined adder
MPY112K

Abstract: No abstract text available
Text: S . A . MPY112K Functional Block Diagram TPSS Pin Assignments 48 Lead DIP - J4 Package , *11 y 10 TRYw Function Y D ata M S B Value TTL TTL T IL J4 Package Pin 16 Pin 15 Pin 14 , Function Pro d u c t M S B J4 Package Pin 20 Pin 21 Pin 22 Pin 23 Pin 24 Pin 25 Pin 26 Pin 27 Pin 28 P , te r Clock J4 Package Pin 38 Pin 18 Controls The MPY112K has tw o control lines. OE is a th , h re e -S ta te C ontrol J4 Package Pin 1 7 Pin 19 TRW LSI Products Inc. 33 MPY112K


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PDF MPY112K MPY112K 16-bit
A74F283

Abstract: so41 TDC1028 IC MSI ADDER
Text: - J4 Package -4 TRW LSI Products Inc. TDC1028 Functional Description General Information , J4 Package Pin 38 P ins 13,37 Inputs The TDC1028 has three types of inputs: signal data , TTL TTl TTL J4 Package Pm 24 Pin 23 P in 22 Pin 21 Pin 33 Pin 32 Pin 31 Pin 30 Pin 14 Pin 12 P in , Sum Output U S B J4 Package Pin 34 Pin 35 Pin 3« Pin 39 Pin 40 Pin 41 Pin 42 Pin 43 Pin 44 Pin 45 , CLK, as shown in Figure 4. Value TTL Function D o ck J4 Package Pin 20 Controls The


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PDF TDC1028 A74F283 so41 TDC1028 IC MSI ADDER
register file

Abstract: TMC3220 TMC3200 TMC3201 TMC3220J4C TMC3220J4V
Text: Ceramic DIP - J4 Package 46 TRW LSI Products Inc. TMC3220 7V?ff Functional Description General , . TMC3220 7#?fV Package Interconnections Signal Signal Type Name Function J4 Package Power VDD Supply , Consumption CMOS Process • Three-State Outputs • Available In A 48 Pin Hermetic Ceramic DIP Package , Screening Package Package Number Marking TMC3220J4C STD-Ta = 0°C to 70°C Commercial 48 Pin Hermetic


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PDF TMC3220 20MHz TMC3220 20MHz 15MHz Reg883 3220J4V register file TMC3200 TMC3201 TMC3220J4C TMC3220J4V
2002 - CAT16-F4

Abstract: CAY16-J2 CAY16-F4
Text: , J4 ) Package Power Rating Models · J2 = 0606 Package Size · F4, J4 = 1206 Package Size 1 % , (F4, J4 ) Resistance Tolerance J Chip Arrays Resistance Tolerance · J = ±5 % · F = ±1 % (4 resistor package only) +70 °C Resistors · 2 = 2 pcs. · 4 = 4 pcs. Dimensions Model A A' B C D E F CAT16-F4, - J4 0.50±0.15 (.020±.006) - 3.20±0.20 , (.012±.006) CAY16-F4, - J4 0.50±0.15 (.002±.006) 0.65±0.15 (.026±.006) 3.20±0.20 (.126±.008


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PDF CAT16/CAY16 CAT16-F4 CAY16-J2 CAY16-F4
TMC3033

Abstract: TMC3210 b11wa I0000
Text: DIP - J4 Package Functional Description General Information The TMC3210 consists of five sections , output as long as the output buffer is enabled. 62 TRW LSI Products Inc. TMC3210 77KV Package Interconnections Signal Signal Type Name Function J4 Package Power %) Supply Voltage 45, 48 GND Ground 13 , Information Product Temperature Flange Screening Package Package Number Marking TMC3210J4C STD-Ta = 0Â


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PDF TMC3210 32-Bit, TMC3210 32-bit TMC3033 3210J4V b11wa I0000
register file

Abstract: OA71
Text: Ceram ic DIP J4 Package 46 TRW LSI Products Inc. TMC3220 Functional Description General , En a b le B 1B , 44 7 , 29 37 J4 Package Clock inputs O u tp u ts C LK D I7 - 0 0 0 *7 -0 , Package Applications · Cache M e m o ry For High-Speed Processors · Interface For M u ltip le -B u s , Package Interconnections Signal Type Pow er TRY* Signal Name VDD GND Function S u p p ly V olta , 1 y (NOTE 2i RDATA LS P O y M SP2 ^ LS P 2 M SP1 ^ LS p 7 XI Package


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PDF TMC3220 register file OA71
2004 - Not Available

Abstract: No abstract text available
Text: Ultra small MicroPak leadfree package s Ultra low dynamic power Ordering Code: Order Number NC7SP00P5X NC7SP00L6X Package Number MAA05A MAC06A Product Code Top Mark P00 J4 Package Description 5 , www.fairchildsemi.com NC7SP00 Tape and Reel Specification TAPE FORMAT for SC70 Package Designator P5X Tape , Package SC70-5 Tape Size 8 mm DIM A 0.093 (2.35) DIM B 0.096 (2.45) DIM F (3.5 ± 0.10) DIM , www.fairchildsemi.com 6 NC7SP00 Tape and Reel Specification TAPE FORMAT for MicroPak Package Designator L6X


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PDF NC7SP00 NC7SP00,
ic for half subtractor

Abstract: No abstract text available
Text: GND 24 48 Lead DIP - J4 Package Functional Description General Information The TMC3210 , Status Outputs J4 Package 46, 48 13, 23, 24, 44 15, 14, 1 2 -1 , 47, 46 2 5 -4 0 22 20, 19 18, 17 21 , output buffer is enabled. 62 TRW LSI Products Inc. TMC3210 Package Interconnections Signal , °C Screening Commercial MIL-STD-883 Package 48 Pin Hermetic Ceramic DIP 48 Pin Hermetic Ceramic DIP Package M arking 3210J4C 3210J4V All param eters contained in this specification are guaranteed by


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PDF TMC3210 32-Bit, ic for half subtractor
tdc1008

Abstract: 2208R 2208n4c 2208R1C TMC2208N4C TMC2208J4V TMC2208J4C TMC2208 tsx micro MARKING lsi logic
Text: DIP - J4 Package 48 Pin Ceramic DIP - N4 Package 68 Leaded Plastic Chip Carrier - R1 Package , Products Inc. 77 TMC2208 TRYw Package Interconnections Signal Type Signal Name Function J4 , N4 Package Pins R1 Package Pins Power Vdd Supply Voltage 37 18 GND Ground 12 24, 41, 51, 62 Data Input x7-0 X , Compatible With The TDC1008 (Pin Compatible In 48 Pin Dip Package ) • 40ns Multiply-Accumulate Time (Worst , Product Temperature Range Screening Package Package Number Marking TMC2208J4C STD-TA = 0°C to 70Â


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PDF TMC2208 TMC2208 25MHz 16-bit 19-bit 2208R1C tdc1008 2208R 2208n4c 2208R1C TMC2208N4C TMC2208J4V TMC2208J4C tsx micro MARKING lsi logic
P8218

Abstract: TDC1008 LSI 2208
Text: > - > - o >- -U x C 3 U C J Pin Hermetic Ceramic DIP - J4 Package Pm Ceramic DIP - N4 Package Leaded Plastic Chip Carrier - R1 Package Functional Description General Information The TM C2208 , Product Output Data 37 12 J4 , N4 Package Pins 18 R1 Package Pins 24, 41, 51, 62 5, 4, 3, 2, 1 , Features · Function Compatible W ith The TDC1008 (Pin Compatible In 48 Pin Dip Package ) · FFT , buffers T R W LSI Products Inc. 77 TMC2208 Package Interconnections Signal Type Power 7 7


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PDF TMC2208 19-Bit 25MHz P8218 TDC1008 LSI 2208
FPM RAM

Abstract: No abstract text available
Text: 400mil 28L Parts Numbers (Top Mark) Definition : GLT 4 41 08 - 40 J4 PACKAGE -SRAM CONFIG , Information Part Number SPEED POWER FEATURE PACKAGE GLT44108-40J4 GLT44108-50J4 GLT44108 , )* 35 : 35ns J3 : 300mil SOJ 12 : 1M(H/EDO)* 40 : 40ns J4 : 400mil SOJ 13 : 1M(H/FPM)* 45 : 45ns , Note : CÙCDROM , HÙHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil) Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil) Package type. 4 : DRAM 6 : Standard SRAM 7


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PDF GLT44108 GLT44108 512-cycle Current-150mA Curren16-40J4 256Kx16 400mil FPM RAM
TDC1028

Abstract: No abstract text available
Text: 25 48 Lead DIP - J4 Package 4 TRW LSI Products Inc. TDC1028 Functional Description , Ceram ic DIP Package · R adiation Hard Bipolar Process · Single + 5 V P o w e r Supply · TTL C om , Package Pin 38 Pins 13,37 vcc GND Inputs The TDC1028 has three types of inputs: signal data , MSB TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Cascading Sum Input LSB TTL J 4 Package Pin 24 , MSB TTL TTL TTL TTL Data Output LSB TTL J 4 Package Pin 34 Pin 35 Pin 38 Pin 39 Pin 40 Pin 41 Pin 42


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PDF TDC1028 TDC1028
2011 - MT48LC16M16A2P75

Abstract: MT48LC16M16A2P-75
Text: functionality. Store unused EVAL-SDP-CB1Z boards in the protective shipping package . CONTENTS PREFACE , . -vii GETTING STARTED Package Contents , €¢ Core performance up to 600 MHz • 208 -ball CSP-BGA package • 24 MHz CLKIN oscillator • 5 Mb of , board package . iv SDP User Guide Preface Intended Audience The primary audience for this , €¢ “Powering Up/Down the SDP” Package Contents Your EVAL-SDP-CB1Z board package contains the following


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PDF J4-45 PH15/COL J4-76 J4-47 J4-74 J4-48 J4-73 J4-49 J4-72 J4-70 MT48LC16M16A2P75 MT48LC16M16A2P-75
2011 - gg150

Abstract: KF301 JE201 SST-50-WWRM gf700 GL-400 GJ401 GH350 HE100 GU-45
Text: and subsequently grouped into flux and wavelength or chromaticity bins. Each individual package or , with their respective bin as outlined in the following pages. Each package or reel will only contain , Color F67 Package Configuration GH Flux Bin I8 Wavelength/ Chromaticity Bin Product Family Chip Area Color Package Config Flux Bin Wavelength/ Chromaticity Bin A - Package type. "C" , (high) denotes a typical color rendering of 92. Not applicable for monochrome parts F 6 7 - Package


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PDF CBT-40, CBT-120, SST-50 CST-90 CBM-360 CSM-360 gg150 KF301 JE201 SST-50-WWRM gf700 GL-400 GJ401 GH350 HE100 GU-45
transistor j307

Abstract: j352 sk063
Text: ) Gain (dB) (dBm) (W) D (%) AM/PM () 1.64 - j4 .15 19.7 51.8 152 57.3 -10 1.62 - j4 .36 19.6 51.8 152 57.2 -10 1.58 - j4 .51 19.5 51.8 151 , - j4 .42 17.4 52.6 183 58.2 -16 1840 1.37 - j3.43 1.29 + j3.76 1.54 - j4 .59 17.3 52.6 182 57.8 -16 1880 1.67 - j3.79 1.66 + j4 .07 1.57 - j4 .80 17.3 , optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package


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PDF AFT18H357--24S AFT18H357-24SR6 transistor j307 j352 sk063
2014 - Not Available

Abstract: No abstract text available
Text: : Exposed backside of the package is the source terminal for the transistors. Figure 1. Pin Connections , Methodology Per JESD22-A113, IPC/JEDEC J-STD-020 Rating Package Peak Temperature Unit 3 260 , .41 940 2.54 – j4 .03 2.49 + j3.84 960 2.90 – j4 .64 2.76 + j4 .31 Zload () (1 , 2.54 – j4 .03 2.45 + j4 .12 2.04 – j0.03 19.2 54.8 299 60.8 –18 960 2.90 – j4 .64 2.74 + j4 .63 1.97 – j0.01 19.1 54.8 300 60.6 –19 Gain (dB


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PDF MMRF1020--04N MMRF1020-04NR3 MMRF1020-04GNR3
2014 - AFV09P350-04NR3

Abstract: No abstract text available
Text: backside of the package is the source terminal for the transistors. Figure 1. Pin Connections ï , Methodology Per JESD22-A113, IPC/JEDEC J-STD-020 Rating Package Peak Temperature Unit 3 260 , 2.39 – j3.65 2.32 + j3.41 940 2.54 – j4 .03 2.49 + j3.84 960 2.90 – j4 .64 2.76 + j4 .31 Zload () (1) Gain (dB) (dBm) (W) D (%) AM/PM () 1.84 + , 54.8 301 61.1 –19 940 2.54 – j4 .03 2.45 + j4 .12 2.04 – j0.03 19.2 54.8


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PDF AFV09P350--04N AFV09P350-04NR3 AFV09P350-04GNR3
2014 - Not Available

Abstract: No abstract text available
Text: backside of the package is the source terminal for the transistors. Figure 1. Pin Connections ï , Methodology Per JESD22-A113, IPC/JEDEC J-STD-020 Rating Package Peak Temperature Unit 3 260 , 2.39 – j3.65 2.32 + j3.41 940 2.54 – j4 .03 2.49 + j3.84 960 2.90 – j4 .64 2.76 + j4 .31 Zload () (1) Gain (dB) (dBm) (W) D (%) AM/PM () 1.84 + , 54.8 301 61.1 –19 940 2.54 – j4 .03 2.45 + j4 .12 2.04 – j0.03 19.2 54.8


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PDF AFV09P350--04N AFV09P350-04NR3 AFV09P350-04GNR3
2013 - TRANSISTOR J477

Abstract: TRANSISTOR J477 48 C5750Y5V1H226Z AFT18H35 32E17
Text: Output Power f (MHz) 1805 1840 1880 Zsource () 1.14 - j4 .15 1.14 - j4 .41 1.54 - j4 .56 Zin () 1.12 + j4 .37 1.32 + j4 .55 1.61 + j4 .79 Zload () (1) Max Linear Gain (dB) 18.3 18.4 18.2 P1dB (dBm) 51.8 51.6 , P3dB D (%) 60.0 59.4 58.3 AM/PM () 15 16 15 1.21 - j4 .03 1.24 - j4 .24 1.23 - j4 .39 (1) Load , package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Input Load Pull Tuner and


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PDF AFT18HW355S AFT18HW355SR6 1805-he AFT18HW355S TRANSISTOR J477 TRANSISTOR J477 48 C5750Y5V1H226Z AFT18H35 32E17
2013 - GK102

Abstract: No abstract text available
Text: and subsequently grouped into lux and wavelength or chromaticity bins. Each individual package or , labeled with their respective bin as outlined in the following pages. Each package or reel will only , Family Chip Area Color Package Configuration Flux Bin Chromaticity Bin 1 2 3 - Total , Chromaticity Bin Flux Bin Package Config. Chip Area A - Package type: “S” denotes surface , € denotes prototyping board Color Product Family ABC F 6 7 - Package coniguration (for internal


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PDF SST-50 PDS-001848 GK102
2008 - CAY16-J2

Abstract: No abstract text available
Text: <1> 255 °C +255 °C and +260 °C 225 Packaging Size J2.0606 Package Size 220 °C Temperature (°C) 190 °C 175 150 °C 60 - 90 seconds Ramp Down 6 °C/second F4, J4 .1206 Package Size F8 .2406 Package Size for CAT16 J8 .2406 Package Size for CAT16; 1506 Package Size for CAY16 , /CAY16 2 (J2), 4 (F4, J4 ), 8 (F8, J8) 62 mW (31 mW for CAY16-J8) ±1 %, ±5 % 10 ohms - 1 megohm 50 V (25 V , ±1 % (4 resistor package and CAT16-F8) Resistors · 2 = 2 Isolated Resistors · 4 = 4 Isolated


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PDF CAT16-F8, CAY16-J8) CAY16-J2
2013 - GK102

Abstract: No abstract text available
Text: and wavelength or chromaticity bins. Each individual package or reel of parts contains only one , labeled with their respective bin as outlined in the following pages. Each package or reel will only , E Color F 6 7 Package Configuration G H Flux Bin I8 Chromaticity , ) denotes a typical CRI of 83 Chromaticity Bin Flux Bin Package Config. Chip Area A - Package type: “S” denotes surface mount B - Lens type: “S” denotes dome C - Chip quantity: “Tâ


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PDF SST-50 PDS-001848 GK102
2013 - TRANSISTOR J477

Abstract: TRANSISTOR J477 48 AFT18HW355S C5750Y5V1H226Z
Text: Output Power f (MHz) 1805 1840 1880 Zsource () 1.14 - j4 .15 1.14 - j4 .41 1.54 - j4 .56 Zin () 1.12 + j4 .37 1.32 + j4 .55 1.61 + j4 .79 Zload () (1) Max Linear Gain (dB) 18.3 18.4 18.2 P1dB (dBm) 51.8 51.6 , P3dB D (%) 60.0 59.4 58.3 AM/PM () 15 16 15 1.21 - j4 .03 1.24 - j4 .24 1.23 - j4 .39 (1) Load , package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Input Load Pull Tuner and


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PDF AFT18HW355S AFT18HW355SR6 1805-he AFT18HW355S TRANSISTOR J477 TRANSISTOR J477 48 C5750Y5V1H226Z
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