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LT1015MJ8/883B Linear Technology IC DUAL LINE RECEIVER, CDIP8, CERDIP-8, Line Driver or Receiver
LT1015CN8#PBF Linear Technology IC LINE RECEIVER, PDIP8, PLASTIC, DIP-8, Line Driver or Receiver
LT1015CJ8 Linear Technology IC LINE RECEIVER, CDIP8, 0.300 INCH, CERAMIC, DIP-8, Line Driver or Receiver
LT1015CN8 Linear Technology IC LINE RECEIVER, PDIP8, 0.300 INCH, PLASTIC, DIP-8, Line Driver or Receiver
LT1015MJ8 Linear Technology IC LINE RECEIVER, CDIP8, 0.300 INCH, CERAMIC, DIP-8, Line Driver or Receiver
LT1081MJ/883B Linear Technology IC LINE TRANSCEIVER, CDIP16, CERDIP-16, Line Driver or Receiver

In a receiver 50 to 500khz is received play back Datasheets Context Search

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2002 - jammer circuit

Abstract:
Text: received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a , value is constant. This allows clock recovery from the data stream itself. In order to achieve a , receiver is continuously Sleep/Run cycling, the ID word has to be recognized to stay in Run mode , set to a high level, if Data Manager is enabled (DME=1), ROMEO2 becomes master and sends received , The combination MG=1, MS=1 is forbidden in any application. It configures the receiver in a test mode


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PDF MC33593/D MC33593 868MHz, 902-928MHz -105dBm 660kHz 500kHz jammer circuit "data comparator" AEC-Q100-002 MC33593 MC33593FTA
2001 - crystal 315mhz

Abstract:
Text: the received data. If the SPI is not used, a Power On Reset (POR) sets Romeo2 to operate correctly in , controlled with a PLL referenced to the crystal oscillator. The received channel is defined by the choice of , If the receiver is continuously Sleep/Run cycling, the ID word has to be recognized to stay in Run , only The combination MG=1, MS=1 is forbidden in any application. It configures the receiver in a , that before the circuit is in sleep mode, a delay corresponding to the crystal oscillator wake-up time


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PDF MC33591/D MC33591/2 315MHz, 434MHz -105dBm 660kHz 300kHz 500kHz 11kBd MC33591/D crystal 315mhz 35KHz bandwidth 434mhz fm transmitter and receiver jammer 315mhz circuit diagram us SOE00 uhf receiver
2002 - jammer 315mhz circuit diagram us

Abstract:
Text: PROTOCOL If the receiver is continuously Sleep/Run cycling, the ID word has to be recognized to stay in , and check ROMEO2 configuration, - ROMEO2 to send the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a default configuration. The master clock is , The combination MG=1, MS=1 is forbidden in any application. It configures the receiver in a test mode , that before the circuit is in sleep mode, a delay corresponding to the crystal oscillator wake-up time


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PDF MC33594/D MC33594 315MHz, 434MHz -105dBm 660kHz 500kHz jammer 315mhz circuit diagram us jammer uhf jammer 434mhz fm transmitter and receiver if amplifier with band pass filter 500khz AEC-Q100-002 jammer circuit MC33594 MC33594FTA motorola crystal oscillator
2001 - AEC-Q100-002

Abstract:
Text: the receiver is continuously Sleep/Run cycling, the ID word has to be recognized to stay in Run mode , ROMEO2 to send the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a default configuration. The master clock is used to synchronise data movement both in and , × Ts (+ time needed to shift out a full byte if STROBE pin is forced to low when in state 10). , MC33593FTA 868MHz / 500kHz -40°C to +85°C LQFP24 This document contains information on a new


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PDF MC33593/D MC33593 868MHz, 902-928MHz -105dBm 660kHz 500kHz AEC-Q100-002 MC33593 MC33593FTA
2002 - 40khz crystal oscillator datasheet

Abstract:
Text: PROTOCOL If the receiver is continuously Sleep/Run cycling, the ID word has to be recognized to stay in , ROMEO2 configuration, - ROMEO2 to send the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a default configuration. The interface is operated by the 3 , and configuration registers' content is set to the reset value. This enables to use ROMEO2 in a , SOE=0 sets ROMEO2 to state 6. The circuit is in Sleep mode. State 7: A high level applied on STROBE


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PDF MC33591/D 315MHz, 434MHz -105dBm 660kHz 500kHz 40khz crystal oscillator datasheet jammer 315mhz circuit diagram us RF transmitter dr1 jammer circuit diagram jammer 434MHZ transmitter AEC-Q100-002 jammer circuit 40khz crystal oscillator MC33591
UM9092A

Abstract:
Text: bit corresponds to a bit in the Interrupt Status Register (ISR). If an interrupt mask bit is set, an , a packet reception, and is used to restore DMA pointers in the event of receive errors. This , pull-low resistor on each pin, and a 10K pull-high resistor can be connected to a pin when it is switched , 54 outputs 312.5KHz * SLOT SELECTION: When this pin is pulled to high, the DM9008 is in NE2000 16 , Receive Input. A differential receiver tie to the receive transformer pair of the twisted-pair wire. The


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PDF DM9008 DM9008 10BASE5 10BASE2 10BASE-T NE2000 NE2000 DM9008-DS-F02 UM9092A memory card reader ckt diagram UM9092 ALL IN ONE memory card reader ckt diagram sd memory card reader ckt diagram simple vu audio meter dm9008-ds ISA BUS spec Da42 ic switch
UM9092A

Abstract:
Text: corresponds to a bit in the Interrupt Status Register (ISR). If an interrupt mask bit is set, an interrupt , to set in the multicast registers. If an address is found to hash to the value 50 (32H), then FB50 , a packet reception, and is used to restore DMA pointers in the event of receive errors. This , in Remote DMA This pin is not used if the value of biteA of CRB is 0, and tie to high to prevent , pull-low resistor on each pin, and a 10K pull-high resistor can be connected to a pin when it is switched


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PDF DM9008 DM9008 10BASE5 10BASE2 10BASE-T NE2000 NE2000 DM9008-DS-F02 UM9092A UM9092 memory card reader ckt diagram sd memory card reader ckt diagram ALL IN ONE memory card reader ckt diagram UM909 contoller circuit diagram of wire less remot control system aui isolation transformer
memory card reader ckt diagram

Abstract:
Text: bit corresponds to a bit in the Interrupt Status Register (ISR). If an interrupt mask bit is set, an , to set in the multicast registers. If an address is found to hash to the value 50 (32H), then FB50 , a packet reception, and is used to restore DMA pointers in the event of receive errors. This , pull-low resistor on each pin, and a 10K pull-high resistor can be connected to a pin when it is switched , 54 outputs 312.5KHz * SLOT SELECTION: When this pin is pulled to high, the DM9008 is in NE2000 16


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PDF DM9008 DM9008 10BASE5 10BASE2 10BASE-T NE2000 NE2000 CA94085, memory card reader ckt diagram UM9092A UM9092 UM909 sd memory card reader ckt diagram FB0-63 d742 MAR7 a55H
2002 - AEC-Q100-002

Abstract:
Text: local oscillator is controlled with a PLL referenced to the crystal oscillator. The received channel is , value is constant. This allows clock recovery from the data stream itself. In order to achieve a , receiver is continuously Sleep/Run cycling, the ID word has to be recognized to stay in Run mode , and check ROMEO2 configuration, - ROMEO2 to send the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a default configuration. The master clock is


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PDF MC33591/D MC33591/2 MC33591FTA 434MHz 500kHz LQFP24 MC33592FTA 300kHz AEC-Q100-002 jammer circuit diagram MC33591 MC33591FTA MC33592 MC33592FTA SOE00
2001 - MC33592FT

Abstract:
Text: is constant. This allows clock recovery from the data stream itself. In order to achieve a correct , configuration, - ROMEO2 to send the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to , only The combination MG=1, MS=1 is forbidden in any application. It configures the receiver in a , is set to the reset value. This enables to use ROMEO2 in a standalone configuration without any , =0 sets ROMEO2 to state 6. The circuit is in Sleep mode. State 7: A high level applied on STROBE sets the


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PDF MC33591/D MC33591/2 315MHz, 434MHz -105dBm 660kHz 300kHz 500kHz 11kBd MC33592FT SOE00
2002 - FM jammer

Abstract:
Text: the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in , that before the circuit is in sleep mode, a delay corresponding to the crystal oscillator wake-up time , =0 sets ROMEO2 to state 6. The circuit is in Sleep mode. State 7: A high level applied on STROBE sets the , referenced to the crystal oscillator. The received channel is defined by the choice of the crystal frequency , accomodate applications where no bus interface is available the circuit defaults at power-on to a standard


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PDF MC33593/D MC33593 868MHz, 902-928MHz -105dBm 660kHz 500kHz 11kBd EAR99 FM jammer ndk vco SOE00 uhf jammer
2002 - Not Available

Abstract:
Text: modulation (MOD=1), clock recovery from the data stream itself is allowed. In order to achieve a correct , configuration, - ROMEO2 to send the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to , combination MG=1, MS=1 is forbidden in any application. It configures the receiver in a test mode where the , Go to : www.freescale.com Non Disclosure Agreement Required In Run mode, the receiver is enabled , referenced to the crystal oscillator. The received channel is defined by the choice of the crystal frequency


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PDF MC33594/D MC33594 315MHz, 434MHz -105dBm 660kHz 500kHz 11kBd EAR99
2002 - AEC-Q100-002

Abstract:
Text: PROTOCOL If the receiver is continuously Sleep/Run cycling, the ID word has to be recognized to stay in , and check ROMEO2 configuration, - ROMEO2 to send the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a default configuration. The master clock is , ' content is set to the reset value. This enables to use ROMEO2 in a standalone configuration without any , : Programming SOE=0 sets ROMEO2 to state 6. The circuit is in Sleep mode. State 7: A high level applied on


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PDF MC33594/D MC33594 MC33594FTA 434MHz 500kHz LQFP24 AEC-Q100-002 MC33594 MC33594FTA
2002 - 868Mhz FSK

Abstract:
Text: . If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a default , set to a high level, if Data Manager is enabled (DME=1), ROMEO2 becomes master and sends received , ' content is set to the reset value. This enables to use ROMEO2 in a standalone configuration without any , : Programming SOE=0 sets ROMEO2 to state 6. The circuit is in Sleep mode. State 7: A high level applied on , is 2 × Ts (+ time needed to shift out a full byte if STROBE pin is forced to low when in state 10).


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PDF MC33593/D MC33593 MC33593FTA 868MHz 500kHz LQFP24 868Mhz FSK AEC-Q100-002 LN-G102 MC33593 MC33593FTA
2002 - Not Available

Abstract:
Text: and check ROMEO2 configuration, - ROMEO2 to send the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a default configuration. The master clock is , €™ content is set to the reset value. This enables to use ROMEO2 in a standalone configuration without any , : Programming SOE=0 sets ROMEO2 to state 6. The circuit is in Sleep mode. State 7: A high level applied on , is 2 à — Ts (+ time needed to shift out a full byte if STROBE pin is forced to low when in state 10).


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PDF MC33594/D MC33594 MC33594FTA 434MHz 500kHz LQFP24
2002 - Not Available

Abstract:
Text: . If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in a default , set to a high level, if Data Manager is enabled (DME=1), ROMEO2 becomes master and sends received , €™ content is set to the reset value. This enables to use ROMEO2 in a standalone configuration without any , : Programming SOE=0 sets ROMEO2 to state 6. The circuit is in Sleep mode. State 7: A high level applied on , is 2 à — Ts (+ time needed to shift out a full byte if STROBE pin is forced to low when in state 10).


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PDF MC33593/D MC33593 MC33593FTA 868MHz 500kHz LQFP24
KD-S707R

Abstract:
Text: a station is received , searching stops. To search stations of lower frequencies. To stop searching before a station is received , press the same button you have pressed for searching. To tune in , . · When a PTY station cannot be tuned in , the previous station is received . · After searching, the , strength is not sufficient for good reception, by referring to the AF list, the receiver searches for a , next track is located and played back . Press 4 briefly, while playing a CD, to go back to the


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PDF KD-SX838R/S737R/S707R KD-SX838R KS-SX838R KD-S737R KS-S737R KD-S707R KS-S707R 1297MNMUIAJES KD-S707R JVC KD-sx838r KSU15K JVC optical pickup u15k JVC PICKUP AUDIO LEVEL INDICATOR KD-SX838R automatic volume loud control KD-S737R
Not Available

Abstract:
Text: signals to interface to external DRAM. The MX802 is a low-power 5-volt CMOS LSI device. It is offered in , output. 10. Passband is reduced to (typically) 2700 Hz when a sample rate of 25 kbps or 50 kbps is used , MX802 may also be used without DRAM (as a “stand alone" CVSD codec), in which case direct access is , condition to the microcontroller by going to logic ⠀œ0." This is a "wire-or able” output, enabling the , Data: This is the C-BUS serial data input from the microcontroller. Data is loaded to this device in 8


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PDF MX802 MX802 -20dB 100S2.
Not Available

Abstract:
Text: . 9. RAS output. 10. Passband is reduced to (typically) 2700 Hz when a sample rate of 25 kb/s or 50 , the necessary address, control and refresh signals to interface to external DRAM. The MX802 is a , indicates an interrupt condition to the microcontroller by going to logic “0.⠀ This is a “wire-or , microcontroller. This pin is an open drain output. It therefore has a low impedance pulldown to logic â , microcontroller. Data is loaded to this device in 8-bit bytes, MSB (bit 7) first, and LSB (bit 0) last


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PDF MX802 -20dB 100S2. MX802
83C795

Abstract:
Text: to 1. 2. The location of a bit is frequently described in this manner . For , arethe locations that data is read from a written to in the I/O p'pe operation. All 8-bt operations , , these arethe loc&ions that data is read from a written to in the I/O p'pe operation. All 8 , In some systems, this b t is wired to a shutdown contrd input f a DC/DC is dated power s uppiy us ed , mode has been added to access the buffer memory. ⠀¢ Auto-configurability logic has been added in


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PDF 83C795 83C795 10BASE-T 83C795, 16-bit
2002 - C2-100pF

Abstract:
Text: the received data. If the SPI is not used, a Power On Reset (POR) sets ROMEO2 to operate correctly in , average value is constant. This allows clock recovery from the data stream itself. In order to achieve a , configuration registers' content is set to the reset value. This enables to use ROMEO2 in a standalone , =0 sets ROMEO2 to state 6. The circuit is in Sleep mode. State 7: A high level applied on STROBE sets the , referenced to the crystal oscillator. The received channel is defined by the choice of the crystal frequency


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PDF MC33591/D 315MHz, 434MHz -105dBm 660kHz 500kHz 11kBd EAR99 C2-100pF jammer 315mhz circuit diagram us
EN14003

Abstract:
Text: unconnected. Network Sync. If ENTECK = 1 in the CGM command, TECK is a 4 kHz output. It will synchronize to , access is an I/O write. Address Enable. This input to the T7901 indicates that a DMA access is in , examples (Figures A -1 and A -2). The ISA-SWAC uses a single 5 V power supply and is available in a 132 , the XCE and RCE bits in the CDM command. When CHI master mode is used, CHICKIN must be con nected to , ENPNP Type* I Name/Function Enable Plug and Play (Active-High). If ENPNP is strapped to Vdd, ISA Plug


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PDF T7901 DS96-043ISDN EN14003 ten pao transformer TN2E-5V
Not Available

Abstract:
Text: unconnected. Network Sync. If ENTECK = 1 in the CGM command, TECK is a 4 kHz output. It will synchronize to , slot is at the input or the output of a pipe, its connectivity to other time slots, where in the , * compatible. ⠖ Can be programmed to resolve up to 15 ms delays in multiple independent B channels. â , application examples (Figures A -1 and A -2). The ISA-SWAC uses a single 5 V power supply and is available in , CHI is in slave mode, C2 is 3-stated. ⠀™ I = input, O = output, B = bidirectional. tC H ID X is


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PDF T7901 SN74LS32) SN74LS04) T7901. theT7901 CY7C199. SN74LS174 GQ23b02
TN2E-5V

Abstract:
Text: . 124 AEN I Address Enable. This input to the T7901 indicates that a DMA access is in progress. The , a pipe, its connectivity to other time slots, where in the serial stream the time slot is located , resources. ⠀” Seven IRQs supported. ⠀” Plug and Play support can be disabled, allowing for use in , resolve up to 15 ms delays in multiple independent B channels. ⠖ Eight programmable I/O (PIO) pins: â , ISA-SWAC uses a single 5 V power supply and is available in a 132-pin JEDEC quad flat pack (BQFP) package


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PDF T7901 15-bit SN74LS32) SN74LS04) T7901. theT7901 CY7C199. SN74LS174 TN2E-5V AROMAT TN2E-5V 2768B ee-19 ever power relay ras 1210 Aromat relay tn2e TDA 2025 TDA 2020 relay ras 1210 specification EN14003
ten pao transformer

Abstract:
Text: . Network Sync. If STECK = 1 in the CGM command, TECK is a 4 kHz output. It will synchronize to the network , is an I/O write. Address Enable. This input to the T7901 indicates that a DMA access is in progress , chip to operate as a multiple channel ISA I/O interface controller. When the network port is configured , , 64, or 128 kbits/s service. The ISA-SWAC uses a single 5 V power supply and is available in a 132 , Divided by 2- MVIP Clock. When the CHI is in master mode, this clock is a divide by two version of


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PDF T7901 DS97-415ISDN DS96-043ISDN AY97-008ISDN) ten pao transformer Lucent Technologies Microelectronics video codecs
Supplyframe Tracking Pixel