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INCR16 Datasheets Context Search

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2010 - MCIMX28

Abstract: MCIMX287CVM4B I.MX28 MCIMX281AVM4B imx28 USB to ethernet INCR16 M06Z ENGR119653 063ac kob628
Text: fix scheduled ENGR119650 USB: USB core INCR8 and INCR16 modes are inoperable No fix scheduled , Semiconductor ENGR119650 ENGR119650 USB: USB core INCR8 and INCR16 modes are inoperable Description: The USB controller may not operate properly when receiving a packet in INCR8 and INCR16 modes. The , Bulk OUT) 2. Primary INCR8/ INCR16 mode is selected (SBUSCFG. AHBBRST of the USB register is set to , 32n + 16 bytes in INCR8 mode, or 64n + 16/32/48 in INCR16 mode, this errata is triggered. Projected


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PDF IMX28CE ENGR119940 MCIMX28 MCIMX283DVM4B MCIMX283CVM4B MCIMX287CVM4B I.MX28 MCIMX281AVM4B imx28 USB to ethernet INCR16 M06Z ENGR119653 063ac kob628
2002 - ahb slave to memory

Abstract: AMBA AHB memory controller ELPIDA 512MB NOR FLASH MT48LC2M32B2-6 ELPIDA DDR User
Text: latency is for the case where one AHB port, in this example AHB port 0 performs INCR16 16-bit wide read transactions. Other AHB ports, in this case AHB port 1 and 2, perform continuos, in page, INCR16 32-bit read , buffered transfer is when a buffered INCR16 16-bit wide burst is being performed and the other AHB ports are performing INCR16 32-bit wide transfers. Table 2-3 shows that the INCR16 16-bit wide read can , 32-bit read from memory and placed in buffer. 16-bit data 2 returned on AHB. Next INCR16


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PDF PL175) 0230D ahb slave to memory AMBA AHB memory controller ELPIDA 512MB NOR FLASH MT48LC2M32B2-6 ELPIDA DDR User
2012 - Freescale i.MX28

Abstract: No abstract text available
Text: fix scheduled ENGR119650 USB: USB core INCR8 and INCR16 modes are inoperable No fix scheduled , USB: USB core INCR8 and INCR16 modes are inoperable Description: The USB controller may not operate properly when receiving a packet in INCR8 and INCR16 modes. The packet is completed correctly , / INCR16 mode is selected (SBUSCFG. AHBBRST of the USB register is set to 0b010 or 0b011) 3. Length of , , or 64n + 16/32/48 in INCR16 mode, this errata is triggered. Projected Impact: This is a low


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PDF IMX28CE ERR002656, ERR002360, TKT131240, TKT140334. ENGR119940 MCIMX28 Freescale i.MX28
2003 - MT46V16M16

Abstract: TIC 122 Transistor datasheet AMBA AHB memory controller K6T8016C3M-70 K6F8008R2M 128Mb DDR SDRAM samsung version 0.3 ELPIDA 512MB NOR FLASH A-20 ARM graphics *48lc16m16a2
Text: No file text available


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PDF GX175) 0277F MT46V16M16 TIC 122 Transistor datasheet AMBA AHB memory controller K6T8016C3M-70 K6F8008R2M 128Mb DDR SDRAM samsung version 0.3 ELPIDA 512MB NOR FLASH A-20 ARM graphics *48lc16m16a2
2002 - 6116 memory

Abstract: infineon sdram 16mx16 MT48LC4M16A2 PL172 R2P1
Text: -bit SDR SDRAM, row open . 6-56 Burst 16 ( INCR16 ) 32-bit read from 32-bit SDR SDRAM, row open . 6-57 Burst 16 ( INCR16 /WRAP16) 32-bit write to 32-bit SDR SDRAM, row open , Burst 8 (INCRA8/WRAP8) 32-bit write to 32-bit SDR SDRAM memory, row open 6-56 Burst 16 ( INCR16 ) 32-bit read from 32-bit SDR SDRAM, row open . 6-58 Burst 16 ( INCR16 /WRAP16) 32-bit write


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PDF PL172) 0215B 6116 memory infineon sdram 16mx16 MT48LC4M16A2 PL172 R2P1
2003 - ELPIDA 512MB NOR FLASH

Abstract: MT46V16M16 TIC 122 Transistor datasheet 128M DDR SDR SDRAM samsung 0 Micron MT48LC4M16A2 MT28S4M16 PL176 MT48LC4M16A2 MT46V8M16 micron NAND FLASH INTERCONNECT
Text: No file text available


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PDF PL176) ELPIDA 512MB NOR FLASH MT46V16M16 TIC 122 Transistor datasheet 128M DDR SDR SDRAM samsung 0 Micron MT48LC4M16A2 MT28S4M16 PL176 MT48LC4M16A2 MT46V8M16 micron NAND FLASH INTERCONNECT
2003 - MBX R-S

Abstract: MT46V16M16 Graphics Core Technical Reference AMBA AHB memory controller mbx 226 MT48LC2M32B2-6 K9F5608U08-Y K9F5608U08
Text: No file text available


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PDF GX176) 0278B MBX R-S MT46V16M16 Graphics Core Technical Reference AMBA AHB memory controller mbx 226 MT48LC2M32B2-6 K9F5608U08-Y K9F5608U08
2002 - BUT12

Abstract: C-16 MT46V8M16 MT48LC4M16A2 25L128160
Text: Burst 8 (INCR8/WRAP8) 32-bit write to 32-bit SDR SDRAM, row open . 6-28 Burst 16 ( INCR16 /WRAP16) 32-bit read from 32-bit SDR SDRAM, row open . 6-30 Burst 16 ( INCR16 /WRAP16) 32-bit write , 8 (INCRA8/WRAP8) 32-bit write to 32-bit SDR SDRAM memory, row open 6-29 Burst 16 ( INCR16 /WRAP16) 32-bit read from 32-bit SDR SDRAM, row open . 6-31 Burst 16 ( INCR16 /WRAP16) 32-bit write to 32-bit SDR


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PDF PL175) BUT12 C-16 MT46V8M16 MT48LC4M16A2 25L128160
2001 - B8001000

Abstract: B8003 LSI ASIC ML670000 ARM7TDMI C80000 NBS Design
Text: Available INCR WRAP4 INCR4 WRAP8 INCR8 WRAP16 INCR16 SINGLE Possible Possible Possible , INCR4 WRAP8 INCR8 WRAP16 INCR16 SINGLE Possible Available Possible Possible Possible , INCR WRAP4 INCR4 WRAP8 INCR8 WRAP16 INCR16 Possible Possible Available Possible


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2009 - CH7301C

Abstract: 2.4 lcd qvga 320x240 24bit rgb input to ccir656 Xilinx lcd display controller dac xilinx spartan rgb TO HDMI convert chip RGB24 ADV7120 Sitronix ST7787 virtex 5 lcd display controller
Text: the following transfer types: SINGLE, INCR, or INCR16. AHB Slave Bidirectional AHB Slave Interface


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PDF 320x240) 1920x1200) 15-bit 24-bit 24-bit RGB24 ADV7120 80MHz CH7301C CH7301C 2.4 lcd qvga 320x240 24bit rgb input to ccir656 Xilinx lcd display controller dac xilinx spartan rgb TO HDMI convert chip ADV7120 Sitronix ST7787 virtex 5 lcd display controller
2009 - tsmc cmos 0.13 um

Abstract: cmos tsmc 0.18 CH7301C TSMC 0.18 um CMOS ahb slave RTL RGB24 CCIR-656 ADV7120 tsmc cmos tsmc 0.18
Text: the following transfer types: SINGLE, INCR, or INCR16. AHB Slave Bidirectional AHB Slave Interface


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PDF 320x240) 1920x1200) 15-bit 24-bit 24-bit RGB24 ADV7120 80MHz CH7301C tsmc cmos 0.13 um cmos tsmc 0.18 CH7301C TSMC 0.18 um CMOS ahb slave RTL CCIR-656 ADV7120 tsmc cmos tsmc 0.18
Toshiba MeP

Abstract: hmtr HM-TR INCR DSAE002317 001227DAA1 3b110
Text: INCR3'b001 WRAP43'b010 INCR43'b011 WRAP83'b100 INCR83'b101 WRAP163'b110 INCR163'b111 OKAY2'b00 , INCR3'b001 WRAP43'b010 INCR43'b011 WRAP83'b100 INCR83'b101 WRAP163'b110 INCR163'b111 OKAY2'b00 , 'b110:WRAP16 3'b111: INCR16 0 HMWrite HMSize output HSIZE[2:0] HMBurst C [2:0] [2 , 'b111: INCR16 C HSWData [63:0] input HWDATA[63:0] [31:0] O O HSSel C HSRData , ,9,10,11,12,13,14,15 INCR 3 4 INCR4 4 8 INCR8 5 16 INCR16 6 17 1 1 (3) AHB


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PDF MEPUM03018-J14 001227DAA1 Toshiba MeP hmtr HM-TR INCR DSAE002317 001227DAA1 3b110
2009 - CH7301C

Abstract: Sitronix ST7787 ST7787 ST7787 Application Notes Chrontel video to vga converter rgb TO HDMI convert chip graphic lcd module 320x240 RGB24 graphic lcd panel fpga example
Text: the following transfer types: SINGLE, INCR, or INCR16. AHB Slave Bidirectional AHB Slave Interface


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PDF 320x240) 1920x1200) 15-bit 24-bit 24-bit RGB24 ADV7120 80MHz CH7301C CH7301C Sitronix ST7787 ST7787 ST7787 Application Notes Chrontel video to vga converter rgb TO HDMI convert chip graphic lcd module 320x240 graphic lcd panel fpga example
2009 - 2.4 lcd qvga 320x240

Abstract: rgb TO HDMI convert chip RGB HDMI convert 1920x1200 Analog DAC graphic lcd panel fpga example ad9889b HSYNC GENERATE PIXEL CLOCK CH7301C RGB24 CCIR-656
Text: transfer types: SINGLE, INCR, or INCR16. AHB Slave Bidirectional AHB Slave Interface for the CONTROL


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PDF 320x240) 1920x1200) 15-bit 24-bit 24-bit RGB24 ADV7120 80MHz CH7301C 2.4 lcd qvga 320x240 rgb TO HDMI convert chip RGB HDMI convert 1920x1200 Analog DAC graphic lcd panel fpga example ad9889b HSYNC GENERATE PIXEL CLOCK CH7301C CCIR-656
2009 - IMX25RMAD

Abstract: ic 4017 pin configuration internal structure of ic 4017 MX25 4017 timer ic MA10 internal diagram of ic 4017 i.MX25 BLOCK DIAGRAM of IC 4017 WITH 16 PINS freescale arm processor I.MX25
Text: INCR4, INCR8 and INCR16 by setting the DMA_BURST_TYPE_RFF bits in the CSICR2 register. After all data , . The burst type for the transfer can be INCR4, INCR8 and INCR16 by setting the DMA_BURST_TYPE_SFF , of DMA transfer from RxFIFO. 00 INCR8 01 INCR4 10 INCR8 11 INCR16 Note: The optimal setting is , INCR8 01 INCR4 10 INCR8 11 INCR16 Note: The optimal setting is INCR8 so that the CSI burst size


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PDF IMX25RMAD IMX25RMAD ic 4017 pin configuration internal structure of ic 4017 MX25 4017 timer ic MA10 internal diagram of ic 4017 i.MX25 BLOCK DIAGRAM of IC 4017 WITH 16 PINS freescale arm processor I.MX25
2009 - rgb TO HDMI convert chip

Abstract: AD9889B CH7301C graphic lcd panel fpga example graphic lcd module 320x240 YCbCr TO TFT converter EP3C40-6 RGB24 ADV7120 1920x1200 Analog DAC
Text: . The AHB Master can initiate only one of the following transfer types: SINGLE, INCR, or INCR16. AHB


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PDF 320x240) 1920x1200) 15-bit 24bit 24-bit RGB24 ADV7120 80MHz CH7301C rgb TO HDMI convert chip AD9889B CH7301C graphic lcd panel fpga example graphic lcd module 320x240 YCbCr TO TFT converter EP3C40-6 ADV7120 1920x1200 Analog DAC
2001 - ahb arbiter

Abstract: AMBA AHB bus arbiter
Text: performing a fixed length burst (WRAP4, INCR4, WRAP8, INCR8, WRAP16, or INCR16 ), the master can lower its


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PDF
2002 - MTSC2568-12

Abstract: MT48LC2M32B2-6 PL172 16 bit register VERILOG HM5257805B-A6 MT48LC1M16A1S static memory controller PAGE Memory Management Unit K3P9V100M-YC ELPIDA 512MB NOR FLASH
Text: No file text available


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PDF PL172) 0215E MTSC2568-12 MT48LC2M32B2-6 PL172 16 bit register VERILOG HM5257805B-A6 MT48LC1M16A1S static memory controller PAGE Memory Management Unit K3P9V100M-YC ELPIDA 512MB NOR FLASH
2011 - XC6SLX150T-FGG900-3

Abstract: Xilinx ISE Design Suite 14.2 state machine axi 3 protocol state machine diagram for axi bridge XC6SLX150T-FGG900 AMBA AHB to AXI XC6SL ahb to axi axi bridge
Text: INCR16 Notes: 1. Infinite length of INCR transfers from the AHB Lite interface are initiated as INCR , transfer of length 15 on AXI side. INCR16 transfer on AHB is converted to INCR transfer of length 15 on AXI


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PDF DS825 ZynqTM-7000 XC6SLX150T-FGG900-3 Xilinx ISE Design Suite 14.2 state machine axi 3 protocol state machine diagram for axi bridge XC6SLX150T-FGG900 AMBA AHB to AXI XC6SL ahb to axi axi bridge
2001 - 017493

Abstract: IHI-0011A 0x78100000 001C 100C DDI-0029E 16651
Text: Meaning SINGLE INCR WRAP4 INCR4 WRAP8 INCR8 WRAP16 INCR16 High-performance BURST type , . For INCR16 transfers, the XMC makes the 9th data beat wait. Operation depends on SDRAM mode register


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PDF 1-800-OKI-6388 017493 IHI-0011A 0x78100000 001C 100C DDI-0029E 16651
2008 - MPC5125

Abstract: 60MHZ MPC5125RM TD5 651
Text: In the system software, set the USB SBUSCFG register to INCR4/INCR8/ INCR16 (0x01/0x02/0x03) to avoid


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PDF MSE5125 0M01S MPC5125 0M01S) 0M01S MPC5125, 0M01S, MPC5125 60MHZ MPC5125RM TD5 651
2005 - IDE Controller

Abstract: QL902M QL92010M
Text: , INCR4, WRAP8, INCR8, WRAP16 or INCR16 ). ahb_sl_burst_start O Indicates that the Fabric slave is


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PDF QL92010M QL92010M QL902M Hz/32-bit 32-bit IDE Controller
2001 - xdbj

Abstract: MeP toshiba soc toshiba Toshiba MeP mep toshiba jtag Toshiba mep jtag
Text: : WRAP8 3 b101: INCR8 3 b110: WRAP16 3 b111: INCR16 HBURST[2:0] 0 C dbHMWData[63:0] or


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PDF MEPUM05011-J12 0x0060 0x0061 xdbj MeP toshiba soc toshiba Toshiba MeP mep toshiba jtag Toshiba mep jtag
2003 - micron emmc 4.4

Abstract: micron emmc micron emmc 4.3 emmc 4.5 ARMv5 ARM1136 ARMv6 Architecture Reference Manual eMMC 4.4 emmc reader ARMv6
Text: No file text available


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PDF 0284G Glossary-10 Glossary-11 Glossary-12 micron emmc 4.4 micron emmc micron emmc 4.3 emmc 4.5 ARMv5 ARM1136 ARMv6 Architecture Reference Manual eMMC 4.4 emmc reader ARMv6
1999 - ARM920T

Abstract: ARM9TDMI LDM bug ARM922T ARM920T instruction mov add
Text: about errata in the EBI. 1.1 Locked 16-Beat Incrementing Bursts A locked INCR16 transfer can


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PDF ARM922T 16-Beat INCR16 ARM920T ARM9TDMI LDM bug ARM920T instruction mov add
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