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IEEE-754 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
56800

Abstract: IEEE-754
Text: User Manual ­ 56800 Family IEEE-754 Compliant Floating-Point Library Section 1. User Guide , . 0.4 Freescale 56800 Family IEEE-754 Compliant Floating-Point Library User Guide 1 User , division the 56800 Family IEEE-754 Compliant Floating-Point Library 2 User Guide RCSL FP 1.0 - Rev , use of the different floating-point features imposed by the IEEE-754 standard [1] is beyond the scope , : 56800 Family IEEE-754 Compliant Floating-Point Library User Guide 3 User Guide ­ SA = 0 -


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PDF IEEE-754 16-bit 32-bit) 56800
ieee754

Abstract: TRW LSI Products IEEE-754 ABMT C3202
Text: Notes IEEE-754 Format. Page J3 TMC3033-1 - Floating-Point ALU 32-Bit 10 8 0.21 0.2 , c C, V c C, A C, A C, V C, V C IEEE-754 Format. J3 TMC3200 TMC32Û1 TMC3202 TMC3210 , -Bit 32-Bit 10 8 16 20 0.16 0.16 0.3 0.3 IEEE-754 w/lnternal Accumulate. IEEE-754 w/Three Port I/O. 8M FLOP, M IL-STD -1750A. 2.5M FLÜP, IEEE-754 Format, J3 J17 J39 J57 hy.es i 2 G u , W 's processors comply with the IEEE 754 standard floating-point arithm etic format. A ddition


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PDF IEEE-754 TMC3200 TMC32 TMC3202 TMC3210 32/34-Bit 32-Bit 32-Bit ieee754 TRW LSI Products ABMT C3202
56800E

Abstract: ieee 754
Text: User Manual ­ 56800E Family IEEE-754 Compliant Floating-Point Library Section 1. User Guide , . 0.4 Freescale 56800E Family IEEE-754 Compliant Floating-Point Library User Guide 1 User , division the 56800E Family IEEE-754 Compliant Floating-Point Library 2 User Guide RCSL FP 1.0 - , use of the different floating-point features imposed by the IEEE-754 standard [1] is beyond the scope , : RCSL FP 1.0 - Rev. 0.4 Freescale 56800E Family IEEE-754 Compliant Floating-Point Library User


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PDF 56800E IEEE-754 56800E 16-bit 32-bit) ieee 754
2008 - IEEE-1754

Abstract: leon3 processor vhdl leon3 vhdl model floatingpoint addition vhdl sparc v8 VHDL code for floating point addition processor control unit vhdl code RTAX2000S-1 RTAX2 RTAX2000S
Text: 2008, Version 1.0.4 GAISLER 4 GRFPU Lite / GRFPU-FT Lite 2 GRFPU Lite - IEEE-754 , as defined in IEEE Standard for Binary Floating-Point Arithmetic ( IEEE-754 ) and SPARC V8 standard , precision format as defined in IEEE-754 standard. Copyright Aeroflex Gaisler AB December 2008 , floating-point unit detects all exceptions defined by the IEEE-754 standard. This includes detection of Invalid , rounding modes defined in the IEEE-754 standard are supported: round-to-nearest, round-to+inf


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PDF IEEE-STD-754 64-bit IEEE-1754 leon3 processor vhdl leon3 vhdl model floatingpoint addition vhdl sparc v8 VHDL code for floating point addition processor control unit vhdl code RTAX2000S-1 RTAX2 RTAX2000S
2008 - AP3E3000-2

Abstract: leon3 vhdl code 64 bit FPU leon3 processor vhdl 4 bit binary multiplier Vhdl code SPARC 7 vhdl code infinity microprocessor RTAX4000S IEEE754 ieee floating point multiplier vhdl
Text: GAISLER 4 GRFPU / GRFPU-FT 2 GRFPU - High-performance IEEE-754 Floating-point unit 2.1 , Standard for Binary Floating-Point Arithmetic ( IEEE-754 ) and the SPARC V8 standard (IEEE-1754). Supported , details about GRFPU's implementation of the IEEE-754 standard including FP formats, operations, opcodes , , "GRFPU - High Performance IEEE-754 Floating-Point Unit" (available at www.gaisler.com). 2.2 , IEEE-754. All operations are summarized in table 2, with their opcodes, operands, results and exception


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PDF IEEE-STD-754 64-bit AP3E3000-2 leon3 vhdl code 64 bit FPU leon3 processor vhdl 4 bit binary multiplier Vhdl code SPARC 7 vhdl code infinity microprocessor RTAX4000S IEEE754 ieee floating point multiplier vhdl
2009 - RT3PE3000L-1

Abstract: ieee floating point multiplier vhdl leon3 RTAX4000S vhdl code 64 bit FPU vhdl code infinity microprocessor IEEE754 vhdl code of floating point unit leon3 processor vhdl rtax4000
Text: 2009, Version 1.0.3 GAISLER 4 GRFPU / GRFPU-FT 2 GRFPU - High-performance IEEE-754 , defined in the IEEE Standard for Binary Floating-Point Arithmetic ( IEEE-754 ) and the SPARC V8 standard , "Functional description" gives details about GRFPU's implementation of the IEEE-754 standard including FP , details refer to the white paper, "GRFPU - High Performance IEEE-754 Floating-Point Unit" (available at , defined in IEEE-754. All operations are summarized in table 3, with their opcodes, operands, results and


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PDF IEEE-STD-754 64-bit RT3PE3000L-1 ieee floating point multiplier vhdl leon3 RTAX4000S vhdl code 64 bit FPU vhdl code infinity microprocessor IEEE754 vhdl code of floating point unit leon3 processor vhdl rtax4000
1995 - 00FF

Abstract: ADSP-2100 IEEE-754 Floating-Point Arithmetic
Text: applications may require the use of IEEE 754 standard floating-point format. Details of the IEEE format can be found in the IEEE-STD- 754 document, 1985. The major ways in which IEEE format differs from two-word , from fixed-point format into floating-point format (both IEEE 754 and two-word) and vice versa. These , from 1.15 fixed-point format into IEEE 754 and two-word floating-point format is discussed in this , be represented in 1.15 fixed-point format can also be represented in IEEE 754 floating-point format


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Not Available

Abstract: No abstract text available
Text: 754 Exception, for details). The TEM field floating-point exception masks are as follows: Bit , . Unlike the IEEE 754 underflow handling, this underflow handling maintains consistency with the overflow , of the NS bit is not the same as the definition given in the SPARC IEEE 754 Implementation , ftt 0 none 1 IEEE_ 754 _exception 2 unfinished_FP op 3 unim plem ented_FP op 4 , Exception (aexc) [Status Field, Readable and Writable] This field accumulates IEEE_ 754 floating-point


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PDF MB86936 IEEE754
1994 - FLO32

Abstract: FPA24 FLO24 FPD32 MLOOP32 integer and floating point numbers NRM32 FPM32 IEEE-754 IEEE754
Text: IEEE 754 Compliant Floating-Point Routines AN575 IEEE 754 Compliant Floating-Point Routines , : eb = e + 2m-1 © 1994 Microchip Technology Inc. DS00575A-page 1 5-11 5 IEEE 754 , Microchip Technology Inc. 5-12 IEEE 754 Compliant Floating-Point Routines The exception flags and , Technology Inc. DS00575A-page 3 5-13 5 IEEE 754 Compliant Floating-Point Routines NORMALIZE , Technology Inc. 5-14 IEEE 754 Compliant Floating-Point Routines APPENDIX A A.3 Floating point


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PDF AN575 PIC16/17 FLO32 FPA24 FLO24 FPD32 MLOOP32 integer and floating point numbers NRM32 FPM32 IEEE-754 IEEE754
1999 - ieee floating point vhdl

Abstract: floating point verilog ieee floating point verilog APEX20K APEX20KC APEX20KE FLEX10KE IEEE-754
Text: DINT2FP Integer to Floating Point Pipelined Converter ver 2.32 OVERVIEW The DINT2FP is the pipelined integer to floating point converter. The input and output numbers format is according to IEEE-754 , Embedded arithmetic coprocessor Data processing & control KEY FEATURES Full IEEE-754 , :0) en rst clk Arguments Checker - performs input data analyze against IEEE-754 number , performs result rounding function, and data alignment to IEEE-754 standard. PERFORMANCE PINS


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PDF IEEE-754 IEEE-754 FLEX10KE APEX20K APEX20KE APEX20KC ieee floating point vhdl floating point verilog ieee floating point verilog APEX20K APEX20KC APEX20KE FLEX10KE
Not Available

Abstract: No abstract text available
Text: Section 10.4.3, IEEE 754 Exception, for details). The TEM field floating-point exception masks are as , ), depending on rounding mode and its sign. Unlike the IE E E 754 underflow handling, this underflow handling , IE E E 754 Implementation Recommendation section of the SPA R C V8 manual.) Bits 21 -20: Reserved , Trap Types, fordetails): ftt T ra p T y p e 0 none 1 IEEE_ 754 _exception 2 , accumulates IEEE_ 754 floating-point exceptions that occur while their traps are disabled using the TEM field


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PDF MB86936 IEEE754
1999 - MUR1 crouzet 88826105

Abstract: PIC 32 bit FP 801 C6201 rts6201
Text: -bit IEEE-754 standard FP format is used: r r r r r r Bit 31 = sign bit (0 = positive, 1 = , ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; IEEE-754 32-bit SP Floating Point input argument 1 " " " " " " " 2 " " " " " output , ; ; ; ; ; ; ; ; ; ; ; ; ; ; program memory ; entry labels ; Fetch Packet boundary IEEE-754 32-bit SP Floating Point input , reserved. Syd Poland 03-23-98 (for TMS320C62xx DSPs) a4 -> a4 IEEE-754 short 32-bit SP Floating , ; program section ; entry labels ; start on fetch packet boundary ; ; ; ; ; ; ; ; input IEEE-754


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PDF SPRA515 TMS320C62xx 32-bit MUR1 crouzet 88826105 PIC 32 bit FP 801 C6201 rts6201
1999 - verilog code for floating point adder

Abstract: vhdl code for floating point adder vhdl code of pipelined adder vhdl code of floating point adder ieee 754 vhdl code of floating point adder ieee floating point verilog digital clock verilog code pipelined adder ARITHMETIC COPROCESSOR vhdl code of floating point unit
Text: Floating Point Pipelined Adder Unit ver 2.31 OVERVIEW The DFPADD uses the pipelined mathematics algorithm to compute sum of two arguments. The input numbers format is according to IEEE-754 standard , processing & control KEY FEATURES Full IEEE-754 compliance Single precision real format , en rst clk Arguments Checker - performs input data analyze against IEEE-754 number standard , result rounding function, data alignment to IEEE-754 standard, and the final flags setting. The


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PDF IEEE-754 IEEE754 verilog code for floating point adder vhdl code for floating point adder vhdl code of pipelined adder vhdl code of floating point adder ieee 754 vhdl code of floating point adder ieee floating point verilog digital clock verilog code pipelined adder ARITHMETIC COPROCESSOR vhdl code of floating point unit
1999 - APEX20K

Abstract: APEX20KC APEX20KE FLEX10KE verilog code for floating point unit vhdl code of floating point unit digital clock vhdl code IEEE-754 digital clock verilog code
Text: IEEE-754 standard. DFPSQRT supports single precision real numbers. SQRT operation can be pipelined up , processing & control KEY FEATURES Full IEEE-754 compliance Single precision real format , ifo en rst clk Arguments Checker - performs input data analyze against IEEE-754 number , performs result rounding function, data alignment to IEEE-754 standard, and the final flags setting


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PDF IEEE-754 APEX20K APEX20KC APEX20KE FLEX10KE verilog code for floating point unit vhdl code of floating point unit digital clock vhdl code digital clock verilog code
1999 - vhdl code of floating point unit

Abstract: No abstract text available
Text: Floating Point Comparator Unit ver 2.07 OVERVIEW The DFPCOMP compares two arguments. The input numbers format is according to IEEE-754 standard. DFPCOMP supports single precision real numbers , appears after 1 clock period latency and next results are available each clock cycle. Full IEEE-754 , changes Delivery the documentation updates Phone & email support KEY FEATURES Full IEEE-754 , ifo Arguments Checker - performs input data analyze against IEEE-754 number standard compliance


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PDF IEEE-754 vhdl code of floating point unit
1999 - vhdl code for floating point multiplier

Abstract: vhdl code complex multiplier ieee floating point multiplier vhdl ieee floating point multiplier verilog floating point verilog vhdl complex multiplier ieee 754 ieee floating point vhdl vhdl code of floating point unit verilog code for floating point unit
Text: and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included , KEY FEATURES Full IEEE-754 compliance Single precision real format support Simple , performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and , alignment to IEEE-754 standard, and the final flags setting. The following table gives a survey about the


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PDF IEEE754 IEEE-754 vhdl code for floating point multiplier vhdl code complex multiplier ieee floating point multiplier vhdl ieee floating point multiplier verilog floating point verilog vhdl complex multiplier ieee 754 ieee floating point vhdl vhdl code of floating point unit verilog code for floating point unit
1999 - vhdl code of floating point adder

Abstract: verilog code for floating point adder ieee 754 vhdl code of floating point adder vhdl code of pipelined adder vhdl code for floating point adder verilog code for floating point unit IEEE754 digital clock vhdl code ieee floating point vhdl IEEE-754
Text: DFPADD Floating Point Pipelined Adder Unit ver 2.50 OVERVIEW The DFPADD uses the pipelined mathematics algorithm to compute sum of two arguments. The input numbers format is according to IEEE-754 , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision , IEEE-754 number standard compliance. The appropriate numbers and information about the input data , . Result Composer - performs result rounding function, data alignment to IEEE-754 standard, and the final


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PDF IEEE-754 IEEE754 vhdl code of floating point adder verilog code for floating point adder ieee 754 vhdl code of floating point adder vhdl code of pipelined adder vhdl code for floating point adder verilog code for floating point unit digital clock vhdl code ieee floating point vhdl
1999 - vhdl code for Clock divider for FPGA

Abstract: verilog code divide floating point verilog verilog code for floating point unit vhdl code of floating point unit IEEE-754 IEEE754 FLEX10KE APEX20KE ARITHMETIC COPROCESSOR
Text: are available each clock cycle. Full IEEE-754 precision and accuracy are included , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision , Checker - performs input data analyze against IEEE-754 number standard compliance. The appropriate , , data alignment to IEEE-754 standard, and the final flags setting. PERFORMANCE The following table


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PDF IEEE754 IEEE-754 IEEE-754 vhdl code for Clock divider for FPGA verilog code divide floating point verilog verilog code for floating point unit vhdl code of floating point unit FLEX10KE APEX20KE ARITHMETIC COPROCESSOR
1999 - k 2996

Abstract: vhdl code of floating point unit example algorithm verilog IEEE754 ieee floating point verilog ieee floating point vhdl vhdl code for Clock divider for FPGA IEEE-754
Text: are available each clock cycle. Full IEEE-754 precision and accuracy are included , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision real , analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the , flags settings. Result Composer - performs result rounding function, data alignment to IEEE-754


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PDF IEEE754 IEEE-754 IEEE-754 k 2996 vhdl code of floating point unit example algorithm verilog ieee floating point verilog ieee floating point vhdl vhdl code for Clock divider for FPGA
1999 - verilog code for floating point unit

Abstract: ieee floating point vhdl vhdl code for digital clock vhdl code of floating point unit ieee floating point verilog
Text: Integer to Floating Point Pipelined Converter ver 2.31 OVERVIEW The DINT2FP is the pipelined integer to floating point converter. The input and output numbers format is according to IEEE-754 , Data processing & control KEY FEATURES Full IEEE-754 compliance Double word integer , clk Arguments Checker - performs input data analyze against IEEE-754 number standard compliance , result rounding function, and data alignment to IEEE-754 standard. PERFORMANCE The following table


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PDF IEEE-754 IEEE-754 verilog code for floating point unit ieee floating point vhdl vhdl code for digital clock vhdl code of floating point unit ieee floating point verilog
1999 - ieee floating point multiplier vhdl

Abstract: ieee floating point multiplier verilog vhdl code for floating point multiplier IEEE-754 IEEE754 FLEX10KE DFPMUL APEX20KE ieee floating point verilog APEX20KC
Text: and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included , Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision , Arguments Checker - performs input data analyze against IEEE-754 number standard compliance. The , function, data alignment to IEEE-754 standard, and the final flags setting. PERFORMANCE The following


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PDF IEEE754 IEEE-754 ieee floating point multiplier vhdl ieee floating point multiplier verilog vhdl code for floating point multiplier FLEX10KE DFPMUL APEX20KE ieee floating point verilog APEX20KC
1999 - example algorithm verilog

Abstract: vhdl code for digital clock
Text: Floating Point Pipelined Square Root Unit ver 2.07 OVERVIEW The DFPSQRT uses the pipelined mathematics algorithm to compute square root function. The input number format is according to IEEE-754 , algorithms KEY FEATURES Full IEEE-754 compliance Single precision real format support , performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and , to IEEE-754 standard, and the final flags setting. PERFORMANCE datao(31:0) ofo ufo ifo en


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PDF IEEE-754 example algorithm verilog vhdl code for digital clock
1999 - verilog code for floating point unit

Abstract: ieee floating point verilog digital clock vhdl code vhdl code of floating point unit floating point verilog
Text: Floating Point To Integer Pipelined Converter ver 2.07 OVERVIEW The DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 , IEEE-754 compliance Single precision real input numbers Double word output numbers(4 , performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and , to IEEE-754 standard, and the final flags setting. SYMBOL datai(31:0) datao(31:0) ofo ufo


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PDF IEEE-754 IEEE-754 verilog code for floating point unit ieee floating point verilog digital clock vhdl code vhdl code of floating point unit floating point verilog
1999 - VHDL code for floating point addition

Abstract: verilog code for floating point division ARITHMETIC COPROCESSOR processor control unit vhdl code vhdl code 8 bit processor test bench for 16 bit shifter verilog code for floating point multiplication DP8051 APEX20KE APEX20KC
Text: change sign of a number. The input numbers format is according to IEEE-754 standard single precision , programming required Configurability of all available functions IEEE-754 Single precision real format , contains exponents and work registers. Align ­ performs the numbers analyze against IEEE-754 standard , 80C51 DP8051 DP8051+DFPAU IEEE-754 FP Instruction Improvement Addition 73 Subtraction 60 , are trademarks of their respective owners. IEEE-754 FP Instruction Improvement Addition 6.4


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PDF DP8051, 32-bit VHDL code for floating point addition verilog code for floating point division ARITHMETIC COPROCESSOR processor control unit vhdl code vhdl code 8 bit processor test bench for 16 bit shifter verilog code for floating point multiplication DP8051 APEX20KE APEX20KC
1999 - verilog code for floating point multiplication

Abstract: vhdl code for cordic cosine and sine verilog code for floating point division VHDL code for floating point addition vhdl code for cordic vhdl code for cordic multiplication program for 8051 16bit square root 8051 16bit addition, subtraction verilog code for single precision floating point multiplication CORDIC sine cosine float altera
Text: to floating point type and vice versa. The input numbers format is according to IEEE-754 standard , compilers: GNU C/C+, 8051 compilers No programming required IEEE-754 Single precision real format , Core performance in ALTERA® devices Device Align ­ performs the numbers analyze against IEEE-754 , (overall) 150 100 50 7,3 1 0 80C51 DP8051 DP8051+DFPMU IEEE-754 FP Instruction , operations All trademarks mentioned in this document are trademarks of their respective owners. IEEE-754


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PDF DP8051, 32-bit verilog code for floating point multiplication vhdl code for cordic cosine and sine verilog code for floating point division VHDL code for floating point addition vhdl code for cordic vhdl code for cordic multiplication program for 8051 16bit square root 8051 16bit addition, subtraction verilog code for single precision floating point multiplication CORDIC sine cosine float altera
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