The Datasheet Archive

ICS97U877 datasheet (10)

Part Manufacturer Description Type PDF
ICS97U877 Integrated Circuit Solution 1.8V Wide Range Frequency Clock Driver Original PDF
ICS97U877AH Integrated Circuit Systems 1.8V Wide Range Frequency Clock Driver Original PDF
ICS97U877AHLF Integrated Circuit Systems 1.8V Wide Range Frequency Clock Driver Original PDF
ICS97U877AHLFT Integrated Circuit Systems Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers, Integrated Circuits (ICs), IC CLK DVR PLL 1:10 370MHZ 52BGA Original PDF
ICS97U877AHT Integrated Circuit Systems Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers, Integrated Circuits (ICs), IC CLK DVR PLL 1:10 370MHZ 52BGA Original PDF
ICS97U877AK Integrated Circuit Systems 1.8V Wide Range Frequency Clock Driver Original PDF
ICS97U877AKLF Integrated Circuit Systems 1.8V Wide Range Frequency Clock Driver Original PDF
ICS97U877AKLFT Integrated Circuit Systems Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers, Integrated Circuits (ICs), IC CLK DVR PLL 1:10 40VFQFN Original PDF
ICS97U877AKT Integrated Circuit Systems Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers, Integrated Circuits (ICs), IC CLK DVR PLL 1:10 40VFQFN Original PDF
ICS97U877yH-T Integrated Circuit Systems 1.8V Wide Range Frequency Clock Driver Original PDF

ICS97U877 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2003 - Not Available

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICS97U877 Advance Information 1.8V Wide Range Frequency , CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ 31 CLKT1 1 30 ICS97U877 10 21 11 20 CLKC7 , CLKC4 CLKT4 VDDQ CLKT9 CLKC9 CLKC8 CLKT8 VDDQ 40-Pin MLF ICS97U877 Advance Information Pin , Differential outputs The PLL clock buffer, ICS97U877 , is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and , . ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten


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PDF ICS97U877 ICSSSTU32864 52-Ball 40-Pin ICS97U877yKT
2003 - Not Available

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICS97U877 Advance Information 1.8V Wide Range Frequency , CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ 31 CLKT1 1 30 ICS97U877 10 21 11 20 CLKC7 , CLKC4 CLKT4 VDDQ CLKT9 CLKC9 CLKC8 CLKT8 VDDQ 40-Pin MLF ICS97U877 Advance Information Pin , Differential outputs The PLL clock buffer, ICS97U877 , is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and , . ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten


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PDF ICS97U877 ICSSSTU32864 52-Ball 40-Pin ICS97U877yKT
2004 - ICS97U877yKLF-T

Abstract: 2506036017Y0 ICS97U877 ICSSSTU32864 MO-205 0792A
Text: Publication 95, MO-205*, MO-225* 10-0055 Ordering Information ICS97U877yHLF-T Example: ICS XXXX , Source Reference: MLF2TM SER 10-0053 Ordering Information ICS97U877yKLF-T Example: ICS XXXX y , ICS97U877 Integrated Circuit Systems, Inc. 1.8V Wide Range Frequency Clock Driver , . CLKT7 ICS97U877 10 21 CLKC7 CLKT8 11 CLKC8 CLKT9 20 CLKC9 FB_OUTT FB_OUTC , VDDQ FB_INT FB_INC FB_OUTC FB_OUTT VDDQ OE OS ICS97U877 Pin Descriptions Te r m i n a l


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PDF ICS97U877 ICSSSTU32864 52-Ball ICS97U877yKLF-T 792A--04/15/04 ICS97U877yKLF-T 2506036017Y0 ICS97U877 ICSSSTU32864 MO-205 0792A
1997 - KMC-3580

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICS97U877 Advance Information 1.8V Wide Range Frequency , CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ 31 CLKT1 1 30 ICS97U877 10 21 11 20 CLKC7 , CLKC4 CLKT4 VDDQ CLKT9 CLKC9 CLKC8 CLKT8 VDDQ 40-Pin MLF ICS97U877 Advance Information Pin , Differential outputs The PLL clock buffer, ICS97U877 , is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and , . ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten


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PDF ICS97U877 ICSSSTU32864 52-Ball TB-0605-05 KMC3580 KMC-3580
2004 - 2506036017Y0

Abstract: ICS97U877 ICSSSTU32864 MO-205
Text: ICS97U877 Integrated Circuit Systems, Inc. 1.8V Wide Range Frequency Clock Driver , . CLKT7 ICS97U877 10 21 CLKC7 CLKT8 11 CLKC8 CLKT9 20 CLKC9 FB_OUTT FB_OUTC , VDDQ FB_INT FB_INC FB_OUTC FB_OUTT VDDQ OE OS ICS97U877 Pin Descriptions Te r m i n a l , outputs NB No ball The PLL clock buffer, ICS97U877 , is designed for a VDDQ of 1.8 V, a AVDD of , and a 40-pin MLF. ICS97U877 is a zero delay buffer that distributes a differential clock input pair


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PDF ICS97U877 ICSSSTU32864 52-Ball 97U877yKLF-T 792A--04/15/04 2506036017Y0 ICS97U877 ICSSSTU32864 MO-205
1997 - Not Available

Abstract: No abstract text available
Text: Ordering Information ICS97U877yKLF-T Example: ICS XXXX y K LF- T Designation for tape and reel , Integrated Circuit Systems, Inc. ICS97U877 1.8V Wide Range Frequency Clock Driver , VDDQ 31 CLKT1 1 30 ICS97U877 10 21 11 20 CLKC7 CLKT7 VDDQ FB_INT FB_INC FB_OUTC , -Pin MLF ICS97U877 Pin Descriptions Te r m i n a l Name AGND AVDD CLK_INT CLK_INC FB_INT FB_INC , Differential outputs Differential outputs The PLL clock buffer, ICS97U877 , is designed for a VDDQ of 1.8 V


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PDF ICS97U877 ICSSSTU32864 52-Ball TB-0605-05 KMC3580
2007 - SPO2

Abstract: 97u877ahlf 2506036017Y0 ICS97U877 ICS97U877AKLF ICSSSTU32864 MO-205
Text: . ICS97U877 is characterized for operation from 0°C to 70°C. 0792-12/18/03 2 ICS97U877AHLF /AKLF , ICS97U877AHLF /AKLF Integrated Circuit Systems, Inc. Advance Information 1.8V Wide Range , CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND 31 30 1 ICS97U877AKLF 10 21 , . ICS97U877AHLF /AKLF Advance Information Pin Descriptions Te r m i n a l Name Electrical Characteristics , Differential outputs NB No ball The PLL clock buffer, ICS97U877 , is designed for a VDDQ of 1.8 V, a


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PDF ICS97U877AHLF/AKLF ICSSSTU32864 40-Pin ICS97U877yKT SPO2 97u877ahlf 2506036017Y0 ICS97U877 ICS97U877AKLF ICSSSTU32864 MO-205
2007 - 2506036017Y0

Abstract: 97U877AHLF ICS97U877 ICS97U877AKLF ICSSSTU32864 MO-205
Text: . ICS97U877 is characterized for operation from 0°C to 70°C. 0792-12/18/03 2 ICS97U877AHLF /AKLF , ICS97U877AHLF /AKLF Integrated Circuit Systems, Inc. Advance Information 1.8V Wide Range , CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND 31 30 1 ICS97U877AKLF 10 21 , . ICS97U877AHLF /AKLF Advance Information Pin Descriptions Te r m i n a l Name Electrical Characteristics , Differential outputs NB No ball The PLL clock buffer, ICS97U877 , is designed for a VDDQ of 1.8 V, a


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PDF ICS97U877AHLF/AKLF ICSSSTU32864 40-Pin 97U877yKT 2506036017Y0 97U877AHLF ICS97U877 ICS97U877AKLF ICSSSTU32864 MO-205
2004 - ICS97U877

Abstract: ICSSSTU32864 Q11A Q13A
Text: ICSSSTU32864 Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM logic solution with ICS97U877 1 2 3 4 5 6 A B C Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on CSR# and RESET# inputs · Low voltage operation VDD =


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PDF ICSSSTU32864 25-Bit ICS97U877 14-bit 10-0055C ICSSSTU32864yHT 0727C--04/15/04 MO-205 ICS97U877 ICSSSTU32864 Q11A Q13A
2004 - ICS97U877

Abstract: Q11A Q13A
Text: ICSSSTUF32864 Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 1 2 3 4 5 6 A B C D Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on CSR


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PDF ICSSSTUF32864 25-Bit ICS97U877 14-bit ICSSSTUF32866 10-0055C ICSSSTUF32864yHT 880A--04/16/04 MO-205 ICS97U877 Q11A Q13A
1997 - BF96

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTUF32864A 25-Bit Configurable Registered Buffer for DDR2 Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on C0, C1 and RESET# inputs · Low voltage operation VDD = 1.7V to 1.9V · Available in 96


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PDF ICSSSTUF32864A 25-Bit ICS97U877 14-bit ICSSSTUF32866 TB-0512-01 KMC3580 BF96
2003 - Not Available

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTU32864 Preliminary Product Preview 25-Bit Configurable Registered Buffer Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM logic solution with ICS97U877 Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on CSR# and RESET# inputs · Low voltage operation VDD = 1.7V to 1.9V · Available in 96 BGA package


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PDF ICSSSTU32864 25-Bit ICS97U877 14-bit 10-0055C MO-205 ICSSSTU32864 0727B--08/27/03
Not Available

Abstract: No abstract text available
Text: ICSSSTUB32864A Integrated Circuit Systems, Inc. Advance Information 25-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533, 667 and 800 1 2 3 4 5 6 A B C D Product Features: • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports


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PDF ICSSSTUB32864A 25-Bit ICS97U877 14-bit ICSSSTUB32866 10-0055C ICSSSTUB32864Az MO-205
2005 - 1055a

Abstract: ICS97U877 ICSSSTUA32864B Q11A Q13A
Text: ICSSSTUA32864B Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 1 2 3 4 5 6 A B C D Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on C0, C1


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PDF ICSSSTUA32864B 25-Bit ICS97U877 14-bit ICSSSTUA32866 10-0055C ICSSSTUA32864Bz 055A--01/28/05 MO-205 1055a ICS97U877 ICSSSTUA32864B Q11A Q13A
1997 - 0727C

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTU32864 25-Bit Configurable Registered Buffer Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM logic solution with ICS97U877 Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on CSR# and RESET# inputs · Low voltage operation VDD = 1.7V to 1.9V · Available in 96 BGA package Pin Configuration 1 A B C D E F G H


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PDF ICSSSTU32864 25-Bit ICS97U877 14-bit BFG96) SSTU32864AHLFT SSTU32864AHT 0727C
2003 - Not Available

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTU32864 Preliminary Product Preview 25-Bit Configurable Registered Buffer Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM logic solution with ICS97U877 Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on CSR# and RESET# inputs · Low voltage operation VDD = 1.7V to 1.9V · Available in 96 BGA package


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PDF ICSSSTU32864 25-Bit ICS97U877 14-bit 10MHz, 727A--07/03/03 ICSSSTU32864y
2004 - Not Available

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTUF32864A 25-Bit Configurable Registered Buffer for DDR2 Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on C0, C1 and RESET# inputs · Low voltage operation VDD = 1.7V to 1.9V · Available in 96


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PDF ICSSSTUF32864A 25-Bit ICS97U877 14-bit ICSSSTUF32866 10-0055C MO-205 ICSSSTUF32864Ay 987A--07/14/04
2005 - ICS97U877

Abstract: ICSSSTUB32864A Q11A Q13A
Text: ICSSSTUB32864A Integrated Circuit Systems, Inc. Advance Information 25-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533, 667 and 800 1 2 3 4 5 6 A B C D Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching


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PDF ICSSSTUB32864A 25-Bit ICS97U877 14-bit ICSSSTUB32866 10-0055C ICSSSTUB32864Az MO-205 ICS97U877 ICSSSTUB32864A Q11A Q13A
2004 - ICS97U877

Abstract: ICSSSTUF32864A Q11A Q13A
Text: ICSSSTUF32864A Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 1 2 3 4 5 6 A B C D Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on C0, C1


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PDF ICSSSTUF32864A 25-Bit ICS97U877 14-bit ICSSSTUF32866 10-0055C ICSSSTUF32864AyHLF-T 0987B--09/28/04 MO-205 ICS97U877 ICSSSTUF32864A Q11A Q13A
2005 - ICS97U877

Abstract: Q11A Q13A SSTU32864
Text: ICSSSTUA32S869A Advance Information Integrated Circuit Systems, Inc. 14-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 1 2 3 4 5 6 7 8 9 10 A B C D Product Features: · 14-bit 1:2 registered buffer with parity check functionality · Supports SSTL_18 JEDEC specification on data inputs and outputs · 50


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PDF ICSSSTUA32S869A 14-Bit ICS97U877 SSTU32864 ICSSSTUA32S869AH ICS97U877 Q11A Q13A SSTU32864
2005 - ICS97U877

Abstract: ICSSSTUA32S865A Q19A BA312
Text: ICSSSTUA32S865A Integrated Circuit Systems, Inc. 28-Bit Registered Buffer for DDR2 Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 1 2 3 4 5 6 7 8 E Product Features: · 28-bit 1:2 registered buffer with parity check functionality · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on CSR# and RESET# inputs ·


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PDF ICSSSTUA32S865A 28-Bit ICS97U877 ICSSSTUA32S865AH 053A--03/21/05 ICS97U877 ICSSSTUA32S865A Q19A BA312
2003 - ICS97U877

Abstract: ICSSSTU32866 Q11A Q13A
Text: ICSSSTU32866 Integrated Circuit Systems, Inc. Advance Information 25-Bit Configurable Registered Buffer Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM logic solution with ICS97U877 1 2 3 4 5 6 A B Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on


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PDF ICSSSTU32866 25-Bit ICS97U877 14-bit 10-0055C ICSSSTU32866yHT MO-205 ICS97U877 ICSSSTU32866 Q11A Q13A
1997 - Not Available

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTUF32864 25-Bit Configurable Registered Buffer for DDR2 Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on CSR# and RESET# inputs · Low voltage operation VDD = 1.7V to 1.9V · Available in 96 BGA package ·


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PDF ICSSSTUF32864 25-Bit ICS97U877 14-bit ICSSSTUF32866 TB-0512-01 KMC3580
1997 - Q13A

Abstract: No abstract text available
Text: Integrated Circuit Systems, Inc. ICSSSTU32866 Advance Information 25-Bit Configurable Registered Buffer Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM logic solution with ICS97U877 Product Features: · 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports LVCMOS switching levels on CSR# and RESET# inputs · Low voltage operation VDD = 1.7V to 1.9V · Available in 96 BGA


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PDF ICSSSTU32866 25-Bit ICS97U877 14-bit TB-0512-01 KMC3580 Q13A
2006 - J2 Q24A B

Abstract: J2 Q15A C Q22A Q15A Q19A ICS97U877 MO-246 capacitor CK-06
Text: ICSSSTUB32S868D Advance Information Integrated Circuit Systems, Inc. 28-Bit Configurable Registered Buffer for DDR2 Pin Configuration Recommended Application: · DDR2 Memory Modules · Provides complete DDR DIMM solution with ICS97U877 · Ideal for DDR2 400, 533 and 667 1 2 3 4 5 6 7 8 A B C D Product Features: · 28-bit 1:2 registered buffer with parity check functionality · Supports SSTL_18 JEDEC specification on data inputs and outputs · Supports


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PDF ICSSSTUB32S868D 28-Bit ICS97U877 MO-205* MO-225* MO-246* ICSSSTUB32S868DH J2 Q24A B J2 Q15A C Q22A Q15A Q19A ICS97U877 MO-246 capacitor CK-06
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