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DC392A-C Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-A Linear Technology LTC1628 or LTC3728 Evaluation Kit
DC392A-B Linear Technology LTC1628 or LTC3728 Evaluation Kit
LT1490AIS8#TRA1PBF Linear Technology Dual and Quad Micropower Rail-to-Rail Input and Output Op Amps
LF198S Linear Technology IC SAMPLE AND HOLD AMPLIFIER, PDSO, Sample and Hold Circuit
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IC of XOR GATE Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Not Available

Abstract: No abstract text available
Text: g ic diagram , one in p u t o f the XOR gate is co nn e cte d to a sin g le p ro d u c t term , w h ile th e second inp u t is connected to the o u tp u t o f th e OR logic array. The XOR gate o u tp u t feeds th e in p u t o f th e D flip -flo p . The w ay in w hich the XOR gate is used to , co nsistin g o f a basic D -typ e flip -flo p driven b y an XOR gate . This allows the user to choose , d m a n ip u la tio n o f th e XOR gate inp u ts and the D flip -flo p output. The tra n sfe r fu


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PDF PAL32VX10 PAL32VX10A PAL32VX10A
CM3000

Abstract: 20XV10B
Text: OUTPUT LOGIC MACROCELLS - XOR Gate C apability on all O utputs - Full Function and Param etric C om , XOR bit controls the polarity of the output. The register is clocked by the lowto-high transition of , common to all XOR macrocells. In Feedback mode, the state of the I/O pin is available to the AND array , combinatorial output The XOR bit con trols the polarity of the output. The inverting output buffer is enabled by , Electronic Signature is always available regardless of the security cell state. D E V IC E P R O G R A M M


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PDF PAL12L10, 20L1d GAL20XV10B CM3000 20XV10B
DM4011

Abstract: "XOR Gate" IC 4011 IC of XOR GATE DATA SHEET IC 4011 DELL power supply diagram Applications of "XOR Gate" 4011 IC data sheet XOR GATE uses differential manchester encoder
Text: 12.5 Gb/sec XOR gate (Preliminary Information) Electrical Characteristics1 2. In the case of , DM4011 12.5 Gb/sec XOR gate (Preliminary Information) Description The DM4011 is a high-speed , +39 (06) 5582904 FAX +39 (06) 5587394 DM4011 12.5 Gb/sec XOR gate (Preliminary Information , (06) 5587394 DM4011 12.5 Gb/sec XOR gate (Preliminary Information) Eye Diagram Performance DM4011 used as XOR gate . 10.709 Gb/s NRZ inputs, 1.8 Vpp differential on DIN1 and DIN2. Power supply


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PDF DM4011 DM4011 50-ohm "XOR Gate" IC 4011 IC of XOR GATE DATA SHEET IC 4011 DELL power supply diagram Applications of "XOR Gate" 4011 IC data sheet XOR GATE uses differential manchester encoder
24v xor IC

Abstract: No abstract text available
Text: Qo GND - GATE ARRAT ( N o te ) F F E A T U R E Cell ;0 R . XOR . POLARITY : F E A , utput > Note ; -777777K D ata unknown ic o mm 1-4 CMOS EPL 2 0 B Configurations of , It EPL 20B SERIES G E N E R A L D ESC RIPTIO N R IC O H E P L 20B Series are Field-programmable , A T IO N 10-INPUT, 8-O UTPUT, AND -OR/ XOR A R R A Y 1 2 -IN PUT, 6 O U T P U T , AND -OR/ XOR A R R A , S-INPUT.S-FEEDBACK.S-OUTPUTS-REGISTERED,AND-OR/ XOR ARRAY 8-INPUT. 6-FEEDBACK, 2-INPUT/OUTPUT. 8-OUTPUT, 6 - REGISTERED. AND-OR/ XOR ARRAY 8


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PDF 16RP8, 16RP6, 16RP4) EPL16P2B EPL16RP4B 20Pin 300mil 24v xor IC
PAL32VX10

Abstract: PAL32VX10C
Text: m acroce ll lo g ic diagram , one in p u t o f the XOR gate is c o n n e cte d to a sing le p ro d u , o n sistin g o f a basic D -typ e flip -flo p drive n b y an XOR gate . This allows the user to , XOR gate o u tp u t feeds th e in p u t o f th e D flip -flo p . The w ay in w hich the XOR g ate is , D flip -flo p o p tio n is im plem ented directly. In this c o n fig u ra tio n , the XOR gate o n , istica te d m a n ip u la tio n o f th e XOR gate inputs and the D flip -flo p outp ut. The tra n sfe r


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PDF 24-pin 300-m PAL32VX10 PAL32VX10C
"XOR Gate"

Abstract: karnaugh map 8 pin dip j k flipflop ic
Text: indicated in the macrocell logic diagram, one input of the XOR gate is connected to a single product term, while the second i nput is connected to the output of the OR logic array. The XOR gate output feeds the input of the D flip-flop. The way in which the XOR gate is used to synthesize the different flip-flop , configuration, the XOR gate on the input o f the flip-flop can be used to program the logic polarity of the , sophisticated manipulation of the XOR gate inputs and the D flip-flop output. The transfer function of a J-K


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PDF 24-pin 300-mil 28-pin PAL22RX8A PAL22RX8A "XOR Gate" karnaugh map 8 pin dip j k flipflop ic
Not Available

Abstract: No abstract text available
Text: Electrical Erasure (<100 ms) - 20 Year Data Retention * TEN OUTPUT LOGIC MACROCELLS - XOR Gate Capability , true. The XOR bit controls the polarity of the output. The register is clocked by the low-to-high , common to all XOR macrocells. In Feedback mode, the state of the I/O pin is available to the AND array , combinatorial output. The XOR bit con trols the polarity of the output. The inverting output buffer is enabled , of SCR induced latching. E L E C T R O N IC S IG N A T U R E An electronic signature word is


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PDF Tested/100% GAL20XV10
Not Available

Abstract: No abstract text available
Text: Retention • TEN OUTPUT LOGIC MACROCELLS — XOR Gate Capability on all Outputs — Full Function , XOR bit controls the polarity of the output. The register is docked by the lowto-high transition of , into two OR-sums of two product terms each, which are then combined by an Exclusive-OR gate and fed to , output enable that is common to aU XOR macrocells. In Feedback mode, the state of the I/O pin is , the combinatorial output The XOR bit con­ trols the polarity of the output The inverting output


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PDF GAL20XV10B
IC of XOR GATE

Abstract: "XOR Gate" PAL22R
Text: flipflop consisting of a basic D-type flip-flop driven by an XOR gate . This allows the user to choose the , of the OR logic array. The XOR gate output feeds the input of the D flip-flop. The way in which the , . The D flip-flop option is implemented directly. In this configuration, the XOR gate on the input of , sophisticated manipulation of the XOR gate inputs and the D flip-flop output. The transfer function of a J-K , ARRAY LOGIC NUMBER OF ARRAY INPUTS OUTPUT TYPE-RX = Registered XOR NUMBER OF OUTPUTS


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PDF 24-pin 300-mil 28-pln PAL22RX8A PAL22RX8A IC of XOR GATE "XOR Gate" PAL22R
IC of XOR GATE

Abstract: N20R IC of XNOR GATE
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quint 2-Input XOR /XNOR Gate The MC1OE/100E107 is a quint 2-input XO R /XN O R gate . The function output F is the OR of all five XOR outputs, while F is the , . Propagation Delay · O R /NOR Function Outputs · Extended 100E V g g Range of - 4.2V to - 5.46V · 7 5 k ii Input Pulldown R esistors M C10E107 MC100E107 QUINT 2-INPUT XOR /XNOR GATE Pinout: 2B-Lead PLCC , 500 410 725 600 100 250 500 410 7 25 600 1 000 PS 'S K E W W ith in -D e v ic e S


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PDF MC1OE/100E107 600ps C10E107 MC100E107 IC of XOR GATE N20R IC of XNOR GATE
IC of XNOR GATE

Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quint 2-Input XOR /XNOR G ate The MC10E/100E107 is a quint 2-input XOR /XNOR gate . The function output F is the OR of all five XOR outputs, while F is the , MC100E107 • 600ps Max. Propagation Delay • OR/NOR Function Outputs QUINT 2-INPUT XOR /XNOR GATE • Extended 100E V e e Range of - 4.2V to - 5.46V • 75k£i Input Pulldown Resistors Pinout , FN SUFFIX v e e [ P L A S T IC P A C K A G E C A S E 7 7 6 -0 2 15 ] 0 3 © °1 a


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PDF MC10E/100E107 MC10E107 MC100E107 600ps 28-Lead IC of XNOR GATE
2009 - IC of XNOR GATE

Abstract: IC of XOR GATE AND8408 AND8408/D XOR schmitt trigger create pulse ULLGA8 Package frequency doubler ic xnor comparator using 2 xor gates
Text: Introduction A configurable multifunction logic gate is a versatile IC that can be used to create pulse , circuits that are created by adding an external resistor and capacitor to the input pin of the logic gate , falling edge of a clock signal. An exclusive OR gate provides a dual edge detector circuit, as shown in , Figure 7. A resistor, capacitor and XOR gate with an inverted input forms an alternative method to create , a delay at powerup and a quick warning at powerdown buffer gate . Figure 14 provides an example of


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PDF AND8408/D IC of XNOR GATE IC of XOR GATE AND8408 AND8408/D XOR schmitt trigger create pulse ULLGA8 Package frequency doubler ic xnor comparator using 2 xor gates
crc-16 implementation

Abstract: toggle type flip flop ic
Text: quad D-type flip flop with XOR gate or 2:1 MUX data inputs (D0A-D3A, D0B-D3B). When the DA and DB inputs are connected together, data to each of the four stages is the XOR of this input and the SEL Input , DnA = DnB Output Qn (t+1) 10G024 OPERATION (Truth Table with XOR Gate Inputs Configured) Function , device is configured for XOR gate inputs by connecting together the DA and DB inputs and using this as , MUX select or XOR gate inputs Individual flip flop clock inputs Common clock input to all four flip


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PDF QQ00405 10G024 10G024K 10G024K) 10G061 050P3 crc-16 implementation toggle type flip flop ic
2013 - XOR schmitt trigger

Abstract: No abstract text available
Text: Quad NOR / XTR5486 Quad XOR Description 1 1A Input A of first 2-input gate . 2 1B , –² Schmitt trigger inputs. ▲ Compatible with NAN, NOR, XOR , INVERTER functions of the standard 54HC , Input A of first 2-input gate / Input of first inverter. 2 1B / 1Y Input B of first 2-input gate / Output of first inverter. 3 1Y / 2A Output of first 2-input gate / Input of second inverter. 4 2A / 2Y Input A of second 2-input gate / Output of second inverter. PR E Pin


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PDF XTR54000 XTR54000 16-pin DS-00443-13 XOR schmitt trigger
Not Available

Abstract: No abstract text available
Text: function output, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and , * SYNERGY QUINT 2-INPUT XOR /XNOR GATE SY10E107 SY100E107 SEMICONDUCTOR DESCRIPTION FEATURES 600ps max. propagation delay Extended 100E V ee range of -4.2V to -5.5V True and complementary , 75K£2 input pulldown resistors ESD protection of 2000V The SY10/100E107 offer five 2-input XOR /XNOR , Data Inputs Q o -Q 4 XOR Outputs Q 0-Q 4 XNOR Outputs F OR Output F NOR Output


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PDF SY10E107 SY100E107 600ps SY10/100E107 MC10E/100E107 28-pin
Not Available

Abstract: No abstract text available
Text: * QUINT 2-INPUT XOR /XNOR GATE SYNERGY SY10E107 SY100E107 SEMICONDUCTOR FEATURES ■■600ps max. propagation delay ■Extended 100E V e e range of -4.2V to -5.5V ■True and , levels DESCRIPTION The SY10/100E107 offer five 2-input XOR /XNOR gates and are designed for use in new, high- performance ECL systems. The E107 also features a function output, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and complementary outputs are provided. â


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PDF SY10E107 SY100E107 600ps SY10/100E107 MC10E/100E107 SY10E107JC J28-1 SY10E107JCTR SY100E107JC
Not Available

Abstract: No abstract text available
Text: with a more sophisticated manipulation of the XOR gate inputs and the D flip-flop output. j ^ 0 0 , XOR gate on the input of the flip-flop can be used to program the logic polarity of the transfer , indicated in the macrocell logic diagram, one input of the XOR gate is connected to a single product term , input of the D flip-flop. The way in which the XOR gate is used to synthesize the different flip-flop , macrocell. Note that the macrocell data input is a function of the two-input XOR gate , whose inputs are


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PDF MIL-STD-883,
PAL20L10 LATTICE

Abstract: No abstract text available
Text: Year Data Retention • TEN OUTPUT LOGIC MACROCELLS — XOR Gate Capability on all Outputs — Full , term. The output is enabled while this product term is true. The XOR bit controls the polarity of the , for the combinatorial output. The XOR bit con­ trols the polarity of the output. The inverting , Combinatorial with Polarity • PRELOAD AND POWER-ON RESET OF ALL REGISTERS • APPLICATIONS INCLUDE: â , (E2 floating gate technology to provide ) the highest speed Exclusive-OR PLD available in the market


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PDF GAL20XV10 PAL20L10 LATTICE
Not Available

Abstract: No abstract text available
Text: SY10/100E107 offer five 2-input XOR /XNOR gates and are designed for use in new, high- performance ECL systems. The E107 also features a function output, F, which is the OR of all five XOR gate outputs , * SYNERGY QUINT 2-INPUT XOR /XNOR GATE SY10E107 SY100E107 SEMICONDUCTOR DESCRIPTION FEATURES 600ps max. propagation delay Extended 100E V ee range of -4.2V to -5.5V True and complementary , resistors ESD protection of 2000V Fully compatible with Motorola MC10E/100E107 Available in 28-pin PLCC


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PDF SY10E107 SY100E107 600ps SY10/100E107 MC10E/100E107 28-pin
Not Available

Abstract: No abstract text available
Text: function^utput, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and , * QUINT 2-INPUT XOR /XNOR GATE SYNERGY SEMICONDUCTOR FEATURES SY10E107 SY100E107 , function outputs ESD protection of 2000V Fully compatible with Industry standard 10KH, 100K I/O levels ■Extended 100E V e e range of -4.2V to -5.46V ■Internal 75KQ input pulldown resistors ■Fully compatible with Motorola MC10E/100E107 The SY10E107 and SY100E107 offer five 2-input XOR / XNO


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PDF SY10E107 SY100E107 600ps MC10E/100E107 SY10E107 SY100E107 SY10E107JC J28-1 SY100E107JC
Not Available

Abstract: No abstract text available
Text: M O TO RO LA SEMICONDUCTOR TECHNICAL DATA Low -Voltage CMOS Quad 2-Input XOR Gate MC74LCX86 With 5V-Tolerant Inputs The MC74LCX86 is a high performance, quad 2-input XOR gate operating from a , | specification of 5.5V allows MC74LCX86 inputs to be safely driven from 5V devices. Current drive capability is 24mA at the outputs. LCX LOW-VOLTAGE CMOS QUAD 2-INPUT XOR GATE • Designed for 2.7 to 3.6V V , 0.4 V c c = 3-OV; IO L = 16mA 0.4 VCC = 3-OV; Iq l = 24mA 0.55 2. These values of V


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PDF MC74LCX86 MC74LCX86 751A0V 10MHz, b3b72S2 BR1339 500ns
RAS 2415

Abstract: hamming code mc74f MC74F2960A
Text: ( XOR ) The check bit is generated as either an XOR or XNOR of the eight data bits noted by an "X" 10 , XOR or XNOR of the 32 53 54 X X X X 55 X X X X X X 56 X X 57 58 X X X 59 60 X X X X X 61 X X X X X X X , at least one of the two errors is a hard error. This requires extra processor cycles. ZD ZD =] ZD , -BIT DATA W O R D S BUILT-IN D IA G N O ST IC S PER M IT S SO FTW A RE S Y S T E M CHECK SEPARATE BYTE CO N , Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power


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PDF MC74F2960/D MC74F2960/ Am2960 MC74F2960A C74F2960 74F2960A C6460B RAS 2415 hamming code mc74f MC74F2960A
ORP 12

Abstract: ispLSI1000
Text: from the GLB. The Reconfigurable Registers consist of four D-type flipflops with an XOR gate on the input. The XOR gate in the GLB can be used either as a logic element or to reconfig ure the D-type , £> MUX ri MUX To Output Enable Mux Figure 4. GLB: XOR Gate Example Inputs From Global , using the XOR gate while Output Two (02) is configured using the four Product Term Bypass. Output One (01) uses one of the inputs from the five Product Term OR gate while Output Zero (00) combines the


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PDF 1000E t20ptxor) 1032E-100 ORP 12 ispLSI1000
Not Available

Abstract: No abstract text available
Text: The M C 10107 is a triple— input exclusive O R /N O R gate . 2 P p = 40 m W typ/ gate (No Load , MC10107 E LE C TR IC A L C H A R A C TE R IS T IC S (continued) TEST VOLTAGE VALUES (Volts) @ Test , to either Output 5, 5, 5, 5, 15 15 15 15 Input 4 ,9 or 14 Corresponding XOR , either Output 4, 9, 14 4, 9, 14 4, 9, 14 4, 9,14 Input 5, 7 or 15 Corresponding XOR /XNOR , Corresponding XOR /XNOR Outputs 8 1, 16 t+ t- * 7, 7, 7, 7, 16 16 16 16


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PDF PIN16 50-ohm DL122
xor IC

Abstract: MOTOROLA ECL IC of XNOR GATE
Text: 10KH, 100K I/O levels Internal 75KQ input pulldown resistors ESD protection of 2000V D E S C R IP TIO N The SV10/100E107 offer five 2-input XOR /XNOR gates and are designed for use in new, high- performance ECL systems. The E107 also features a function output, F, which is the OR of all five XOR gate , 'O' QUINT 2-INPUT < O R / X N O R GA T E 3Y10E1Û7 Y 10 R E i 0 7 SY N E R G Y S E M IC O N D U C T O R FEATURES 600ps max. propagation delay Extended 100E Vee range of -4.2V to


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PDF 3Y10E1 600ps SV10/100E107 MC10E/100E107 Typ410 SY10E107JC SY10E107JCTR SY100E107JC SY100E107JCTR J28-1 xor IC MOTOROLA ECL IC of XNOR GATE
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