The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
BD9G201EFJ-M BD9G201EFJ-M ECAD Model ROHM Semiconductor 4.5V to 42V, 1ch Buck Converter
BD8306MUV BD8306MUV ECAD Model ROHM Semiconductor 1.8-5.5V 1A 1ch Buck-Boost converter
BD70522GUL BD70522GUL ECAD Model ROHM Semiconductor Ultra Low Iq Buck Converter For Low Power Applications
BD7682FJ-LB BD7682FJ-LB ECAD Model ROHM Semiconductor Quasi-resonant type (low EMI) Control DC/DC converter IC for AC/DC Converter
BD9D321EFJ BD9D321EFJ ECAD Model ROHM Semiconductor 4.5 to 18V 3.0A 1ch Synchronous Buck Converter,External Current Detection Resistors, 1.4 ohm on resistor
BU33UV7NUX BU33UV7NUX ECAD Model ROHM Semiconductor 0.6 V to 4.5 V, 1ch SSynchronous Boost DC/DC Converter

Hsync Vsync convert Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2001 - Hsync Vsync analog to digital convert

Abstract: Hsync Vsync convert Hsync Vsync VGA rgb to hsync vsync VSYNC HSYNC DDC_CLOCK DDC_DATA Hsync Vsync separate ttl input convert to vga output Hsync Vsync Hsync Vsync RGB HSYNC, VSYNC input output
Text: protection diodes, < 5pF typical · TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines · , to VAUX) for HSYNC & VSYNC inputs · Pull-up resistors (1.8K nominal to VCC) for DDC_CLK and , included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These , HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers also have high , B DDC_DATA HSYNC VSYNC HSYNC_OUT C1780401 © 2001 California Micro Devices Corp. All


Original
PDF PACVGA105 IEC-1000-4-2 16-Lead PACVGA105Q Hsync Vsync analog to digital convert Hsync Vsync convert Hsync Vsync VGA rgb to hsync vsync VSYNC HSYNC DDC_CLOCK DDC_DATA Hsync Vsync separate ttl input convert to vga output Hsync Vsync Hsync Vsync RGB HSYNC, VSYNC input output
F27h

Abstract: MTV412 MTV412MV MTV412M MTV412MF MTV412MS f29h F42H ad2e P72E
Text: ALE INT1 XFR ADC AD0-3 AUXRAM & DDCRAM1 & DDCRAM2 HSYNC VSYNC HBLANK VBLANK HCLAMP , .2 1 42 VSYNC /P7.4 DA1/P5.1 2 41 HSYNC /P7.3 DA0/P5.0 3 40 DA3/P5 , .6 VDD3 DA0/P5.0 VSYNC /P7.4 DA2/P5.2 DA1/P5.1 DA3/P5.3 HSYNC /P7.3 DA4/P5.4 DA5/P5.5 6 , MTV412M DA0/P5.0 VSYNC /P7.4 DA2/P5.2 DA1/P5.1 DA3/P5.3 HSYNC /P7.3 DA4/P5.4 DA5/P5 , power, all output pins swing from 0~3.3V, HSYNC , VSYNC and open drain pin can accept 0~5V input range


Original
PDF MTV412M 12MHz 1024-byte 128K-byte 44-pin) 42-pin) F27h MTV412 MTV412MV MTV412M MTV412MF MTV412MS f29h F42H ad2e P72E
myson isp

Abstract: 24Lc02 eeprom mtv312 MTV312M64 f29h 7031H 24LC02 p607 MTV312M44 F39h
Text: ADC AUXRAM & DDCRAM H/ VSYNC CONTROL HSYNC VSYNC HBLANK VBLANK PWM DAC P6.0-7 P5 , 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNC HSYNC DA3/P5 , 27 26 25 24 23 22 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HLFHO DA9/HALFV HBLANK/P4 , .0/AD0 P6.1/AD1 P1.7 P1.6 P1.5 DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC DA2/P5.2 DA1/P5 , 3.3V power, all output pins swing from 0~3.3V, HSYNC , VSYNC and open drain pin can accept 0~5V input


Original
PDF MTV312M64 12MHz 1024-byte 64K-byte 868mm 256mm 44-pin 70TYP. myson isp 24Lc02 eeprom mtv312 MTV312M64 f29h 7031H 24LC02 p607 MTV312M44 F39h
MTV312M64

Abstract: da1228 12MARCH 24Lc02 eeprom ad2e p607 8051 based pulse counter 0700M 8051 simple lcd program 8051 programming in c
Text: CONTROL HSYNC VSYNC HBLANK VBLANK PWM DAC P6.0-7 P5.0-6 AUX I/O DA0-13 DDC & IIC , DA2/P5.2 1 42 VSYNC DA1/P5.1 2 39 HSYNC DA1/P5.1 2 41 HSYNC DA0/P5 , .2 DA1/P5.1 VSYNC DA3/P5.3 HSYNC DA4/P5.4 DA5/P5.5 6 5 4 3 2 44 43 , , HSYNC , VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And , bit). ii) H/V Frequency Counter MTV312M can discriminate HSYNC / VSYNC frequency and save the


Original
PDF MTV312M64 MTV312M 1024-byte 64Kbyte 12MHz 64K-byte MTV312M64 da1228 12MARCH 24Lc02 eeprom ad2e p607 8051 based pulse counter 0700M 8051 simple lcd program 8051 programming in c
2013 - Not Available

Abstract: No abstract text available
Text: protection for all signals, Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals , match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used , Buffers for the HSYNC and VSYNC Lines * High impedance Pull−Ups (50kΩ Nominal to VAUX) for HSYNC , . VAUX supply pin. This is the supply input for the 50kΩ pullups connected to the HSYNC and VSYNC , HSYNC , VSYNC GND-0.5 ~ VAUX +0.5 V DDC_CLK, DDC_DATA GND-0.5 ~ VCC +0.5 V Package Power Rating


Original
PDF QW-R223-021
P56E

Abstract: hf6 56 HSYNC, VSYNC counter ad2e Hsync Vsync convert HIIC2 AD3E
Text: AD0-3 P7.0-7 AUXRAM & DDCRAM1 & DDCRAM2 DA0-13 ADC H/ VSYNC CONTROL HSYNC VSYNC , ~3.3V, HSYNC , VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V , I/O I/O I/O I/O I/O O O O HSYNC /P7.3 41 43 I/O VSYNC /P7.4 42 44 I/O , .4. Pin " VSYNC /P7.4" is VSYNC . Pin " HSYNC /P7.3" is P7.3. Pin " HSYNC /P7.3" is HSYNC . Pin "DA9/P7 , (DF1,DF0) bits. The VSYNC digital filter has no control bit. It works as (DF1,DF0) = (0, 0) of HSYNC


Original
PDF MTV412M 12MHz 1024-byte 128K-byte 44-pin) 42-pin) 494mm 868mm 256mm 70TYP. P56E hf6 56 HSYNC, VSYNC counter ad2e Hsync Vsync convert HIIC2 AD3E
F38h

Abstract: AD2E AD3E lcd interface with 8051 8051 pin configuration 8051 simple program Digital Clock LCD 8051 F40H Hsync Vsync generator write 8051 adc using simple program
Text: WR ALE INT1 XFR AD0-3 P3.4-5 ADC AUXRAM & DDCRAM H/ VSYNC CONTROL HSYNC , 28 27 26 25 24 23 22 21 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HLFHO DA9/HALFV , 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSYNC HSYNC , /P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD3 NC NC 40 41 42 , output pins swing from 0~3.3V, HSYNC , VSYNC and open drain pin can accept 0~5V input range, other pins


Original
PDF MTV312M64 12MHz 1024-byte 64K-byte Sing868mm 254mm 256mm 44-pin 70TYP. F38h AD2E AD3E lcd interface with 8051 8051 pin configuration 8051 simple program Digital Clock LCD 8051 F40H Hsync Vsync generator write 8051 adc using simple program
8051 ADC

Abstract: MTV212 MTV212A16 MTV212A24 MTV212A32U MTV212A48U MTV212A64U MTV212M32 PDIP40 SDIP42
Text: .07 RD WR ALE INT1 P1.0-7 ALE INT1 XFR H/ VSYNC CONTROL STOUT HBLANK VBLANK HSYNC , customer' demand. s DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC RST VDD P2.3/AD3 VSS X2 X1 ISDA , HSDA/P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH , 16 17 18 19 20 21 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH DA9/HALFV HBLANK/P4 , .0 HBLANK/P4.1 DA9/HALFV DA8/HALFH DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC Revision 1.1 Type I


Original
PDF MTV212M32 12MHz 512-byte 32K-byte 6-bit36 256mm 70TYP. 8051 ADC MTV212 MTV212A16 MTV212A24 MTV212A32U MTV212A48U MTV212A64U MTV212M32 PDIP40 SDIP42
write 8051 adc using simple program

Abstract: 8051 ADC 8051 pin configuration COP20 myson 8051 8bit microcontroller COP23
Text: .07 RD WR ALE INT1 P1.0-7 ALE INT1 XFR H/ VSYNC CONTROL STOUT HBLANK VBLANK HSYNC , customers'demand. DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC RST VDD P2.3/AD3 VSS X2 X1 ISDA/P3.4/T0 , /P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH , 16 17 18 19 20 21 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH DA9/HALFV HBLANK/P4 , /P4.0 HBLANK/P4.1 DA9/HALFV DA8/HALFH DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC Revision 0.9


Original
PDF MTV212M64i 12MHz 1024-byte 64K-byte 256mm 70TYP. write 8051 adc using simple program 8051 ADC 8051 pin configuration COP20 myson 8051 8bit microcontroller COP23
myson isp

Abstract: 0746H
Text: .07 RD WR ALE INT1 P1.0-7 ALE INT1 XFR H/ VSYNC CONTROL STOUT HBLANK VBLANK HSYNC , ' demand. DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC RST VDD P2.3/AD3 VSS X2 X1 ISDA/P3.4/T0 , /P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH , 16 17 18 19 20 21 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH DA9/HALFV HBLANK/P4 , /P4.0 HBLANK/P4.1 DA9/HALFV DA8/HALFH DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC Revision 0.9


Original
PDF MTV212M64i 12MHz 1024-byte 64K-byte 256mm 70TYP. myson isp 0746H
myson isp

Abstract: MTV312M64 F42H Hsync Vsync generator myson 312m 24LC02 8051 simple lcd program 24Lc02 eeprom
Text: ADC AUXRAM & DDCRAM H/ VSYNC CONTROL HSYNC VSYNC HBLANK VBLANK PWM DAC P6.0-7 P5 , 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNC HSYNC DA3/P5 , 27 26 25 24 23 22 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HLFHO DA9/HALFV HBLANK/P4 , .0/AD0 P6.1/AD1 P1.7 P1.6 P1.5 DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC DA2/P5.2 DA1/P5 , are connected to 3.3V power, all output pins swing from 0~3.3V, HSYNC , VSYNC and open drain pin can


Original
PDF MTV312M64 12MHz 1024-byte 64K-byte 868mm 256mm 70TYP. myson isp MTV312M64 F42H Hsync Vsync generator myson 312m 24LC02 8051 simple lcd program 24Lc02 eeprom
0746H

Abstract: P56E 1244H ad2e HSYNC, VSYNC input output Hsync Vsync convert MTV212A16 DA91 MTV212A32U MTV212A48U
Text: AD0-2 ADC H/ VSYNC CONTROL RST STOUT HBLANK VBLANK HSYNC VSYNC HCLAMP HALFV HALFH , ) MYSON TECHNOLOGY PIN CONNECTION DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC RST VDD NC VSS X2 , -3- HSDA/P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5 , 13 14 15 16 17 18 19 20 21 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH DA9 , DA4/P5.4 I/O 37 DA3/P5.3 I/O 38 I I 39 40 HSYNC VSYNC Revision 1.2


Original
PDF MTV212A32 12MHz 512-byte 32K-byte 494mm 868mm 254mm 256mm 70TYP. 0746H P56E 1244H ad2e HSYNC, VSYNC input output Hsync Vsync convert MTV212A16 DA91 MTV212A32U MTV212A48U
p5038

Abstract: 0746H
Text: .07 RD WR XFR ALE INT1 H/ VSYNC CONTROL 8051 AD0-2 STOUT HBLANK VBLANK HSYNC VSYNC , .1/AD1 P1.6 20 21 P1.7 DA2/P5.2 1 42 VSYNC DA1/P5.1 2 41 HSYNC DA0 , DA3/P5.3 HSYNC 36 44 5 VSYNC DA4/P5.4 VDD 2 37 DA2/P5.2 DA1/P5.1 4 3 DA3/P5.3 RST DA0/P5.0 38 4 3 NC HSYNC DA0/P5.0 5 VSYNC 39 6 , .4 DA3/P5.3 HSYNC VSYNC Type I/O I/O I/O I I/O O I I/O I/O O I/O I/O I/O I I/O I/O


Original
PDF MTV212M64i 12MHz 1024-byte 64K-byte 494mm 868mm 256mm 70TYP. p5038 0746H
ad2e

Abstract: AD3E circuit diagram for interfacing dac with 8051 mtv212m MTV212A16 MTV212A24 MTV212A32 MTV212A32U MTV212A48U MTV212A64U
Text: .7 P1.3 20 21 P1.4 DA2/P5.2 1 42 VSYNC DA1/P5.1 2 41 HSYNC DA0/P5 , Pin PDIP #1 Non-USB USB DA0/P5.0 DA2/P5.2 DA1/P5.1 VSYNC DA3/P5.3 HSYNC DA4/P5 , DA8/HALFH DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC I/O I/O I/O I/O I/O I/O I I/O O I I , / General purpose Output. PWM DAC output / Vsync half freq. output (open drain). PWM DAC output / Hsync , "DA9/HALFV" is VSYNC half frequency output. pin "DA9/HALFV" is DA9. pin "DA8/HALFH" is HSYNC half


Original
PDF MTV212M64 12MHz 1024-byte 64K-byte 70TYP. ad2e AD3E circuit diagram for interfacing dac with 8051 mtv212m MTV212A16 MTV212A24 MTV212A32 MTV212A32U MTV212A48U MTV212A64U
MTV212A16

Abstract: MTV212 MTV212A24 MTV212A32U MTV212A48U MTV212A64U MTV212M32 PDIP40 SDIP42 AD3E
Text: XFR AD0-2 ADC H/ VSYNC CONTROL P3.4-5 RST X1 X2 STOUT HBLANK VBLANK HSYNC VSYNC , .7 DA2/P5.2 1 42 VSYNC DA1/P5.1 2 41 HSYNC DA0/P5.0 3 40 DA3/P5.3 NC , DA0/P5.0 38 4 3 NC HSYNC DA0/P5.0 5 VSYNC 39 6 40 2 NC 1 , /HCLAMP VBLANK/P4.0 HBLANK/P4.1 DA9/HALFV DA8/HALFH DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC , HSYNC / VSYNC frequency and saves the information in XFRs. The 14 bits Hcounter counts the time of


Original
PDF MTV212M32 12MHz 512-byte 32K-byte 494mm 868mm 256mm 70TYP. MTV212A16 MTV212 MTV212A24 MTV212A32U MTV212A48U MTV212A64U MTV212M32 PDIP40 SDIP42 AD3E
micro controller 8051

Abstract: 7031H 8051 reset circuit MTV212 MTV212A16 MTV212A24 MTV212A32U MTV212A48U MTV212A64U MTV212M32
Text: .07 RD WR ALE INT1 P1.0-7 ALE INT1 XFR H/ VSYNC CONTROL STOUT HBLANK VBLANK HSYNC , customer's demand. DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC RST VDD P2.3/AD3 VSS X2 X1 ISDA , HSDA/P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH , 16 17 18 19 20 21 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH DA9/HALFV HBLANK/P4 , .0 HBLANK/P4.1 DA9/HALFV DA8/HALFH DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC Revision 1.1 Type I


Original
PDF MTV212M32 12MHz 512-byte 32K-byte 256mm 70TYP. micro controller 8051 7031H 8051 reset circuit MTV212 MTV212A16 MTV212A24 MTV212A32U MTV212A48U MTV212A64U MTV212M32
ad2e

Abstract: MTV212A32 MTV212A32U MTV212A48U MTV212A64U PDIP40 PLCC44 SDIP42 MTV212 MTV212A16
Text: AD0-2 ADC H/ VSYNC CONTROL RST STOUT HBLANK VBLANK HSYNC VSYNC HCLAMP HALFV HALFH , ) MYSON TECHNOLOGY PIN CONNECTION DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC RST VDD NC VSS X2 , -3- HSDA/P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5 , 13 14 15 16 17 18 19 20 21 VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HALFH DA9 , DA4/P5.4 I/O 37 DA3/P5.3 I/O 38 I I 39 40 HSYNC VSYNC Revision 1.2


Original
PDF MTV212A32 12MHz 512-byte 32K-byte 494mm 868mm 254mm 256mm 70TYP. ad2e MTV212A32 MTV212A32U MTV212A48U MTV212A64U PDIP40 PLCC44 SDIP42 MTV212 MTV212A16
2011 - Hsync Vsync convert

Abstract: Hsync Vsync analog to digital convert Hsync Vsync Hsync Vsync separate
Text: in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers , Protection Diodes at Less than 5 pF Typical TTL to CMOS Level-Translating Buffers for the HSYNC and VSYNC , Graphics Controller ICs High impedance Pull-Ups (50 kW Nominal to VAUX) for HSYNC and VSYNC Inputs Pull-Up , 1.8 kW R G B DDC_CLK 1.8 kW 50 kW 50 kW VSYNC_OUT VAUX GNDA DDC_DATA HSYNC VSYNC GNDD , to the HSYNC and VSYNC buffer inputs. Vertical sync signal buffer input. Connects to the VGA


Original
PDF PACVGA105 IEC-1000-4-2 PACVGA105/D Hsync Vsync convert Hsync Vsync analog to digital convert Hsync Vsync Hsync Vsync separate
Not Available

Abstract: No abstract text available
Text: I/O I/O — — SDA SCL MASTER CLK VCC GND D.VCC RESET BLANK VSYNC HSYNC A.GND , : HORIZONTAL SYNC HSYNC SDA : SERIAL INTERFACE DATA : VERTICAL SYNC VSYNC BT865AKRF (3/3) SCL SDA , LATCH HSYNC VREF 43 10 RESET VBIAS 50 MOD. AND MIXER BLANK CVBS/G DAC 13 Y/CVBS 49 48 10 COLOR SPACE CONVERT 10 VSYNC DAC FIELD MASTER ALTADDR


Original
PDF BT865AKRF
2004 - Hsync Vsync VGA

Abstract: Hsync Vsync convert Hsync Vsync separate Notebook lcd rgb schematic Hsync Vsync RGB schematic diagram video to vga VGA 20 PIN LCD notebook CONNECTION DIAGRAM ttl input convert to vga output Non VGA Video Controller IC IEC-1000-4-2
Text: typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent supply , impedance pull-ups (50k nominal to VAUX) for HSYNC and VSYNC inputs Pull-up resistors (1.8k nominal to VCC , Two non-inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from , the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used. The , 1.8k 50k 50k VSYNC_OUT DDC_CLK G B GNDD GNDA DDC_DATA HSYNC VSYNC HSYNC_OUT


Original
PDF PACVGA105 PACVGA105 IEC-1000-4-2 IEC-1000-4-2 QSOP-16 Hsync Vsync VGA Hsync Vsync convert Hsync Vsync separate Notebook lcd rgb schematic Hsync Vsync RGB schematic diagram video to vga VGA 20 PIN LCD notebook CONNECTION DIAGRAM ttl input convert to vga output Non VGA Video Controller IC
Not Available

Abstract: No abstract text available
Text: buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics , impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers also , Buffers for the HSYNC and VSYNC Lines Three Independent Supply Pins (VCC, VRGB and VAUX) to Facilitate , HSYNC and VSYNC Inputs Pull−Up Resistors (1.8 kW Nominal to VCC) for DDC_CLK and DDC_DATA Lines , VSYNC_OUT GNDD DDC_DATA HSYNC VSYNC GNDA 50 kW HSYNC_OUT PACKAGE / PINOUT DIAGRAMS Top


Original
PDF PACVGA105 PACVGA105 PACVGA105/D
2006 - TV vertical section

Abstract: NJM2207 "Video Switches" DMP14 Package DMP14 NJM2207D NJM2207M NJM2207S ZIP16 Hsync Vsync convert
Text: Threshold Voltage VISP Source Resistance Rg=75 100 140 180 mV H-Sync . High Level VHH1 RL=100k Pin 3 (13) 4.0 - - V H-Sync . High Level VHH2 RL=2.2k Pin 3 (13) 3.6 4.1 - V H-Sync . Low Level VHL RL=2.2k Pin 3 (13) - - 0.1 V H-Sync . High Level VHH ¯ RL=100k Pin 4 (14) 4.9 - - V H-Sync . Low Level VHL ¯ RL=100k Pin 4 (14) - - 0.3 V V-Sync . High Level VVH1 RL=100k Pin 7 (2) 4.0 - -


Original
PDF NJM2207 NJM2207 NJM2207D DIP14, DMP14, ZIP16 NJM2207S DIP14) ZIP16) TV vertical section "Video Switches" DMP14 Package DMP14 NJM2207D NJM2207M NJM2207S ZIP16 Hsync Vsync convert
1996 - HSYNC Clock generator rgb

Abstract: HSYNC, VSYNC Clock generator rgb Hsync Vsync generator video out convert rgb HSYNC, VSYNC Clock generator Vsync, hsync to csync
Text: synchronized to external devices using the Horizontal Sync ( HSYNC ) and Vertical Sync ( VSYNC ) signals. The CL48x , (master) mode. The HSYNC / VSYNC direction (in or out) and the VCK direction (in or out) are independently selectable. HSYNC and VSYNC are always in the same direction. This makes the following four video signal configurations possible: s s s s VSYNC (or CSYNC)/ HSYNC / VCK Out VSYNC / HSYNC / VCK In VSYNC (or CSYNC)/ HSYNC Out and VCK In VSYNC / HSYNC In and VCK Out Note: VCK is typically 27 MHz if the CL48x is operating


Original
PDF CL48x HSYNC Clock generator rgb HSYNC, VSYNC Clock generator rgb Hsync Vsync generator video out convert rgb HSYNC, VSYNC Clock generator Vsync, hsync to csync
2010 - Hsync Vsync VGA

Abstract: Hsync Vsync analog to digital convert Hsync Vsync convert Non VGA Video Controller IC schematic diagram video to vga VGA 20 PIN LCD notebook CONNECTION DIAGRAM IEC-1000-4-2 IEC1000-4-2 IEC-61000-4-2 PACVGA105
Text: 5pF typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent , impedance pull-ups (50k nominal to VAUX) for HSYNC and VSYNC inputs Pull-up resistors (1.8k nominal to VCC , buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics , impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers , 1.8k R 1.8k 50k 50k VSYNC_OUT DDC_CLK G B GNDA DDC_DA TA HSYNC VSYNC


Original
PDF PACVGA105 PACVGA105 IEC1000-4-2 IEC-1000-4-2 Hsync Vsync VGA Hsync Vsync analog to digital convert Hsync Vsync convert Non VGA Video Controller IC schematic diagram video to vga VGA 20 PIN LCD notebook CONNECTION DIAGRAM IEC-61000-4-2
Not Available

Abstract: No abstract text available
Text: Voltage VISP Source Resistance Rg=75 100 140 180 mV H-Sync . High Level VHH1 RL=100k Pin 3 (13) 4.0 - - V H-Sync . High Level VHH2 RL=2.2k Pin 3 (13) 3.6 4.1 - V H-Sync . Low Level VHL RL=2.2k Pin 3 (13) - - 0.1 V H-Sync . High Level VHH ¯ RL=100k Pin 4 (14) 4.9 - - V H-Sync . Low Level VHL ¯ RL=100k Pin 4 (14) - - 0.3 V V-Sync . High Level VVH1 RL=100k Pin 7 (2) 4.0 -


Original
PDF NJM2207 NJM2207 NJM2207D DIP14, DMP14, ZIP16 NJM2207S DIP14) ZIP16)
Supplyframe Tracking Pixel