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Part Manufacturer Supplier Stock Best Price Price Each Buy Part
10-32X5/16PAN PH SS NL MACHINE SCREWS Bisco Industries 158 - -
2-56X3/16FLT PH SS NP SUPPLY CHAIN # JN Bisco Industries 40 - -
2-56X3/16PAN PH SS NP Bisco Bisco Industries 2,529 - -
3-48X3/16PAN PH SS NP Nylok Fastener Bisco Industries 100 - -
4-40X1/2PAN PH SS NP MACHINE SCREWS Bisco Industries 194 - -
4-40X1/4TRS PH SS NP SUPPLY CHAIN # JN Bisco Industries 12,230 - -
4-40X5/6PAN PH SS NP Bisco Bisco Industries 5,000 - -
4-40X5/8FT1 PH SS NP Nylok Fastener Bisco Industries 99 - -
6-32X1/4PAN PH SS NL+ SEMS SCREWS Bisco Industries 310 - -
6-32X1/4PAN PH SS NP MACHINE SCREWS Bisco Industries 70 - -
6-32X3/8PAN PH SS NP Nylok Fastener Bisco Industries 2,500 - -
6-32X7/16FLT PH SS NLP SUPPLY CHAIN # MT Bisco Industries 20 - -
CL-33-SHS-SN Northrop Grumman Electronic Systems New Advantage Corporation 2 - -
M2.5X8MMPAN PH SS NP MACHINE SCREWS Bisco Industries 5 - -
M2X6PAN PH SS NP MACHINE SCREWS Bisco Industries 70 - -
M3-0.5X5PAN PH SS NP MACHINE SCREWS Bisco Industries 4,400 - -
TH452J44HSSN Amphenol Corporation Avnet - - -

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2012 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS , VDD HB HO 3 HS 3 6 HS 4 5 7 VSS 6 4 HI SO Power Pad , 7 3 6 VSS 3 8 LI 4 7 HI 5 6 NC LI WSON-8 HS 4 5 HI VDD HB HO HS 2 9 VSS HO 2 NC LO 10 HS 8 1 HO 1 VDD , positive terminal of the bootstrap capacitor to HB and the negative terminal to HS . The bootstrap


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PDF LM25101A, LM25101B, LM25101C SNVS859B LM25101A/B/C HIP2100/HIP2101
2012 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS , VDD HB HO 3 HS 3 6 HS 4 5 7 VSS 6 4 HI SO Power Pad , 7 3 6 VSS 3 8 LI 4 7 HI 5 6 NC LI WSON-8 HS 4 5 HI VDD HB HO HS 2 9 VSS HO 2 NC LO 10 HS 8 1 HO 1 VDD , positive terminal of the bootstrap capacitor to HB and the negative terminal to HS . The bootstrap


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PDF LM25101A, LM25101B, LM25101C SNVS859B LM25101A/B/C HIP2100/HIP2101
2012 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS , VDD HB HO 3 HS 3 6 HS 4 5 7 VSS 6 4 HI SO Power Pad , 7 3 6 VSS 3 8 LI 4 7 HI 5 6 NC LI WSON-8 HS 4 5 HI VDD HB HO HS 2 9 VSS HO 2 NC LO 10 HS 8 1 HO 1 VDD , positive terminal of the bootstrap capacitor to HB and the negative terminal to HS . The bootstrap


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PDF LM25101A, LM25101B, LM25101C SNVS859B LM25101A/B/C HIP2100/HIP2101
2006 - Not Available

Abstract: No abstract text available
Text: Diagram HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS 1 2 , 7 VSS WSON-8 HO 3 6 LI HS 4 5 HI HO 7 1 10 LO 2 9 VSS 3 8 LI 4 7 HI NC 2 HI HS HB 5 HO LO 4 HB 8 LI VDD 1 6 HS VDD 3 5 6 NC VSS SO PowerPad-8 HO 3 6 LI HS 4 5 WSON-10 HI Exposed Pad Connect to VSS VDD LO HB MSOPPowerPad-8 HO


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PDF LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C LM5100A/B/C LM5101A/B/C
2012 - Not Available

Abstract: No abstract text available
Text: -8 pin packages. SIMPLIFIED BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD , LI HS 8 1 VSS HSOP-8 HO 3 6 LI HS 4 5 HI Exposed Pad Connect , Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS . The , output Connect to the gate of high-side MOSFET with a short, low inductance path. 4 4 HS , (1) −0.3V to +18V VDD to VSS −0.3V to +18V HB to HS LI or HI Input −0.3V to VDD


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PDF LM25101, LM25101A, LM25101B, LM25101C SNVS859A LM25101A/B/C
2006 - Not Available

Abstract: No abstract text available
Text: Diagram HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS 1 2 , 7 VSS WSON-8 HO 3 6 LI HS 4 5 HI HO 7 1 10 LO 2 9 VSS 3 8 LI 4 7 HI NC 2 HI HS HB 5 HO LO 4 HB 8 LI VDD 1 6 HS VDD 3 5 6 NC VSS SO PowerPad-8 HO 3 6 LI HS 4 5 WSON-10 HI Exposed Pad Connect to VSS VDD LO HB MSOPPowerPad-8 HO


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PDF LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C LM5100A/B/C LM5101A/B/C
2006 - 5101bs

Abstract: L5101 BMA L5100 AM L5101AM 5101ASD L5101 L5101BMA 5101as LM5101BMAXNOPB 5100ASD
Text: HB UVLO LEVEL SHIFT HI HO DRIVER HS VDD UVLO LI LO DRIVER VSS 1 2 Please be , Current 3A 3A 2A 2A 1A 1A Connection Diagrams VDD HB HO HS 1 2 8 7 LO VSS LI HO 3 VDD 1 8 LO SOIC-8 3 4 6 5 HI HB 2 7 VSS WSON-8 6 LI HS 4 5 HI VDD 1 8 LO VDD HB 1 2 3 4 5 10 9 LO VSS LI HI NC HB 2 SO PowerPad-8 7 VSS HO HS NC WSON-10 8 7 6 HO 3 6 LI HS 4 5 HI Exposed Pad Connect to VSS VDD HB HO


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PDF LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C LM5100A/B/C LM5101A/B/C 5101bs L5101 BMA L5100 AM L5101AM 5101ASD L5101 L5101BMA 5101as LM5101BMAXNOPB 5100ASD
2012 - Not Available

Abstract: No abstract text available
Text: BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS , VDD HB HO 3 HS 3 6 HS 4 5 7 VSS 6 4 HI SO Power Pad , 7 3 6 VSS 3 8 LI 4 7 HI 5 6 NC LI WSON-8 HS 4 5 HI VDD HB HO HS 2 9 VSS HO 2 NC LO 10 HS 8 1 HO 1 VDD , positive terminal of the bootstrap capacitor to HB and the negative terminal to HS . The bootstrap


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PDF LM25101A, LM25101B, LM25101C SNVS859B LM25101A/B/C HIP2100/HIP2101
2006 - 5101bs

Abstract: No abstract text available
Text: Diagram HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS 1 2 , 7 VSS WSON-8 HO 3 6 LI HS 4 5 HI HO 7 1 10 LO 2 9 VSS 3 8 LI 4 7 HI NC 2 HI HS HB 5 HO LO 4 HB 8 LI VDD 1 6 HS VDD 3 5 6 NC VSS SO PowerPad-8 HO 3 6 LI HS 4 5 WSON-10 HI Exposed Pad Connect to VSS VDD LO HB MSOPPowerPad-8 HO


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PDF LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C LM5100A/B/C LM5101A/B/C 5101bs
2012 - Not Available

Abstract: No abstract text available
Text: UVLO LEVEL SHIFT HI HO DRIVER HS VDD UVLO LI LO DRIVER VSS 1 2 Please be aware , Input Thresholds TTL TTL TTL Peak Output Current 3A 2A 1A Connection Diagrams VDD HB HO HS 1 2 8 7 LO VSS HB LI HI HO 3 2 SO Power Pad-8 7 VSS VDD 1 8 LO SOIC-8 3 4 6 5 6 LI HS 4 5 HI Exposed Pad Connect to VSS VDD 1 8 LO VDD HB HB 2 7 VSS HO 6 LI HS HS 4 5 HI NC 4 5 7 6 HI NC 3 1 2 10 9 LO VSS LI WSON-8 HO 3 WSON-10 8 VDD HB HO HS MSOPPowerPad-8 LO VSS LI HI


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PDF LM25101A, LM25101B, LM25101C SNVS859B LM25101A/B/C HIP2100/HIP2101 WSON-10
2006 - Not Available

Abstract: No abstract text available
Text: HB UVLO LEVEL SHIFT HI HO DRIVER HS VDD UVLO LI LO DRIVER VSS 1 2 Please be , Current 3A 3A 2A 2A 1A 1A Connection Diagrams VDD HB HO HS 1 2 8 7 LO VSS LI HO 3 VDD 1 8 LO SOIC-8 3 4 6 5 HI HB 2 7 VSS WSON-8 6 LI HS 4 5 HI VDD 1 8 LO VDD HB 1 2 3 4 5 10 9 LO VSS LI HI NC HB 2 SO PowerPad-8 7 VSS HO HS NC WSON-10 8 7 6 HO 3 6 LI HS 4 5 HI Exposed Pad Connect to VSS VDD HB HO


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PDF LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C LM5100A/B/C LM5101A/B/C
2012 - Not Available

Abstract: No abstract text available
Text: -8 pin packages. SIMPLIFIED BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD , LI HS 8 1 VSS HSOP-8 HO 3 6 LI HS 4 5 HI Exposed Pad Connect , Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS . The , output Connect to the gate of high-side MOSFET with a short, low inductance path. 4 4 HS , (1) −0.3V to +18V VDD to VSS −0.3V to +18V HB to HS LI or HI Input −0.3V to VDD


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PDF LM25101, LM25101A, LM25101B, LM25101C SNVS859A LM25101A/B/C
nl250

Abstract: S310 S312 SP25 SP26 PD16602 S-112N
Text: 1 4 2 26 LPC PL/NL VDD2A HS VCOM BIAS1 VSS2A BIAS2 VSS2C . S1 S312 1 BIAS1 - SW3 SW1 CH DR0 to DR3 S/HP DG0 to DG3 Sn DB0 to DB3 - SW4 SW2 BIAS2 CH SPn S/HN PL/NL HS SPnIC 5.56 2 µ PD16602 2 , . . PL/NL S5 . HS , = H S/D = H PL/NL = L PL/NL = H S/D S/D = H S/D = L HS HS =


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PDF PD16602 312TFT-LCD PD16602TFT-LCD1024 PD16602N-× S10671JJ1V0DS001 nl250 S310 S312 SP25 SP26 PD16602 S-112N
S-112N

Abstract: S310 S312 SP25 SP26 PD16602TFT-LCD1024 LCD VCOM PD16602
Text: 1 4 2 26 LPC PL/NL VDD2A HS VCOM BIAS1 VSS2A BIAS2 VSS2C . S1 S312 1 BIAS1 - SW3 SW1 CH DR0 to DR3 S/HP DG0 to DG3 Sn DB0 to DB3 - SW4 SW2 BIAS2 CH SPn S/HN PL/NL HS SPnIC 5.56 2 µ PD16602 2 , . . PL/NL S5 . HS , = H S/D = H PL/NL = L PL/NL = H S/D S/D = H S/D = L HS HS =


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PDF PD16602 312TFT-LCD PD16602TFT-LCD1024 PD16602N-× S10671JJ1V0DS001 S-112N S310 S312 SP25 SP26 LCD VCOM PD16602
2012 - L25101

Abstract: No abstract text available
Text: HS VDD UVLO LI LO DRIVER VSS 1 2 Please be aware that an important notice concerning , Current 3A 2A 1A Connection Diagrams VDD HB HO HS 1 2 8 7 LO VSS HB LI HI HO 3 2 HSOP-8 6 LI 7 VSS VDD 1 8 LO SOIC-8 3 4 6 5 HS 4 5 HI Exposed Pad Connect to VSS Pin Descriptions , negative terminal to HS . The bootstrap capacitor should be placed as close to the IC as possible. Connect , ground plane under the IC to aid in heat dissipation. 3 4 5 6 7 8 3 4 5 6 7 8 EP HO HS HI LI VSS


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PDF LM25101, LM25101A, LM25101B, LM25101C SNVS859A LM25101A/B/C L25101
coshh

Abstract: solder coshh assessment coshh data sheet lead free solder fume smoke MS24 MS25 45e5 EH40 coshh lead free solder
Text: CEL Part No. 680105 680107 680106 680108 680109 680110 Tin/Copper ( Sn /Cu) Tin/Copper ( Sn /Cu) Tin/Silver/Copper ( Sn /Ag/Cu) Tin/Silver/Copper ( Sn /Ag/Cu) Tin/Silver/Copper ( Sn /Ag/Cu) Tin/Silver/Copper ( Sn /Ag/Cu) : Anglia (refer to sheet 4 for contact details). Composition / Information , Composition (typical values) 45C501A 45C102C Sn /Cu Tin 99% / Copper 1% 45D501A 45D102C Sn /Ag/Cu Tin 95.2% / Silver 3.8% / Copper 1% 45E501A 45E102C 3. CEL Part No. Sn /Ag/Cu


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PDF 45C501A 45C102C 45D501A 45D102C 45E501A 45E102C 91/155/EEC, 93/112/EEC) coshh solder coshh assessment coshh data sheet lead free solder fume smoke MS24 MS25 45e5 EH40 coshh lead free solder
2012 - Not Available

Abstract: No abstract text available
Text: -8 pin packages. SIMPLIFIED BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD , LI HS 8 1 VSS HSOP-8 HO 3 6 LI HS 4 5 HI Exposed Pad Connect , Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS . The , output Connect to the gate of high-side MOSFET with a short, low inductance path. 4 4 HS , (1) −0.3V to +18V VDD to VSS −0.3V to +18V HB to HS LI or HI Input −0.3V to VDD


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PDF LM25101, LM25101A, LM25101B, LM25101C SNVS859A LM25101A/B/C
2012 - Not Available

Abstract: No abstract text available
Text: -8 pin packages. SIMPLIFIED BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD , LI HS 8 1 VSS HSOP-8 HO 3 6 LI HS 4 5 HI Exposed Pad Connect , Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS . The , output Connect to the gate of high-side MOSFET with a short, low inductance path. 4 4 HS , (1) −0.3V to +18V VDD to VSS −0.3V to +18V HB to HS LI or HI Input −0.3V to VDD


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PDF LM25101, LM25101A, LM25101B, LM25101C SNVS859A LM25101A/B/C
2007 - Not Available

Abstract: No abstract text available
Text: LEVEL SHIFT DRIVER HO HS HI VDD UVLO DRIVER LO LI VSS 1 2 Please , HB 7 2 HS 8 1 5 4 VDD 6 3 HB 7 2 LI 8 1 HO 6 HS 5 LO WSON-8 SOIC-8 Figure 1. 8-Pin SOIC Package See Package Number D (R-PDSO-G8 , driver output Connect to the gate of the low-side N-MOS device. 6 6 HS High side source , bootstrap capacitor to HS . The bootstrap capacitor should be placed as close to IC as possible. For WSON


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PDF LM5109B SNVS477B LM5109B ISL6700
2006 - Not Available

Abstract: No abstract text available
Text: Simplified Block Diagram VDD HV HB HO DRIVER LEVEL SHIFT UVLO HS HI VDD UVLO , 7 HO HI 2 7 HO LI 3 6 HS LI 3 6 HS VSS 4 5 LO , . 6 6 HS High side source connection Connect to the negative terminal of the bootstrap , bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS . The bootstrap , –0.3V to 18V HB to HS −0.3V to 18V −0.3V to VDD + 0.3V LI or HI to VSS LO to VSS


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PDF LM5109A SNVS412A LM5109A
2006 - 170M

Abstract: GP64 VP531 VP531E VP551E Model CG 100 A
Text: 806 to 138 HS normal (64 cks) Table.4 for NTSC and PAL-B, D, G, H, I, N PAL HCNT = SN + 127 , ) HCNT = SN + 739 ( SN = 739 - 857) NCK 0 to 131 * HS pulse shortened means that the width of the , the TRS codes or the HS and VS inputs. The rise and fall times of sync, burst envelope and video , 25 26 27 28 29 30 31 32 FUNCTION VDD GND D0 (VS I/O) D1 ( HS I/O) D2 (FC0 O/P) D3 (FC1 , SL_HS_VS 1 = Slave to HS and VS inputs VFS1-0 HANC Horizontal Ancillary Data Control DFI2-0(read


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PDF VP531E/VP551E DS4573 VP531/VP551 27MHz 170M GP64 VP531 VP531E VP551E Model CG 100 A
1999 - FR07

Abstract: Block diagram on monochrome tv transmitter DS4573 VP551E VP531E VP531 GP64 170M fr17 FR06
Text: /PALM HCNT = SN + 119 ( SN = 0 - 738) HCNT = SN + 739 ( SN = 739 - 857) NCK 0 to 131 * HS pulse , slave mode the device will lock to the TRS codes or the HS and VS inputs. The rise and fall times of , I/O) D1 ( HS I/O) D2 (FC0 O/P) D3 (FC1 O/P) D4 (FC2 O/P) D5 D6 (SCSYNC I/P) D7 (PALID I/P , applied to PXCK pin. Low = normal operation (default). SL_HS_VS 1 = Slave to HS and VS inputs , defined in GPPCTL) HSOFFM-L HSOFF9-0 HS offset This is a 10 bit number which allows the user to


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PDF VP531E/VP551E DS4573 VP531/VP551 27MHz VP531 FR07 Block diagram on monochrome tv transmitter VP551E VP531E GP64 170M fr17 FR06
coshh lead free solder

Abstract: SOLDER WIRE coshh solder coshh assessment 43D501F coshh data sheet lead free solder
Text: / / / / 681118 681122 681318 681322 Alloy Tin/Copper ( Sn /Cu) Tin/Copper ( Sn /Cu) Tin/Silver/Copper ( Sn /Ag/Cu) Tin/Silver/Copper ( Sn /Ag/Cu) : Anglia (refer to sheet 4 for contact details). Composition , reflects the hazards associated with solder reflow operations. Chemical Breakdown : Alloy Sn /Cu Sn /Ag/Cu 3. Composition (typical values) Tin 99% Copper 1% Flux Level Halide Content , Detailed Guidance from the UK Health and Safety Executive : HS (G) 37 HS (G) 53 HS (G) 97 An


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PDF 22swg. 43C501D/1 43C501F/1 43D501D/1 43D501F/1 91/155/EEC, 93/112/EEC) coshh lead free solder SOLDER WIRE coshh solder coshh assessment 43D501F coshh data sheet lead free solder
2006 - cvbs decoder

Abstract: FR07
Text: device will lock to the TRS codes or the HS and VS inputs. The rise and fall times of sync, burst , 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FUNCTION VDD GND D0 (VS I/O) D1 ( HS I/O , . A 27MHz clock must be applied to PXCK pin. Low = normal operation (default). 1 = Slave to HS and VS , ) HS offset This is a 10 bit number which allows the user to offset the start of digital data input with reference to the pulse HS . H &V Slave mode control register 1 = NCO Line Reset Disable (NTSC only


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PDF VP5311B/VP5511B DS4575 VP5311/VP5511 27MHz cvbs decoder FR07
2002 - 170M

Abstract: GP64 VP531 VP531E VP551E
Text: /PALM HCNT = SN + 119 ( SN = 0 - 738) HCNT = SN + 739 ( SN = 739 - 857) NCK 0 to 131 * HS pulse , slave mode the device will lock to the TRS codes or the HS and VS inputs. The rise and fall times of , I/O) D1 ( HS I/O) D2 (FC0 O/P) D3 (FC1 O/P) D4 (FC2 O/P) D5 D6 (SCSYNC I/P) D7 (PALID I/P , applied to PXCK pin. Low = normal operation (default). SL_HS_VS 1 = Slave to HS and VS inputs , defined in GPPCTL) HSOFFM-L HSOFF9-0 HS offset This is a 10 bit number which allows the user to


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PDF VP531E/VP551E DS4573 VP531/VP551 27MHz VP531 170M GP64 VP531E VP551E
Supplyframe Tracking Pixel