The Datasheet Archive

HDSL2 datasheet (3)

Part Manufacturer Description Type PDF
HDSL2 DT Magnetics International Transformer Approved for use with ADIs AD930 Chipset Original PDF
HDSL2 Intel HDSL2 Modem Chip Set Original PDF
HDSL2 Pulse Engineering LINE TRANSFORMER For Use with GlobeSpan Chipset Original PDF

HDSL2 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2001 - fireberd 6000a manual

Abstract: ttc fireberd 6000A reference manual rj11 to db9 rj11 to db25 fireberd zener DB3 C209 fireberd 6000a schematics TTC 6000a schematic rj48 to db9 fireberd 6000a schematic
Text: for E1. The MCLK source is selected through the HDSL2 software. The HDSL2-T1 Evaluation system is , TTC Fireberd 6000A for HDSL2-Framed mode using the digital interface. Power supply and COM port , HDSL2 Evaluation System for T1 Applications - LXDHDSL2-T1 Developer Manual January 2001 As of January 15, 2001, this document replaces the Level One document known as HDSL2 Evaluation System , respective owners. HDSL2 Evaluation System for T1 Applications - LXDHDSL2-T1 Developer Manual


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PDF CON10B CSB25 fireberd 6000a manual ttc fireberd 6000A reference manual rj11 to db9 rj11 to db25 fireberd zener DB3 C209 fireberd 6000a schematics TTC 6000a schematic rj48 to db9 fireberd 6000a schematic
2001 - sk70743

Abstract: HDSL2 SK70742 SK70740 SK70741 SK70744 adsl psd mask
Text: combine POTS and HDSL2? HDSL2's PSD, known as OPTIS, is designed around T1 transport applications. As , is growing at 20-30% per year ­ so we will continue to see business in HDSL2. 6 Frequently , used for HDSL2? The framing structure is currently based on ANSI contribution T1E1.418-2000. Q13 , HDSL2 Frequently Asked Questions January 2001 Order Number: 249381-001 As of January 15, 2001, this document replaces the Level One document known as HDSL2 - FAQ. Information in this document is


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PAM16

Abstract: Metalink PAM-16 HDSL2 MTH2405 SDSL AFE
Text: MtH2405 SDSL2/ HDSL2 Dual Transceiver (Product Brief) Advanced Multi-Mode DSLTM Integration Key Features : Dual SDSL2/ HDSL2 Transceiver Metalink's MtH2405 Chipset Solution implements a low power Dual SDSL2/ HDSL2 transceiver. Each transceiver implements PAM 4, 8, 16 line codes with trellis coded , power consumption and a small real estate. Superior Performance The Metalink Dual SDSL2/ HDSL2 , Voice and Data With a minimal transmission delay of less than 0.5 msec., Metalink's SDSL2/ HDSL2 Dual


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PDF MtH2405 MtH2435 256-pin PAM16 Metalink PAM-16 HDSL2 SDSL AFE
2001 - PAM16

Abstract: SK70741 PAM-16 SK70740 SK70742 INTEL CLOCK AND DATA RECOVERY
Text: product brief Intel SK70740, SK70741, SK70742 ® HDSL2 Data Pump and Framer Chip Set Product Overview Intel Internet Exchange Architecture ® Intel® has developed an HDSL2 data pump and , three-chip solution supports the ANSI HDSL2 standard and is capable of delivering 10 -7 BER performance in , HDSL2 modulation scheme. The power spectral density (PSD) of the transmit signal conforms to the OPTIS template, which ensures that HDSL2 does not interfere with preexisting services such as T1, ISDN, HDSL


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PDF SK70740, SK70741, SK70742 USA/0101/1K/ASI/DC PAM16 SK70741 PAM-16 SK70740 SK70742 INTEL CLOCK AND DATA RECOVERY
2001 - DSX Access Systems

Abstract: No abstract text available
Text: The result is HDSL2. HDSL2 is the acronym for High-bit-rate (high-speed) Digital Subscriber Line, generation 2. In a nutshell, HDSL2 provides the same performance as its predecessor HDSL, but on a single , coding are not supported by any standard and fall short of HDSL2's 12,000 feet of reach. The Intel , application brief HDSL2 High-speed Digital Subscriber Line, generation 2 Product Description , delivery. The new technology requirements were to: The performance expectations for HDSL2 presented


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PDF USA/0101/1K/ASI/DC DSX Access Systems
2000 - Not Available

Abstract: No abstract text available
Text: T1 over HDSL2_4.qxd 8/3/00 12:58 PM Page 1 T1 over HDSL2 The future of Digital Subscriber Line technology T1 over HDSL2_4.qxd 8/3/00 12:58 PM Page 2 T1 over HDSL2 : The , over HDSL2_4.qxd 8/3/00 12:58 PM Page 3 T1 over HDSL2 : The future of Digital Subscriber , , connecting to the CSU used to terminate the T1. 3 T1 over HDSL2_4.qxd 8/3/00 12:58 PM Page 4 , regular T1 interface. A typical HDSL T1 over HDSL2_4.qxd 8/3/00 12:58 PM Page 5 T1 over


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PDF 0700/OC/AO/SK/PP/2 NP1745
1999 - 4148NX

Abstract: SK70742 SK70741 EOC17 e.oc3 SK70742QE e.oc1 SK70740 80C51 500E
Text: DATA SHEET MARCH 2000 Revision 2.3 SK70742 HDSL2 FEC/Framer General Description Features Level One's HDSL2 chip set provides synchronous fullduplex transmission over a single twisted pair. The SK70742 combines the functions of HDSL2 Frame Mapping and Forward Error Correction (FEC) in , · · · Meets requirements for ANSI T1E1.418 · HDSL2 Frame Correction Mapping and , 5 Volt tolerant input pins · Data buffering and rate adaption between the T1 and HDSL2 line rate


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PDF SK70742 SK70742 SK70741 SK70741 SK70742-R2 4148NX EOC17 e.oc3 SK70742QE e.oc1 SK70740 80C51 500E
2001 - intel batch MARKING

Abstract: intel i960 batch MARKING SK70742 SK70744HE SK70744 SK70742QE SK70741HE SK70741 SK70740HE SK70740
Text: HDSL2 Product Family Specification Update September 2001 The HDSL2 products may contain design , changes to them. The HDSL2 products may contain design defects or errors known as errata which may cause , Specification Update HDSL2 Product Family Contents Contents Revision History , . 14 HDSL2 Product Family Specification Update 3 Revision History Revision History , . Specification Update HDSL2 Product Family Preface Preface This document is an update to the


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PDF SK70742 intel batch MARKING intel i960 batch MARKING SK70744HE SK70744 SK70742QE SK70741HE SK70741 SK70740HE SK70740
2001 - pam modulator demodulator circuit

Abstract: Trellis HDSL2 SK70740 SK70744 regenerator
Text: product brief Intel SK70740/SK70744 HDSL2 Modem Chip Set ® Product Overview The Intel® SK70740/SK70744 chip set is an ANSI HDSL2 modem that provides symmetric full-duplex, T1 transmission , Interlocking Spectrum (OPTIS) power spectral density (PSD). This HDSL2 modem solution consists of two chips , within the HDSL2 frame. A synchronous TDM interface allows the chip set to be used with common T1 , CS JTAS D/A WR, DS REGISTERS PAM PROCESSOR ALE, A<7> RSER DESCRAMBLER HDSL2


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PDF SK70740/SK70744 SK70740/SK70744 USA/0101/7K/ASI/DC pam modulator demodulator circuit Trellis HDSL2 SK70740 SK70744 regenerator
2001 - D link schematic circuit diagram adsl modem board

Abstract: tms 3874 schematic circuit diagram adsl modem board water level control block diagram fec 34 afe 1000 AFE LINE DRIVER automatic water level controller circuit diagram DIGITAL water level indicator water level control circuit diagram
Text: provides frame mapping, transceiver, and line interface functions for single pair HDSL2. The SK70740/44 , SK70740/44 HDSL2 Modem Chip Set Datasheet The SK70740 and SK70744 chip set provide full-duplex , consists of two ICs that provide the HDSL2 modem solution: s SK70740HE - Analog Front End (AFE) s , Coded PAM modulator/demodulator. HDSL2 utilizes shaped PAM-16 modulation to minimize interference into , other services. The frame mapping function inserts and recovers the HDSL2 overhead. Interrupt alarms


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PDF SK70740/44 SK70740 SK70744 SK70740HE SK70744HE MO-112. SK70744HE D link schematic circuit diagram adsl modem board tms 3874 schematic circuit diagram adsl modem board water level control block diagram fec 34 afe 1000 AFE LINE DRIVER automatic water level controller circuit diagram DIGITAL water level indicator water level control circuit diagram
2001 - smd ND

Abstract: TH101
Text: 51264R 50517R Appl i cati on Orio n IDSL Analo g fro nt e nd Analo g fro nt e nd HDSL2 HDSL2 MDSL MDSL IDSL HDSL2 HDSL2 IDSL-M2B1Q MSDL-HMS g . SHDSL Turns Rati on PRI :SEC 5. 4: 1 2: 1 2: 1 2: 1 2. 2: 1


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PDF 51264R 50517R 50711R 50864R 51081R 51074R 51128R 51075R 51197R 51166R smd ND TH101
2001 - PAIRGAIN

Abstract: HDSL2 adsl psd mask T1E1 viterbi algorithm Adtran T1.413 ADSL standard HDSL 120 TR-28 trellis code modulation 5/6 decoder scheme trellis 5/6 decoder
Text: of the various services was compared when disturbed by either HDSL or HDSL2. Table 2 shows the , HDSL2 Overcomes the Impairments of the Local Loop White Paper January 2001 Order Number: 249346-001 As of January 15, 2001, this document replaces the Level One document HDSL2 Overcomes the , whatsoever for conflicts or incompatibilities arising from future changes to them. The HDSL2 may contain , owners. White Paper HDSL2 Overcomes the Impairments of the Local Loop Contents 1.0


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2001 - automatic water level controller circuit diagram

Abstract: water level controller circuit diagram water level control circuit diagram water level indicator using microcontroller water level control block diagram WATER LEVEL CONTROLLER Xm-19 intel batch MARKING FEC Encoder DIGITAL water level indicator
Text: SK70742 HDSL2 FEC/Framer Datasheet Intel's HDSL2 chip set provides full-duplex transmission over a single twisted pair. The SK70742 combines the functions of HDSL2 Frame Mapping and Forward , ANSI T1E1.418 HDSL2 Frame Mapping and Forward Error Correction Operates from a single 3.3 V supply 5 Volt tolerant input pins Data buffering and rate adaption between the T1 and HDSL2 line rate , January 15, 2001, this document replaces the Level One document SK70742 - HDSL2 FEC/Framer. Order


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PDF SK70742 SK70742 SK70741 SK70742QE MO-112. automatic water level controller circuit diagram water level controller circuit diagram water level control circuit diagram water level indicator using microcontroller water level control block diagram WATER LEVEL CONTROLLER Xm-19 intel batch MARKING FEC Encoder DIGITAL water level indicator
2001 - hdsl modem chipset

Abstract: SK70740 SK70744 PAM16
Text: product brief Intel SK70740/SK70744 HDSL2 Modem Chipset ® Product Description The Intel® SK70740/SK70744 chipset is an ANSI HDSL2 modem that provides symmetric full-duplex, T1 transmission over , Interlocking Spectrum (OPTIS) power spectral density (PSD). This HDSL2 modem solution consists of two chips: s The core of the transceiver/framer is a Trellis Coded PAM modulator/demodulator. HDSL2 , access devices s Wireless access systems SK70744 TFSYNC TCLK TSER HDSL2 TX FRAMER


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PDF SK70740/SK70744 SK70740/SK70744 PAM-16 USA/0301/1K/ASI/DC hdsl modem chipset SK70740 SK70744 PAM16
2002 - gs2237-208-001p

Abstract: GS3137-08T gs3137 gs2237 SHDSL gs3137 GS2237-208 GS3137-08-T globespan gs3137 GS3137-08 GS3137 ILD2
Text: UTOPIA Level 2 or single-channel ATM over UTOPIA Level 1 is supported for SHDSL, SDSL 2B1Q, and HDSL2. , ) G2237-208-041PT B2 (SHDSL/ HDSL2 ) G2237-208-041PT C1 (SHDSL/ HDSL2 ) XDSL2TM SDSL, HDSL2 , or SHDSL - , including SDSL, HDSL2 , and SHDSL, using population options for optimization. · · Data Sheet The , T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL Reference design compatible with Bellcore GR-1089, IEC , SDSL, HDSL2 , and SHDSL - ILD2 Data Sheet Introduction The GlobespanVirata DSL chip sets support


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PDF G2216-208-041PF G2214-208-041DF G2237-208-041PT GS3137-08T DO-009643-DS, gs2237-208-001p GS3137-08T gs3137 gs2237 SHDSL gs3137 GS2237-208 GS3137-08-T globespan gs3137 GS3137-08 GS3137 ILD2
2000 - g991

Abstract: afe 1000 SDSL AFE VC7220 ECHO line canceller IC phone VIRATA HDSL2 bd3800
Text: DSL Access Modem using the Aluminum Digitally Tuned Analog Front End HDSL2 /G.shdsl/2B1Q SDSL , the PAM transceiver, HDSL2 framer, and 512 state Trellis encoder and decoder with a high performance , . Aluminum is optimized for the ANSI HDSL2 standard for T1 transport. It can also be used for testing and , is used for T1 transport in HDSL2 mode. Aluminum also supports 2B1Q SDSL. The Power Spectral , DSL Access Multiplexers (DSLAMs) s T1 HDSL2 CSU/DSUs Ordering Information s T1 HDSL2


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PDF 192Kbps 304Mbps 192Kbps 32-bit P0800V1 17F-2 g991 afe 1000 SDSL AFE VC7220 ECHO line canceller IC phone VIRATA HDSL2 bd3800
2002 - DSL Line TRANSFORMER and Hybrid

Abstract: transformer interface with 8051 SDSL AFE TR-28
Text: Multi-Mode Transceiver M28976 Two Full-Rate T1/E1 Payloads Over a Single G.shdsl/ HDSL2 /SDSL Link , operation and guaranteed interoperability with legacy software control. systems including HDSL2 , SDSL , and software handle the extended tion. In addition, it complies with the ANSI HDSL2 standard , and HDSL2 supports data rates from 192 Kbps to 4.6 Mbps, and requires only frame formats and EOC , for high density and manufacturability ­ HDSL2 (ANSI T1.418) ­ SDSL/2B1Q (AutoBaud) ­ Option A


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PDF M28976 M28976 32-level Nx64K DSL Line TRANSFORMER and Hybrid transformer interface with 8051 SDSL AFE TR-28
2001 - RJ48 pin out

Abstract: SK70742 741i AN110 BZX84C4V7LT1 AD8016ARB SK70740 SK70741 AD8016 48c60
Text: HDSL2 - System Design and Chip Set Overview Application Note January 2001 Order Number , and names are the property of their respective owners. Application Note HDSL2 - System Design , .12 1 2 3 4 5 6 7 8 9 10 11 12 HDSL2 Block Diagram , Tables Application Note 3 HDSL2 - System Design and Chip Set Overview 1.0 General Description Intel's HDSL2 chip set provides synchronous, full duplex transmission over a single twisted pair


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PDF AN110. RJ48 pin out SK70742 741i AN110 BZX84C4V7LT1 AD8016ARB SK70740 SK70741 AD8016 48c60
2000 - TC-PAM

Abstract: tcpam encoder Modulation TC-PAM G.SHDSL LOOP modems LXT776 G.SHDSL Line Driver SHDSL SHDSL chips PAM time division multiplexing
Text: LXT776 also includes an integrated line driver that supports G.SHDSL, ETSI SDSL, and HDSL2 standards , Error Correction G.SHDSL: International Symmetric High-speed DSL standard (developed by ITU) HDSL2 , supports G.SHDSL, ETSI SDSL, and HDSL2 digital subscriber line applications, and data rates from 192Kbps , HDSL2 REMOTE TERMINAL T1 SERVICE DSX-1 Figure 3: HDSL ACCESS BAY INTEROFFICE NETWORK DSX-1 HDSL2 ACCESS BAY HDSL SPAN LEVEL ONE PARTS = HDSL2 DATA PUMP = T1 TRANSCEIVER (LIU


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PDF LXT776 192Kbps PB-1013 USA/0600/7K/ASI/CR TC-PAM tcpam encoder Modulation TC-PAM G.SHDSL LOOP modems G.SHDSL Line Driver SHDSL SHDSL chips PAM time division multiplexing
1999 - Campus Italia Vol 1

Abstract: 071 0039 adc interfacing with 8051 asm code satellite l300 ZipWire2 8051 opcode sheet l300 THA 12065 P2A13 8051 ps2 keyboard asm program
Text: . . . . . . . . . . . . . . . . . . . . . . . 14-3 HDSL2-Single Pair . . . . . . . . . . . . . . . , parametric information contains target parameters that are subject to change. CN8980 ZipWire2 HDSL2 /SDSL , for HDSL2 T1 transport and meets all the current requirements of the emerging ETSI standards for SDSL , OPTIS-based HDSL2 through software modifications. The ZipWire2 device has a two- or three-chip architecture , almost any frame format. In particular, it supports the ANSI HDSL2 and ETSI HDSL1 frame formats. It


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PDF CN8980 Campus Italia Vol 1 071 0039 adc interfacing with 8051 asm code satellite l300 ZipWire2 8051 opcode sheet l300 THA 12065 P2A13 8051 ps2 keyboard asm program
2003 - RAD-AG30-8T

Abstract: HRE-420 HRE-422 HPS-448 HFA-357 HRE-450-L3B ENC-819-CG3P-VA3 HRE-602 RAD-BA30-16 HLU-319
Text: HiGain® Wideband 3190 Integrated SONET/DS3 Multiplexer for HDSL/ HDSL2 /HDSL4 The HiGain , 's industry-standard HDSL, HDSL2 or HDSL4 distribution system. The Wideband implementation maintains full compatibility , Multiplexer for HDSL/ HDSL2 /HDSL4 The WBS-3190 multiplexes 28 HDSL lines into a single DS3 or STS-1 line , -1 DS3 STS-1 (HXU) DSX-1 HDSL2 LU HDSL2 Remote DS1 104732AE DSX-1 LOOP THROUGH T1 , Integrated SONET/DS3 Multiplexer for HDSL/ HDSL2 /HDSL4 · Supports extensive loopbacks on DS3 and DS1


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PDF WBS-3190) 104732AE RAD-AG30-8T HRE-420 HRE-422 HPS-448 HFA-357 HRE-450-L3B ENC-819-CG3P-VA3 HRE-602 RAD-BA30-16 HLU-319
2000 - afe 1000

Abstract: SDSL ADC DAC bd3800 SDSL AFE AFE LINE DRIVER line echo cancellation ic G.SHDSL VC8220 VC822 SHDSL transformer
Text: Aluminum-AFE Product Profile August 2000 KEY FEATURES Description Aluminum-AFE is an HDSL2 , Aluminum DSL Processor HDSL2 /G.shdsl/2B1Q SDSL compliant AFE Programmable data rates from 192Kbps to , also provides a power down mode for standby operation. Aluminum-AFE conforms to the HDSL2 OPTIS , ) Environmental s T1 HDSL2 CSU/DSUs s s T1 HDSL2 M13 line cards 350 mW normal operation (290mW without AES) s HDSL2 /G.shdsl repeaters s 0.35 micron CMOS 3.3V/2.5V supply s


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PDF 192Kbps 304Mbps 192Kbps 17F-2 afe 1000 SDSL ADC DAC bd3800 SDSL AFE AFE LINE DRIVER line echo cancellation ic G.SHDSL VC8220 VC822 SHDSL transformer
1999 - PAM16

Abstract: tms echo cancellation PAM-16
Text: DATA SHEET AUGUST 1999 SK70741 HDSL2 PAM Transceiver General Description Level One's HDSL2 chip set provides synchronous fullduplex transmission over a single twisted pair. The SK70741 is the heart of the HDSL2 chip set and is optimized to meet the ANSI HDSL2 standard for T1 transport. The device supports data rates from 144 kbps to 2064 kbps. PAM-16 modulation is used to achieve these rates , to crosstalk and interference to other systems. This allows HDSL2 to coexist with other transport


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PDF SK70741 SK70741 PAM-16 PAM16 tms echo cancellation
2005 - 51576

Abstract: 51576R 5-0517 shdsl IC 51166R
Text: Application Orion IDSL Analog front end Analog front end HDSL2 HDSL2 MDSL MDSL IDSL HDSL2 HDSL2 IDSL-M2B1Q


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PDF 51576R 50517R 50711R 50864R 51081R 51074R 51128R 51075R 51197R 51166R 51576 5-0517 shdsl IC
2001 - circuit diagram of PAM transmitter and receiver

Abstract: motorola 68000 microprocessor datasheet SK70741 intel 68000 INSTRUCTION SET 80C51 SK70740 SK70742 motorola 68000
Text: SK70741 HDSL2 PAM Transceiver Datasheet Intel's HDSL2 chip set provides full-duplex transmission over a single twisted pair. The SK70741 is the heart of the HDSL2 chip set and supports the ANSI T1E1.418 HDSL2 standard for T1 transport. PAM-16 modulation is used to achieve this rate over standard , crosstalk and interference to other systems. This allows HDSL2 to coexist with other transport technologies , - HDSL2 PAM Transceiver. Order Number: 249238-001 January 2001 Information in this document


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PDF SK70741 SK70741 PAM-16 SK70741HE MO-112. circuit diagram of PAM transmitter and receiver motorola 68000 microprocessor datasheet intel 68000 INSTRUCTION SET 80C51 SK70740 SK70742 motorola 68000
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