The Datasheet Archive

HC-49/U4B Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1996 - 74l500

Abstract:
Text: 2 13 12 10 9 1 U4A 8 74L500 3 5 5 4 4 U4B 6 74L500 U2B 6 74L520


Original
PDF HCTL-1100 M-025 HCTL-1100 74l500 schematic diagram brushless motor control LOGIC OF 74L500 ic 74LS08 74Ls08 truth table Encoder interface with HCTL-1100 M109 B1 motorola 74LS08 74LS08 UC3657
1996 - oszillator

Abstract:
Text: V 4.9 V 5.1 V 5.3 V 5.5 V Vcc Bild 8: Änderung der Frequenz bei , U4B sicherzustellen. Das Meßgerät arbeitet nach folgendem Verfahren: Man geht davon aus, daß im Ruhezustand das Flipflop U4A gesetzt ist (Q = Low) und das Flipflop U4B zurückgesetzt ist (Q = High). Durch eine positive Flanke der Eingangsfrequenz fin2 wird das Flipflop U4B gesetzt, welches darauf das Tor , das Flipflop U4B zurückgesetzt wird. Damit ist die eigentliche Messung beendet. Bezeichnet man die


Original
PDF EB100B EB100 SN74S124 SN74S124. oszillator STYROFLEX EB100B til306 EB100 SN74S124 SN74S124 ANALOGE quarzoszillator R/SN74S124 keramikkondensator
Not Available

Abstract:
Text: Link 10uF RTS 74AHC12 HA DSHA E U4B 4 GND TXD RXD RTS CTS VDD Pairing Status


Original
PDF LM-400 LM400 LM400
Not Available

Abstract:
Text: PAIRI G STATUS DSR DTR RST 1 0R R3 CTS 12 74AHC12 6 U4B 3 U4A 0R


Original
PDF LM-400 LM400 LM400
1995 - STYROFLEX CAPACITOR

Abstract:
Text: -1.5 % 4.5 V 4.7 V 4.9 V 5.1 V 5.3 V 5.5 V Vcc Figure 8: Change of frequency with , flip-flops U4A and U4B are sufficiently steep. The measurement equipment operates as follows: It is first assumed that in the quiescent state the flip-flop U4A is set (Q = Low), and that the flip-flop U4B is reset (Q = High). The flip-flop U4B will be set as a result of a positive edge of the input frequency , input frequency fin1, and thus the flip-flop U4B is reset. At this point the measurement is essentially


Original
PDF EB100E SN74S124 SN74S124. SN74S124 STYROFLEX CAPACITOR applications of blocking oscillator TIL306 EB100E 10 bit Controlled Oscillator Styroflex capacitors STYROFLEX PUT Oscillator Voltage Controlled Oscillator
2001 - TCI 550 antenna

Abstract:
Text: ipolar2 U3 D G 201 4 5 U4B +15V -15V +5V 0 +15V 4k OUT + +15V 8 LF147 4 , )1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: + 49 -(0)8141-349-087, Fax: + 49 -(0)8141-349-089 Sweden -


Original
PDF PW-8X075P6 PW-83075P6 PW-84075P6 PW-85075P6 1-800-DDC-5757 A5976 TCI 550 antenna 3 phase induction motor fpga
1999 - CD4049 equivalent

Abstract:
Text: { RN } 6 OUT 7 L F 147 Vn Vcc Vp I_C_b ipolar2 U3 D G 201 { RS } 5 IC + U4B Vp 0 4k


Original
PDF 75Amps 50Amps PW-8X075P6 PW-83075P6 PW-83075 PW-84075 PW-85075 1-800-DDC-5757 A5976 CD4049 equivalent cd4049 CD4049 ic 16 pin diagram IRML2402 cd4050 cd4049 pin out CD4049 PIN DIAGRAM PW-8X075P6 lm741 cross reference
2001 - CD4050 equivalent

Abstract:
Text: ipolar2 U3 D G 201 4 5 U4B +15V -15V +5V 0 +15V 4k OUT + +15V 8 LF147 4 , )1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: + 49 -(0)8141-349-087, Fax: + 49 -(0)8141-349-089 Sweden -


Original
PDF PW-8X075P6 PW-83075P6 PW-84075P6 PW-85075P6 Half--5757 A5976 CD4050 equivalent amplifier using lm741 CD4049 ic 16 pin diagram LS132 resolver sensor
RCA H 715

Abstract:
Text: - 161 - 451 7B Dual 64 Bit Static Shift Register 1 '6 1 15 ■8MB »a Xr-y 64t' / h X2 f Ail umi' asij x'JTMl' 7o. 3X-r— rifjAjA-HTflb. "a / !./j:\)Xv>7 r cfio. 16, 32, 43. u4b ' y rftaifis VDD typ ■ax *fî m « tr 5V 100 200 ns DIP SOP 10V 50 100 ns ¡* 15V , into 17-fllt Oata at tap antarad into 33-Bit Oata at tap antarad into 49 -Bit Hlgh impadanca 15V ns


OCR Scan
PDF UPD4517BC HD14517B 16-BITTAP 32-BtT 48-BIT 64-8IT MN4517B 47High HCC4517B 16-Bit RCA H 715 CD4517B HEF4517BP MC14517B SCL4517B
u7a capacitor

Abstract:
Text: CKE1* 88 DQ50 108 VSS 128 DQ59 9 DQ3 29 A0 49 DQ13 69 S0 , DQ4 DQ5 DQ6 DQ7 DQ0 DQM CS DQ1 U0B DQ2 DQ3 DQ36 DQ37 DQ38 DQ39 DQ5 DQM CS DQ6 U4B , ,U3B U4A, U4B CLK1 U5A,U5B U6A,U6B RAS U7A,U7B BA0, BA1, A0-A10/AP, A11, : SDRAMs U0A-U7A


Original
PDF SL64G8G16M4G-A10V SL64G8G16M4G-A10V 54-pin 400-mil 144-pin 100MHz cycles/64ms A0-A10/AP, u7a capacitor
CD4049 PIN DIAGRAM

Abstract:
Text: } 0 0 { RP } 11 VSS GND V- { RS } V+ 5 IC + U4B Vn Vcc Vp L F 147 - 0


Original
PDF 75Amps 50Amps PW-8X075P6 PW-83075P6 PW-84075P6 PW-85075P6 1-800-DDC-5757 A5976 CD4049 PIN DIAGRAM CD4049 equivalent CD4049 ic 16 pin diagram CD4049 PIN DIAGRAM Circuit HC 148 TRANSISTOR CD4050 ic 16 pin diagram UC1625 application CD4049 ic 8 pin diagram 60v 50a dc motor controller circuit
2000 - need 22k Potentiometers

Abstract:
Text: down. U4B performs similar a similar scaling, but R18 offset the control signal so that U2 is , approximately double the slope of the control signal. As the output of U4B continues to approach -0.6 V, D1 , 133k U4B 5532 V- Figure 1: Pan pot circuit Figure 3 shows the deviation from ideal constant


Original
PDF certai25degC 30degC 35degC 20degC 25degC need 22k Potentiometers 22k LOG pot 10K potentiometer linear 1N4148
U-4A

Abstract:
Text: Two Electrode Gas Tube Surge Arrester Part Number: U-4A / U-4B Applications: Transient Voltage Surge Suppression (TVSS) Cable Telephony Products Modems/Cable Modems Broadband/CATV/Coaxial Protectors xDSL Modems and Peripherals Building Entry/Outside Plant U-4A (Units: mm) 0.8 U-4B 30 ± 2.0 SANKOSHA UL 497B Recognized UL File E140906 Non-Radioactive 100% Lead-Free (RoHS Compliant) Low Capacitance Proven Performance ISO 9001 Certified World Renowned Quality Marking U


Original
PDF E140906 U-4A U-4B 230V U-4B
2000 - 22k LOG pot

Abstract:
Text: down. U4B performs similar a similar scaling, but R18 offset the control signal so that U2 is , approximately double the slope of the control signal. As the output of U4B continues to approach -0.6 V, D1 , 6 7 Lout 5 U3B 5532 V- 7 5 R19 U4B 43k DP3T2 5532 R20 R17 R18 Inv. 133k


Original
PDF 20degC 25degC 30degC 35degC 22k LOG pot 6133k 1N4148 22k pot datasheets L25D MOTORIZED Potentiometer 10k need 22k Potentiometers resistor* 10k "log" pot
1997 - FDC37C651

Abstract:
Text: is shown in Figure 2. This implementation shows the addition of U7A, U7B, U4B , U4C, U8A, U8B, and U9A to implement the DMA option. In this implementation, U4B and U4C are used to add the DMA control to


Original
PDF FDC37C6XX FDC37C651/625, FDC37C661/662, FDC37C663/664, FDC37C665/666. FDC37CXX SIO6001 FDC37C651 FDC37C665/666 u-7B
M9-1-473

Abstract:
Text: M7-1-473 SW2 DSS108 9 10 11 12 13 14 15 16 VDD1 49 50 51 52 53 54 , 4 R6 51 4 IMCLK DVDD 49 47K 50 52 53 55 54 PLL2 DVSS PLL0 , 42 41 RX0 43 NC 46 45 44 RX1 NC VCOM U4B IPS0 4 R20 LED2 , HC- 49 /U 24.576MHz 10 29 7 7 74HC14 14 JP8 HIF3G-50P-2.54DSA (2x1) 6 VDD1 , XTI-TX X2 HC- 49 /U 11.2896MHz 8 14 7 7 6 32 1 5 HIF3G-50P-2.54DSA (2x1


Original
PDF AKD4126-A] AKD4126-A AK4126Rev AKD4126-AAK4126 AK4126 AK4114 10pin M9-1-473 64-128fs DSS108 XTIJP16 AKD4126-A AK4114 HIF3G hl24 JP13 JP24
2000 - AK4345

Abstract:
Text: =44.1kHz, fin=0dBFs 06/18/07 09: 49 :36 +1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A , =96kHz 06/18/07 10: 49 :42 +1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A +0.1 +0 -0.1 , 10u + C7 0.1u VCC C8 E C5 0.1u + E 5p D AK4112B-MCKO1 D X1 HC- 49 , U4B 74AC74 14 10 VCC 14 4 E VCC PR E 6 U7C 74HC14 9 8 U7D 74HC14


Original
PDF AKD4345-A] AKD4345-A AK4345 AKD4345-ADIT24 96kHz AK4345A/D DIRAK4112B/BNC 74LVC541 AK4345 74LVC541A-PDN 74AC163 AK4112 AK4112B-LRCK JP15 AKD4345-A AKD4345 AK4112B-MODE AK4112B
2000 - AK4345

Abstract:
Text: =44.1kHz, fin=0dBFs 06/18/07 09: 49 :36 +1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A , =96kHz 06/18/07 10: 49 :42 +1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A +0.1 +0 -0.1 , + C7 0.1u VCC C8 E C5 0.1u + E 5p D AK4112B-MCKO1 D X1 HC- 49 /U , 12 JP11 (3x2) U4A 74AC74 7 13 EXT J1 BNC-R-PC U4B 74AC74 14 10 VCC


Original
PDF AKD4344-A] AKD4344-A AK4344 AKD4344-ADIT24 96kHz AK4344A/D DIRAK4112B/BNC 74LVC541 AK4345 74LVC541A-PDN AK4112B AK4344 AKD4344 AKD4344-A
104 csk

Abstract:
Text: 36 37 36 39 40 41 42 43 44 45 46 47 48 49 50 51 52 104 103 10 2 10 1 10 0 99 96 97 96 95 94 94 92 91 , /Oe, & W Ec GND O gp W Eo I/O 59 I/O 56 l/ 0 57 I/O « I/O « l/Oe* 1/0« l/Os > GND I/ Û4B I/O49


OCR Scan
PDF CYM1910 the60 I/O49 104 csk
xtal 12MHz

Abstract:
Text: 10ppm 627 49 12.9 (Diameter) Frequency Range (Fundamental) Major Application TV, VCR Telecom , 10.8 x 4.5 x 3.35 Metal Can DIP X'tal 3.5MHz ~ 90MHz 10ppm 2x8 163 49 3.4 XO-Type (U3) 10.8 x 4.5 x 2.45 Metal Can DIP X'tal 3.5MHz ~ 90MHz 10ppm 2x8 119 49 2.5 , XJ-Type ( U4B ) 13.4 x 4.85 x 3.0 49U/S SMD X'tal 3.5MHz ~ 35MHz 10ppm 2x8 195 65 3.0


Original
PDF DEMO-05-B 180MHz 10ppm 25ppm 50ppm 26Mhz 160Mhz 135Mhz 55Mhz xtal 12MHz Xtal 8Mhz crystal Crystal Oscillators 3.57MHz XTAL 8mHZ XTAL 24MHZ 50PPM xtal 3.57MHz CRYSTAL SMD 8MHZ XTAL 8MHZ SMD CRYSTAL SMD 12MHZ X-TAL 12MHZ
2004 - smsc

Abstract:
Text: Implementation 2 is shown in Figure 2. This implementation shows the addition of U7A, U7B, U4B , U4C, U8A, U8B, and U9A to implement the DMA option. In this implementation, U4B and U4C are used to add the DMA


Original
PDF FDC37C6XX FDC37C651/625, FDC37C661/662, FDC37C663/664, FDC37C665/666. FDC37CXX SIO6001 smsc
MHDR1X8

Abstract:
Text: 1 2 3 4 5 6 7 8 DIL24 Device Adapter R9 - + OUT1_u 3 OUT2 In+ In- 7 R0 VDD U1B TS924 6 - + In- 1 OUT2_u VDD U1A TS924 2 R10 5 In+ OUT1 O1_u U4B TS922 3 In+ 1 + - VDD R0 A VDD In- R20 OUT5_u - + OUT6_u 8 10 OUT6 In+ In- 14 R0 TS922 R21 12 In+ U4A VDD , PB10 PB11 Vss1 Vdd1 SW3 0R 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49


Original
PDF DIL24 TS924 TS922 100nF lds3985xx30 BC817 MHDR1X8 STM32F102R8 EKSTM32 mhdr MHDR1X USBLC6-2P6 usbdm PC13-TAMPER-RTC header 12x2 STM32F102
2000 - 74hct05

Abstract:
Text: detects the start condition (falling edge of SMBDATA when SMBCLK is high). Flip-flop U4B detects the , of U1A also resets flip-flop U4B . Because the IBM PC parallel port has a limited number of inputs , CLK Q 8 HOLDING_CLOCK J1­15 10 S U4B J2­8 J2­9 J2­10 J2­11 J2­12 MASK_ALERT1 MASK_ALERT2 MASK_START


Original
PDF
1998 - zener diode 6.8v

Abstract:
Text: Flip-flop U4A detects the start condition (falling edge of SMBDATA when SMBCLK is high). Flip-flop U4B , high at the input of U1A also resets flip-flop U4B . Because the IBM PC parallel port has a limited , ALERT1 U4B Q Q R1 47k R2 47k +5V 74HC74 R D CLK S SMBSUS R11


Original
PDF 1N5235B 1N5229B 1N4148 47knt zener diode 6.8v quad 74HC04 NOT GATE datasheet of 74HC74 ic diode U3d zener diode 68v 74HC04 NOT GATE P116 Diode 74HC05 74HC04 74HC74
2000 - 74HC05

Abstract:
Text: edge of SMBDATA when SMBCLK is high). Flip-flop U4B detects the falling SMBCLK edge when enabled, and , uses U1A to assert and then release SMBCLK. A logic high at the input of U1A also resets flip-flop U4B , CAPTURE_ENABLE 12 D U3D U1F OC 74HC05 12 SMBCLK DECOUPLING CAPACITOR +5V 11 CLK Q 8 HOLDING_CLOCK J1­15 10 S U4B


Original
PDF
Supplyframe Tracking Pixel