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DS4064

Abstract: SP5658S MP14 SP5658 SP5658F SP5659 low noise divide by 2 2,7GHz PRESCALER
Text: SP5658 2.7GHz 3-Wire Bus Controlled Frequency Synthesiser Advance Information Supersedes October 1996 Media IC Handbook HB3923-2 CHARGE PUMP 1 14 DRIVE V EE CRYSTAL SP5658F The SP5658 is a single chip frequency synthesiser designed for tuning systems up to 2.7GHz. The RF preamplifer contains a divide by two prescaler which can be disabled for applications up to 2GHz so enabling , version s Four switching ports in 16 pin version s Pin compatible with SP5659 I 2 C bus low phase noise


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PDF SP5658 HB3923-2 SP5658F SP5658 lock5658S SP5659 SP5658F/KG/MP1S SP5658S/KG/MP2S SP5658F/KG/MP1T SP5658S/KG/MP2T DS4064 SP5658S MP14 SP5658F low noise divide by 2 2,7GHz PRESCALER
1999 - how dsp is used in radar

Abstract: Mitel Semiconductor ON SEMICONDUCTOR 613 PDSP16256 PDSP16350 hilbert
Text: PDSP16256/PDSP16350 Evaluation System Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 DS3854 - 2.0 May 1996 DAC FILTER 1 PDSP16256 ADC FILTER 2 PDSP16256 DAC , (dependent on sample rate and configuration) I Decimate by 2 mode Signal Generation I High resolution sine , PDSP DFDS-1 PDSP DFDS- 2 PDSP DFDS-3 PDSP DFDS-4 20MHz 20MHz 1MHz 1MHz 8 bits 8 bits 12 bits 12 bits 1 2 1 2 All options include the following IBM PC compatible hardware and


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PDF PDSP16256/PDSP16350 HB3923-2 DS3854 PDSP16256 PDSP16350 PDSP16350 PDSP16256 how dsp is used in radar Mitel Semiconductor ON SEMICONDUCTOR 613 hilbert
2001 - Not Available

Abstract: No abstract text available
Text: Supersedes October 1996 Media IC Handbook HB3923-2 CHARGE PUMP 1 14 DRIVE V EE CRYSTAL , 2 C bus low phase noise synthesiserPP s ESD protection (Normal ESD handling procedures should be , RF INPUTS PHASE COMP PROGRAMMABLE DIVIDER : 2 /1 13 BIT COUNT F pd F comp REFERENCE DIVIDER See Table 1 :-16/17 OSC 2 CRYSTAL 1 14 DE 4 BIT COUNT 16 , INTERFACE DATA INTERFACE 7 P3 8 9 10 P2 P1/0C P0/OP Fig. 2 SP5658S block diagram 2 T0


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PDF SP5658 HB3923-2 SP5658F SP5658
Not Available

Abstract: No abstract text available
Text: dvance Inform ation sem ic o n d u c to r Supersedes O ctober 1996 M edia IC Handbook HB3923-2 The , switching ports in 14 pin version Four switching ports in 16 pin version Pin compatible with SP5659 I 2 C , SO) (Tubes, 16 lead SO) (Tape and Mounted) (Tape and Mounted) SP5658 Fig. 2 SP5658S block diagram 2 SP5658 ELECTRICAL CHARACTERISTICS T amb = - 2 0 °C to + 80°C, Vcc = + 4.5V to + 5.5V , RF input capacitance 13, 14 Data, Clock, Enable & Disable 50 Q. PF 3,4,5,6 2


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PDF SP5658 HB3923-2 SP5658
1999 - varactor APPLICATION

Abstract: DS4064 MP14 SP5658 SP5658F SP5658S SP5659
Text: 1996 Media IC Handbook HB3923-2 CHARGE PUMP 1 14 DRIVE V EE CRYSTAL SP5658F The , version s Four switching ports in 16 pin version s Pin compatible with SP5659 I 2 C bus low phase noise , PROGRAMMABLE DIVIDER : 2 /1 13 BIT COUNT F pd F comp REFERENCE DIVIDER See Table 1 :-16/17 OSC 2 CRYSTAL 1 14 DE 4 BIT COUNT 16 CHARGE PUMP CHARGE PUMP DRIVE CO 1 , 9 10 P2 P1/0C P0/OP Fig. 2 SP5658S block diagram 2 T0 1 BIT LATCH FLOCK 11


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PDF SP5658 HB3923-2 SP5658F SP5658 varactor APPLICATION DS4064 MP14 SP5658F SP5658S SP5659
H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S
Text: IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION s Fully , average rate up to 2 Mbits per second. The bursty nature of the input, together with the fact that each , RD VMUX ERROR VMUX EVENT HOST INTERFACE DATA PMD 2 :0 SIDE INFORMATION STROBE DATA , active low signals do not appear with a bar in the main body of the text. 2 FRAME ALIGNMENT The H , expected. 2 ) The codeword is not valid for its context, causing no match to be obtained. Each variable


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PDF VP2614 HB3923-2 DS3735 VP2615 VP2614 H261 VP2611 VP2612 VP510 VP520S
Not Available

Abstract: No abstract text available
Text: Handbook HB3923-2 The SP5658 is a single chip frequency synthesiser designed for tuning systems up to , V cc LOCK PORTPO/OP M P14 f t FEATURES C o m p le te 2 .7 G H z s in g le c h ip s , itc h in g p o rts in 16 pin v e rs io n P in c o m p a tib le w ith S P 5 6 5 9 I 2 C b u s lo w p h , lead SO) (Tape and Mounted) (Tape and Mounted) SP5658 Fig. 2 SP5658S block diagram 2 SP5658 ELECTRICAL CHARACTERISTICS T amb = - 2 0 °C to + 80°C, Vcc = + 4.5V to + 5.5V. Reference


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PDF SP5658 DS4064 HB3923-2 SP5658
2002 - H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S "Overflow detection"
Text: VP2612 Video Multiplexer Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 , for the Transmission buffer. 2 NOTE: "Barred" active low signals do not appear with a bar in , DMODE 3:0 FEC Block DATA FROM VP2611 DATA VALID Figure 2 . DBUS Timing least two cycles , DMODE3:0 are valid, as shown in Figure 2 . The sequence of events, and the duration of each event, is , represents an actual quantisation level between 2 and 62, in steps of 2 and as defined in H.261. Horizontal


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 DS3511 H261 VP2612 "Overflow detection"
2001 - H.261 encoder chip

Abstract: No abstract text available
Text: IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION The VP2614 Video , an average rate up to 2 Mbits per second. The bursty nature of the input, together with the fact that , ALIGNMENT VALIDITY CHECK VARIABLE LENGTH DECODE VP2615 INTER FACE SIDE INFORMATION PMD 2 :0 D7:0 DM3:0 DCLK , body of the text. 2 VP2614 VIDEO LOCK Once the VP2614 has locked to the H261 frames it will , Group of Blocks ( GOB ) Start Code is not present when expected. 2 ) The codeword is not valid for its


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PDF VP2614 HB3923-2 DS3735 VP2614 VP2615 H.261 encoder chip
2003 - H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S
Text: IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION s Fully , average rate up to 2 Mbits per second. The bursty nature of the input, together with the fact that each , RD VMUX ERROR VMUX EVENT HOST INTERFACE DATA PMD 2 :0 SIDE INFORMATION STROBE DATA , active low signals do not appear with a bar in the main body of the text. 2 FRAME ALIGNMENT The H , expected. 2 ) The codeword is not valid for its context, causing no match to be obtained. Each variable


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PDF VP2614 HB3923-2 DS3735 VP2615 VP2614 H261 VP2611 VP2612 VP510 VP520S
2006 - VP2611

Abstract: VP2612 VP2614 VP2615 VP510 VP520S H261
Text: Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 , rate of 4 Mbits per second, but with an average rate up to 2 Mbits per second. The bursty nature of , Converter HD7:0 HA3:0 CEN WR RD VMUX ERROR VMUX EVENT HOST INTERFACE DATA PMD 2 :0 , NOTE: "Barred" active low signals do not appear with a bar in the main body of the text. 2 , ) Start Code is not present when expected. 2 ) The codeword is not valid for its context, causing no


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PDF VP2614 HB3923-2 DS3735 VP2615 VP2611 VP2612 VP2614 VP510 VP520S H261
2002 - H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S 16 line to 4 line coder multiplexer
Text: VP2612 Video Multiplexer Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 , for the Transmission buffer. 2 NOTE: "Barred" active low signals do not appear with a bar in , DMODE 3:0 FEC Block DATA FROM VP2611 DATA VALID Figure 2 . DBUS Timing least two cycles , DMODE3:0 are valid, as shown in Figure 2 . The sequence of events, and the duration of each event, is , represents an actual quantisation level between 2 and 62, in steps of 2 and as defined in H.261. Horizontal


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 DS3511 H261 VP2612 16 line to 4 line coder multiplexer
2002 - H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S
Text: IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION s Fully , average rate up to 2 Mbits per second. The bursty nature of the input, together with the fact that each , RD VMUX ERROR VMUX EVENT HOST INTERFACE DATA PMD 2 :0 SIDE INFORMATION STROBE DATA , active low signals do not appear with a bar in the main body of the text. 2 FRAME ALIGNMENT The H , expected. 2 ) The codeword is not valid for its context, causing no match to be obtained. Each variable


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PDF VP2614 HB3923-2 DS3735 VP2615 VP2614 H261 VP2611 VP2612 VP510 VP520S
V2611

Abstract: "TOPS" data bus sytem "sub data bus" TXA11 VP520S VP510 VP2615 VP2614 VP2612 VP2611
Text: VP2612 Video Multiplexer Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 , for the Transmission buffer. 2 NOTE: "Barred" active low signals do not appear with a bar in , DMODE 3:0 FEC Block DATA FROM VP2611 DATA VALID Figure 2 . DBUS Timing least two cycles , DMODE3:0 are valid, as shown in Figure 2 . The sequence of events, and the duration of each event, is , represents an actual quantisation level between 2 and 62, in steps of 2 and as defined in H.261. Horizontal


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 DS3511 V2611 "TOPS" data bus sytem "sub data bus" TXA11 VP2612
Not Available

Abstract: No abstract text available
Text: , HB3923-2 VP2614 H.261 Video De-Multiplexer DS3735 - 3.2 October 1996 FEATURES Fully integrated , data up to a peak rate of 4 Mbits per second, but with an average rate up to 2 Mbits per second. The , body of the text. 2 VP2614 VIDEO LOCK Once the VP2614 has locked to the H261 frames it will , Group of Blocks ( GOB ) Start Code is not present when expected. 2 ) The codeword is not valid for its , Decoder to use data from the previously decoded picture. Note that Video LINE (LCLK) Ons min 2 0 +10ns


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PDF HB3923-2 VP2614 DS3735 VP2615 VP2614
1999 - Pin and function compatible VP2612

Abstract: VP520S VP510 VP2615 VP2614 VP2612 VP2611 H261 TXA11 16 line to 4 line coder multiplexer
Text: VP2612 Video Multiplexer Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 , for the Transmission buffer. 2 NOTE: "Barred" active low signals do not appear with a bar in , DMODE 3:0 FEC Block DATA FROM VP2611 DATA VALID Figure 2 . DBUS Timing least two cycles , DMODE3:0 are valid, as shown in Figure 2 . The sequence of events, and the duration of each event, is , represents an actual quantisation level between 2 and 62, in steps of 2 and as defined in H.261. Horizontal


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 DS3511 Pin and function compatible VP2612 VP2612 H261 TXA11 16 line to 4 line coder multiplexer
2001 - TXA13

Abstract: No abstract text available
Text: VP2612 Video Multiplexer Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 , buffer. Active low chip enable for the Transmission buffer. 2 VP2612 monitoring is, however, done , on DBUS4:0 (DBUS4 is MSB). This represents an actual quantisation level between 2 and 62, in steps of 2 and as defined in H.261. Horizontal MV : If motion compensation was used the horizontal component , max 25ns max DATA FROM VP2611 DMODE 3:0 DATA VALID 20ns max DATA VALID Figure 2 . DBUS Timing


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PDF VP2612 HB3923-2 DS3511 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 TXA13
1996 - Not Available

Abstract: No abstract text available
Text: Digital Video & DSP IC Handbook, HB3923-2 ) FEATURES DESCRIPTION s Fully integrated H.261 video , rate of 4 Mbits per second, but with an average rate up to 2 Mbits per second. The bursty nature of , Converter HD7:0 HA3:0 CEN WR RD VMUX ERROR VMUX EVENT HOST INTERFACE DATA PMD 2 :0 , NOTE: "Barred" active low signals do not appear with a bar in the main body of the text. 2 , is not present when expected. 2 ) The codeword is not valid for its context, causing no match to be


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PDF VP2614 DS3735 HB3923-2) VP2615 VP2614
Not Available

Abstract: No abstract text available
Text: 1995 Digital Video & DSP IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION , . The VP2614 will accept data up to a peak rate of 4 Mbits per second, but with an average rate up to 2 , the main body of the text. 2 FRAME ALIGNMENT The H.261 continuous bitstream is split into , is not present when expected. 2 ) The codeword is not valid for its context, causing no m atch to be , Video LINE (LCLK) LINE l/P DATA 0ns min X 2 0 +10ns min DATA VALID X DE-MUX


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PDF VP2614 HB3923-2 DS3735 VP2615 VP2614
VMUX

Abstract: No abstract text available
Text: June 1995 Digital Video & DSP 1C Handbook, HB3923-2 ) FEATURES The VP2612 Video Multiplexer forms , DMODE3.0 are valid, as shown in Figure 2 . The sequence of events, and the duration of each event, is , Represents an actual quantisation level be­ tween 2 and 62, in steps of 2 and as defined in H:261 , motion compensation was not used this is a don’t care value. 235 37bfl522 0 0 2 7477 bfl7 , I ( 2 c y c le s ) Coded Block Pattern : This byte contains a 6 bit linear code that indicates


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PDF VP2612 HB3923-2) VP2612 27MHz VP2611 VMUX
2001 - Not Available

Abstract: No abstract text available
Text: IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION The VP2614 Video , an average rate up to 2 Mbits per second. The bursty nature of the input, together with the fact that , ALIGNMENT VALIDITY CHECK VARIABLE LENGTH DECODE VP2615 INTER FACE SIDE INFORMATION PMD 2 :0 D7:0 DM3:0 DCLK , body of the text. 2 VP2614 VIDEO LOCK Once the VP2614 has locked to the H261 frames it will , Group of Blocks ( GOB ) Start Code is not present when expected. 2 ) The codeword is not valid for its


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PDF VP2614 HB3923-2 DS3735 VP2614 VP2615 VP261include
Not Available

Abstract: No abstract text available
Text: version in June 1995 Digital Video & DSP 1C Handbook, HB3923-2 ) FEATURES DESCRIPTION ■Fully , average rate upto 2 Mbits per second. The bursty nature of the input, together with the fact that each , is not present when expected. 2 ) The codeword is not valid for its context, causing no match to be , me system c'oc< pence Fig 2 : Line Interface Timing 244 Lock is actually lost and re-gained , enabled by a Data Valid signal. Detailed timing information is given in Figure 2 . Maximum input


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PDF DS3735 VP2614 HB3923-2) VP2615 VP2614
Not Available

Abstract: No abstract text available
Text: .261 VIDEO DE-MULTIPLEXER (Supersedes version, in June 1995 Digital Video & DSP 1C Handbook, HB3923-2 , to a peak rate of 4 Mbits per second, but with an average rate up to 2 Mbits per second. The bursty , / sec. Maximum peak input rates of 4 Mbit / sec. 100 pin quad flatpack SSOCIATED PRODUCTS V P 2 6 1 , bar in the main body of the text. 243 37bSSSB 0 0 2 7 4 0 5 753 VP2614 VIDEO LOCK Once , present when expected. 2 ) The codeword is not valid for its context, causing no match to be obtained


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PDF VP2614 HB3923-2) VP2614 37bflS22
2006 - philips hd6

Abstract: H261 "Overflow detection" VP520S VP510 VP2615 VP2614 VP2612 VP2611 "TOPS"
Text: in June 1995 Digital Video & DSP IC Handbook, HB3923-2 FEATURES s Fully integrated H261 , to Transmission buffer. TXE1 Active low chip enable for the Transmission buffer. 2 NOTE , VP2611 DATA VALID Figure 2 . DBUS Timing least two cycles, and DCLK is high for minimum of one cycle. The rising DCLK edge occurs one cycle after DBUS7:0 and DMODE3:0 are valid, as shown in Figure 2 , macroblock is provided on DBUS4:0 (DBUS4 is MSB). This represents an actual quantisation level between 2 and


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PDF VP2612 HB3923-2 VP2611 64kbits/s VP2615 VP2614 VP520S VP510 philips hd6 H261 "Overflow detection" VP2612 "TOPS"
1996 - Not Available

Abstract: No abstract text available
Text: version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 ) FEATURES DESCRIPTION s Inputs , external DRAM 1. RW2 Read/Write control for the external DRAM 2 . OE1 Output Enable control for , external DRAM 2 N/C if 256k DRAMs in use. CBUS7:0 Bi-directional data bus for use by a , ] ADD LOW PASS FILTER FRAME STORE CONTROLLER ADR[7:0] FS[15:0] OE1 OE2 2 RW1 RW2 RAS CAS Fig 2 : Simplified Block Diagram YUV[7:0] VP2615 OPERATION OF MAJOR BLOCKS Frame Store


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PDF VP2615 DS3479 HB3923-2) VP2615
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