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Not Available

Abstract:
Text: -2.1 P D S P 1 6 3 1 8 /P D S P 1 6 3 1 8 A COMPLEX ACCUMULATOR (Supersedes version in December 1993 Digital Video & Digital Signal Processing 1C Handbook, HB3923-1 ) The PDSP16318 contains two Independent , 4 3 2 1 AC84 Fig. 1 Pin connections - bottom view (AC84 - PSA) APPLICATIONS â , R o rA S I ASX1 0 0 1 1 DEL 0 1 0 1 A+B A A -B B -A MS A port input Delayed A port input Real and Imag* Mux Control 0 1 Delay Mux Control 0 1 ALU Function


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PDF DS3706-2 HB3923-1) PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A 256ps. PDSP16318/13618A PDSP16318/CO/AC
Not Available

Abstract:
Text: 1993 Digital Video & Digital Signal Processing 1C Handbook, HB3923-1 ) The PDSP16112/PDSP16112A will , achieve a 20MHz (PDSP16112A) or 10MHz (PDSP16112) throughput. 1 i * « S 8 7 â , Logic Unit PDSP16318 40MHz Address Generator PDSP16330 Pythagoras Processor Fig. 1 Pin connections , FUNCTION (PGA Package - AC120) 1 2 3 4 5 6 7 8 A VCC GND PI07 PI10 , GND 8 7 6 5 4 3 118 117 116 49 50 51 52 53 54 55 56 57 58 59 63 1 16 2 10


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PDF DS3708 PDSP16112/PDSP16112A HB3923-1) PDSP16112/PDSP16112A 20MHz PDSP16112A) 10MHz PDSP16112) PDSP16112 10MHz-PGA)
Not Available

Abstract:
Text: version in December 1993 D igital Video & Video D igital Signal Processing 1C Handbook, HB3923-1 ) The , Correlation/Convolution ■84 Pin PGA or QFP packages V 11 10 9 8 7 6 5 4 3 2 1 AC84 Fig. 1 Pin connections - bottom view (AC84 - PGA) ASSOCIATED PRODUCTS PDSP16112 16 x 12 Complex Multiplier PDSP16116 1 6 x 1 6 Complex Multiplier PDSP1601 ALU and Barrel Shifter PDSP16330 Pythagoras , /16318A A SRor ASi ASX1 0 0 1 1 DEL 0 f 1 0 1 A+B A A -B B -A MS B port input


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PDF DS3706 PDSP16318/PDSP16318 HB3923-1) PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A PDSP16318/13618A PDSP16318A/B0/AC
1995 - "transient capture"

Abstract:
Text: , HB3923-1 ) FEATURES alternatively from a high speed (20MHz) complex (16 + 16 bit) digital data input , to develop proprietary software control if required. Fig. 1 PDSP16510 Evaluation Board , Board is shown in figure 1 . A TTL level input trigger can be used to enable the Input Capture , maximum data input rate depends on the source of the data (ADC or complex digital input). Tables 1 to 3 detail the possible data rates. PDSPFTDS Fig.2 Free Run Mode Table 1 . Free Run Mode Complex


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PDF DS3227 PDSP16510 HB3923-1) 20MHz) PDSP16510 10MHz, PDSP16330 "transient capture" Block Floating Point Implementation 64x256 gec plessey semiconductor PDSP16330 plessey PDSP16540 SP973T8
Not Available

Abstract:
Text: Handbook, HB3923-1 ) The PDSP16330 is a high speed digital CMOS IC that converts Cartesian data (Real and , GEC PLESSEY ADVANCE INFORMATION S t* M I C O IN D U C T O K S P D S P 1 6 3 3 0 /A /B , © © K © © © ,L © © B 7 © © © © © 6 5 4 3 2 1 AC84 Fig. 1 Pin connections - bottom view (PGA) a/ \ _ II? s& dl ûj^ûuuiJTJuuuuuuuuouDujJiK UO , ■I 37bf l S52 00244=51 255 I I 384 PDSP16330/A/B 1 . J >ms OM □ 7 8 E GD N L iR a


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PDF HB3923-1) PDSP16330 20MHz. PDSP16330 PDSP16330A PDSP16330B
Not Available

Abstract:
Text: 1C Handbook, HB3923-1 ) The PDSP16318 contains two independent 20-bit Adder/ Subtracters combined , © © © © D 8 7 Fig. 1 Pin connections 6 - 5 4 3 2 1 K L AC84 bottom view (AC84 - PGA) ASSOCIATED PRODUCTS PDSP16112 PDSP16116 PDSP1601 PDSP16330 1 6 x 1 2 Complex Multiplier 1 6 x 1 6 Complex Multiplier ALU and Barrel Shifter Pythagoras Processor 405 , 0 1 1 DEL 0 1 0 1 Delay Mux Control 0 1 ALU Function A port input D elayed


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PDF PDSP16318/PDSP16318A HB3923-1) PDSP16318 20-bit 20MHz PDSP1631 PDSP16112A 0027b4S PDSP16318/13618A PDSP16318A/B0/AC
Not Available

Abstract:
Text: (Supersedes version in December 1993 Digital Video & Digital Signal Processing IC Handbook, HB3923-1 ) The , © @ © ® H © © © © 5 4 3 2 1 J AC84 APPLICATIONS ■■â , A S S O C IA T E D P R O D U C T S PDSP16112 1 6 X 1 2 Complex Multiplier PDSP16116 1 6 X 1 6 , . S1 so 0 0 x1 0 1 X2 1 0 x4 1 1 x8 S caling Factor FO R M , number range is from 0 to 2 when the scaling fa cto r is set at x 1 . 434 ;■37bflS22


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PDF PDSP16330/A/B HB3923-1) PDSP16330 20MHz. PDSP16330A PDSP16330B 10MHZ 20MHZ 25MHZ
1996 - PDSP16330

Abstract:
Text: Handbook, HB3923-1 DS3884 - 1.3 September 1996 The PDSP16330 is a high speed digital CMOS IC that , Dissipation at 10MHz 84-pin PGA or 100 pin QFP Package or 84 LCC 11 10 9 8 7 6 5 4 3 2 1 AC84 Fig. 1 Pin connections - bottom view (PGA) APPLICATIONS Digital Signal Processing Digital Radio , 0 0 x1 0 1 x2 1 0 x4 1 1 x8 FORM This input selects the format , 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 M7 M6 M5 M4 M3 M2 M1 M0


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PDF PDSP16330/A/B HB3923-1 DS3884 PDSP16330 20MHz. 10MHz AC84 PDSP16330A PDSP16318 PDSP16116 PDSP16112 m15m diode GG 26 PDSP16350
1995 - Not Available

Abstract:
Text: , HB3923-1 ) The PDSP16318 contains two independent 20-bit Adder/ Subtractors combined with accumulator , Power Dissipation 84 Pin PGA or QFP packages L 11 10 9 8 7 6 5 4 3 2 1 AC84 Fig. 1 Pin connections - bottom view (AC84 - PGA) APPLICATIONS s s s s High speed Complex , simplified block diagram 1 PDSP16318/16318A Fig. 3 Block diagram FUNCTIONAL DESCRIPTION The , adder bits are selected the output data is padded with zeros. ABSOLUTE MAXIMUM RATINGS (Note 1


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PDF PDSP16318/13618A DS3708 PDSP16318/PDSP16318A HB3923-1) PDSP16318 20-bit 20MHz PDSP16318As PDSP16112A
diode GG 71

Abstract:
Text: Handbook, HB3923-1 ) The PDSP16330 is a high speed digital CMOS IC that converts Cartesian data (Real and , 10 9 8 7 6 5 4 3 2 1 AC84 Fig. 1 Pin connections - bottom view (PGA) 1 / OND SI SO r I7-M0 k , Port output is invalid. S1 so Scaling Factor 0 0 X1 0 1 x2 1 0 x4 1 1 x8 The output number range , GG LC Function Pin No. AC GG LC Function F3 91 1 M7 L9 23 29 YO A9 59 57 X1 G3 92 2 M6 L10 24 30 , GND A5 68 66 XI0 L1 1 11 GND F10 37 39 GND B5 69 67 X11 K2 6 12 Vcc G10 38 40 OEP C5 70 68 X12 K3 7


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PDF ds3884 PDSP16330/A/B HB3923-1) PDSP16330 20MHz. 10MHz 10MHZ diode GG 71 Stand Alone FFT Processor diode GG 79 l3915 diode GG 64 ERMA 110 L92329 LCC Package m15m m15m0
Not Available

Abstract:
Text: 1C Handbook, HB3923-1 ) The PDSP16112/PDSP16112A will multiply a complex (16 +16) bit word by a , ) throughput. 1 2 3 4 « t 7 • • 10 11 12 . 1J FEATURES â , Pythagoras Processor F ig . 1 P in c o n n e c tio n s - to p v ie w ( A C 1 2 0 - P G A ) F ig . 2 M u , internally connected to Vcc by 10k (nominal) resistors. PIN OUT - PIN TO FUNCTION (PGA Package - AC120) 1 , 1 16 2 10 30 62 81 90 119 PI00 PI01 PI02 PI03 PI04 PI05 PI06 PI07 PI08 YR00


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PDF DS3706 PDSP16112/PDSP16112A HB3923-1) PDSP16112/PDSP16112A 20MHz PDSP16112A) 10MHz PDSP16112) 20MHz PDSP16112A
DS4064

Abstract:
Text: SP5658 2.7GHz 3-Wire Bus Controlled Frequency Synthesiser Advance Information Supersedes October 1996 Media IC Handbook HB3923-2 CHARGE PUMP 1 14 DRIVE V EE CRYSTAL SP5658F The SP5658 is a single chip frequency synthesiser designed for tuning systems up to 2.7GHz. The RF , Cable tuning systems s Communications systems CHARGE PUMP 1 16 DRIVE CRYSTAL V EE , PORT P3 PORT P0/OP PORT P2 PORT P1/OC MP16 Fig. 1 Pin connections ­ top view ORDERING


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PDF SP5658 HB3923-2 SP5658F SP5658 lock5658S SP5659 SP5658F/KG/MP1S SP5658S/KG/MP2S SP5658F/KG/MP1T SP5658S/KG/MP2T DS4064 2,7GHz PRESCALER low noise divide by 2 MP14 SP5658F SP5658S
Not Available

Abstract:
Text: VIDEO MULTIPLEXER (Supersedes version in December 1993 Digital Video & DSP 1C Handbook, HB3923-1 ) The , CIF/QCIF Converter HDTO H A S .« CEN WH BO O VER FLO W S TU FF Fig. 1 VP2612 , the data type present on the data bus D7:0. Polarities are given in Table 1 . DCLK A strobe for , be transmitted. DBUS4 and DBUS7 are not used. Table 1 This is to warn the system processor that , period (see Table 1 ). The output of the VP2611 is structured such that the data on DBUS7:0 and DMODE3iO


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PDF DS3511 VP2612 HB3923-1) VP2612 27MHz VP2611 37fciÃ
1995 - Not Available

Abstract:
Text: version in December 1993 Digital Video & Digital Signal Processing IC Handbook, HB3923-1 ) The PDSP16340 , is illustrated in Fig. 1 , and uses the formula:Xr = R cos(Ø) Xi = R sin(Ø) In look-up table mode, the , Xi R Ø Xr Fig. 1 . Cartesian to Polar Coordinates Real Real (Cosine) Imaginary (Sine) Fig. 2. Simplified Block Diagram 1 PDSP16340 N PEN MODE M1 M3 M5 VDD M8 , GND XR14 XR12 XR10 VDD XR8 GND XR5 XR3 XR1 OEI OER 1 2 3


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PDF PDSP16340 DS3710 PDSP16340 HB3923-1)
Not Available

Abstract:
Text: Signal Processing 1C Handbook, HB3923-1 ) The PDSP16350 provides an integrated solution to the need for , GEC P I E S S E Y S i S E MI CONDUCTORS P ADVANCE INFORMATION D S P 1 6 , modulation modes ■84 pin PGA or 132 pin QFP Fig. 1 Block Diagram APPLICATIONS ASSOCIATED , UHF generators Signal demodulator 199 ■B7b6SSS 00 E4 S0 b 53b ■PDSP16350 1 2 , SIG GC SIG GND 1 N/C 34 N/C 67 GND 100 2 CEN 35 VOUT 68


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PDF HB3923-1) PDSP16350 PDSP16350 20MHz
Not Available

Abstract:
Text: P D S P 1 6 5 4 0 32K BUCKET BUFFER (Supersedes version in December 1993 Digital Video & Digital Signal Processing 1C Handbook, HB3923-1 ) The PDSP16540 Bucket Buffer is for use in systems which , to accept the information, which will consist of both new and old data, in amounts defined by MD2: 1 , D4:0 during reset. MD2: 1 define the amount of new data within the block length as defined above. The options MD2: 1 are 1024 (00), 512 (01), 256 (10), or the number defined in groups of 32 words by D9:5


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PDF HB3923-1) PDSP16540 37fcifl525 0D24Stm PDSP16540
1995 - PDSP16510 timing

Abstract:
Text: version in December 1993 Digital Video & Digital Signal Processing IC Handbook, HB3923-1 ) The PDSP16540 , Figure 1 . Simplified Block Diagram 1 PDSP16540 NAME TYPE SIGNAL DESCRIPTION IP31:0 I , data, in amounts defined by MD2: 1 . The flag will go in-active for one read strobe period every time , defined in groups of 32 words by the data on D4:0 during reset. MD2: 1 MD2: 1 define the amount of , MD4 F VDD DAV MD5 VDD E WS IP 0 IP 31 RES D IP 1 IP 2 IP


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PDF PDSP16540 DS3715 HB3923-1) PDSP16540 PDSP16510 timing PDSP16116 PDSP16318 PDSP16330 PDSP16340 PDSP16510 PDSP16520
Not Available

Abstract:
Text: Handbook, HB3923-1 P D S P 1 6 3 3 0 /A /B Pythagoras Processor DS3884 - 1.3 Septem ber 1996 The , © © © © ® ® © © © © © © © © © © © © © © © © © © 2 1 © © © © © © © © © © © © © © © @ © © © © © © © @ © 9 © 8 © 7 © 6 © 5 © 4 © 3 , is invalid. S1 0 0 1 1 so 0 1 0 1 Scaling Factor x1 x2 x4 x8 FORM This input selects the , B1 C1 D2 D1 E3 E2 E1 F2 GG Function 91 92 93 94 95 96 97 98 99 100 1 6 7 8 9 10 11 12 13 14 15 16 , ) = -40°C to + 85°C Vcc (Commercial) = 5.0V + 5%, Vcc (Industrial and Military) = 5.0V + 1 %, GND = 0V


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PDF HB3923-1 DS3884 PDSP16330 20MHz. 10MHz PDSP16330) 20MHz
1995 - CORDIC MAGNITUDE

Abstract:
Text: (Supersedes version in December 1993 Digital Video & Digital Signal Processing IC Handbook, HB3923-1 ) The , is illustrated in Fig. 1 , and uses the formula:Xr = R cos(Ø) Xi = R sin(Ø) In look-up table mode , Magnitude CORDIC PROCESSOR ARRAY Magnitude Adjust Xi R Ø Xr Fig. 1 . Cartesian to Polar Coordinates Real Real (Cosine) Imaginary (Sine) Fig. 2. Simplified Block Diagram 1 , P4 P3 XI2 XI3 C P2 P1 XI0 XI1 B P0 A CLOCK 1 XR15 XR13


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PDF PDSP16340 DS3710 HB3923-1) PDSP16340 CORDIC MAGNITUDE how dsp is used in radar PDSP16116 PDSP16256 PDSP16318 PDSP16330 PDSP16350 PDSP16510
COS15

Abstract:
Text: Digital Video & DSP IC Handbook, HB3923-1 DS3711-2.3 September 1996 The PDSP16350 provides an integrated , phase accum register i£ cordic processor array SIN cos Fig. 1 Block Diagram ASSOCIATED PRODUCTS , SIG GC SIG GC SIG 1 N/C 34 N/C 67 GND 100 GND 2 CEN 35 VOUT 68 DIN17 101 VDD 3 N/C 36 DIN33 69 N/C , ground pins. All must be connected. VCC Four +5V pins. All must be connected. 4 Table 1 . Pin , 2N These equations illustrate some very important features of direct digital synthesisers :- 1


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PDF PDSP16350 HB3923-1 DS3711-2 PDSP16350 418/ED/51624/001 GPD00274 COS15 din32 AC84 D3318 K217 N1137 PDSP16488A PDSP16510A
Not Available

Abstract:
Text: Processing 1C Handbook, HB3923-1 ) The PDSP16340 can be configured to perform either a coordinate conversion , Si GEC PLESSEY ADVANCE INFORMATION S E M I C O N D U C T O R S P D S P 1 6 3 4 0 POLAR , (Real, Imaginary). The translation is illustrated in Fig. 1 , and usesthe formula:Xr = R cos(0) XI = R , GC SIG GC SIG GND 1 N/C 34 N/C 67 GND 100 2 MEN 35 VOUT , pins. All pins must be connected. Table 1 . Signal description 194 37L&SSS 0G 24501 T54


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PDF HB3923-1) PDSP16340 SP16340 20MHz
1995 - PDSP16116

Abstract:
Text: Signal Processing IC Handbook, HB3923-1 ) The PDSP16540 Bucket Buffer is for use in systems which , Converter 32 BIT O/P DATA Figure 1 . Simplified Block Diagram 1 PDSP16540 NAME TYPE , information, which will consist of both new and old data, in amounts defined by MD2: 1 . The flag will go , . MD2: 1 MD2: 1 define the amount of new data within the block length as defined above. The options , IP 0 IP 31 RES D IP 1 IP 2 IP 29 IP 30 C IP 3 IP 4 IP 27


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PDF PDSP16540 DS3715 HB3923-1) PDSP16540 PDSP16116 PDSP16318 PDSP16330 PDSP16340 PDSP16510 PDSP16520
Not Available

Abstract:
Text: , HB3923-1 ) The P D S P 16350 provides an integrated solution to the need for very accurate, digitised , GEC PLESS EY w S I' M I C O IN IJ V C T Ü K Î) P D S P 1 6 3 5 0 l/Q SPLITTER , accuracies betterthan 0.001 Hz Fig . 1 B lo c k D ia g ra m Amplitude and Phase modulation modes 84 pin , SIG 1 N/C 34 N/C 67 2 CEN 35 VOUT 68 GND 100 GND DIN17 , +5V pins. All must be connected. T able 1 . P in D e scrip tio n 443 37bfl522 DQ27b7S b


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PDF HB3923-1) fl522 PDSP16350 37bflS22 0027b62
full adder 2 bit ic

Abstract:
Text: dvance Inform ation Supersedes version in Decem ber 1993 Digital Video & DSP IC Handbook, HB3923-1 , © © © © © © © © © © © © © © © © @ © © @ © © © © © © 11 10 9 8 7 6 5 4 3 2 1 AC84 Fig. 1 Pin connections - bottom view (AC84 - , (GG100) 3 PDSP16318/16318A ASR orASI ASX1 ASX0 0 0 1 1 0 1 0 1 ALU Function A+ B A A-B B-A DEL 0 1 Delay Mux Control A port input Delayed A port input MS 0 1 Real and Iniag Mux Control B pot inputì Del mux output C accumu latori D accumualtor sai) S2 S1 Adder result so 0 1 0 1 0 1 0 1


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PDF PDSP16318/PDSP16318A DS3708 HB3923-1 PDSP16318 20-bit PDSP16318As PDSP16112A full adder 2 bit ic pin diagram of full adder using Multiplexer IC "Overflow detection" AC84 ALU of 4 bit adder and subtractor
Not Available

Abstract:
Text: Handbook, HB3923-1 PDSP16330/A/B Pythagoras Processor DS3884 - 1.3 Septem ber 1996 The PDSP16330 is , D U C TS PDSP16112 1 6 X 1 2 Complex Multiplier PDSP16116 1 6 X 1 6 Complex Multiplier PDSP16318 , © © @ 9 8 7 © © © © © © 6 5 4 3 2 1 AC84 Fig. 1 Pin connections - bottom view (PGA) GG100/R , for the period that the M Port output is invalid. S1 0 0 1 1 so 0 1 0 1 Scaling Factor x1 x2 , Function 91 92 93 94 95 96 97 98 99 100 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 M7 M6 M5 M4


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PDF HB3923-1 PDSP16330/A/B DS3884 PDSP16330 20MHz.
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