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GSA-V1/32 Datasheets Context Search

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2007 - Not Available

Abstract: No abstract text available
Text: CSA Certified, UL Recognized AMPERE RATING VOLTS GSA-V1/100 1/100A GSA1/100 GSA-V1/ 32 1/32A GSA1/ 32 GSA-V1/16 1/16A GSA1/16 GSA-V1/10 1/10A GSA1/10 GSA-V1/8 1/8A GSA1/8 GSA-V15 , GSA3 GSA-V3-2/10 3-2 /10A GSA3-2/10 GSA-V3-1/2 3-1/2A GSA3-1/2 GSA-V4 4A GSA4 GSA-V5 5A GSA5 , RATING VOLTS GDL-V1/100 1/100A GDL1/100 250V GDL-V1/ 32 1/32A GDL1/ 32 250V GDL-V4/100 4 , -2/10 3-2 /10A 250V GDL3-2/10 GDL-V4 4A GDL4 250V GDL-V5 5A GDL5 250V GDL-V6 6A GDL6 250V


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PDF 250VAC 125VAC GSA-V1/100 1/100A GSA1/100 GSA-V1/32 1/32A GSA1/32 GSA-V1/16
2012 - Not Available

Abstract: No abstract text available
Text: 2-8/10A 3A 3-2 /10A 3-1/2A 4A 5A 6A 6-1/4A 7A 8A 10A 12A 15A 20A 25A 30A 250V 250V , /10A 1-8/10A 2A 2-1/4A 2-1/2A 2-8/10A 3A 3-2 /10A 4A 5A 6A 6-1/4A 7A 8A 10A 12A 15A 20A


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PDF 1/16A 250VAC, 125VAC, 32VAC, 125VAC
PR2A10DC6K-1.5 10A 250VAC

Abstract: GSR-V3/4 GDL20 GAB7 FUSE 3A 125V Fuse 250V 2A GGX2 GAB15 ceramic fuse 20A 250V GGM1
Text: , UL Recognized AMPERE RATING VOLTS GSA-V1/100 1/100A GSA1/100 GSA-V1/ 32 1/32A GSA1/ 32 , -2/10 3-2 /10A GSA3-2/10 GSA-V3-1/2 3-1/2A GSA3-1/2 GSA-V4 4A GSA4 GSA-V5 5A GSA5 GSA-V6 6A , VOLTS GDL-V1/100 1/100A GDL1/100 250V GDL-V1/ 32 1/32A GDL1/ 32 250V GDL-V4/100 4/100A GDL4 , 2-1/2A GDL2-1/2 250V GDL-V2-8/10 2-8/10A 250V GDL2-8/10 GDL-V3 3A GDL3 250V GDL-V3-2/10 3-2 , /100 GGC-V1/ 32 1/32A GGC1/ 32 GGC-V1/16 1/16A GGC1/16 GGC-V1/10 1/10A GGC1/10 GGC-V1/8 1/8A


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PDF 250VAC 125VAC GSA-V1/100 1/100A GSA1/100 GSA-V1/32 1/32A GSA1/32 GSA-V1/16 PR2A10DC6K-1.5 10A 250VAC GSR-V3/4 GDL20 GAB7 FUSE 3A 125V Fuse 250V 2A GGX2 GAB15 ceramic fuse 20A 250V GGM1
1996 - 47c201

Abstract: TMP47C101M TMP47C101P TMP47C201M TMP47C201P TMP47C990E TMP47P201VP
Text: consultation with TOSHIBA. TOSHIBA CORPORATION 1/ 32 TMP47C101/201 Pin Assignment (Top View) Pin , Reset signal input HOLD (INT1) I/O (Input) VDD VSS 2/ 32 External interrupt 2 input , 3.2 Interval Timer · 3.3 Timer/Counters (TC1, TC2) 3/ 32 TMP47C101/201 2. Internal CPU , ] instruction execution, when the branch con- Table 2-1 Status Change of Program Counter 4/ 32 TOSHIBA , the address 000H through 3FFH are read. 5/ 32 TMP47C101/201 Figure 2-3. Program Memory Map


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PDF TLCS-47E TMP47C101/201 47C101/201 TMP47C101P, TMP47C201P, TMP47C101M, TMP47C201M TMP47C101P 47c201 TMP47C101M TMP47C101P TMP47C201M TMP47C201P TMP47C990E TMP47P201VP
CSA8.00MT

Abstract: No abstract text available
Text: Input data ' p in Output data V KK Figure 3-2 . Ports P1, P2, P3 Figure 3-3. Example of , addressing bit manipulation instructions [SET @L], [CLR @L], and [TEST @L], Table 3-2 lists the pins (I/O , 0 0 1 1 0 1 : o 0 1 Pin R70 R71 R72 R73 Table 3-2 . Relationship between L register , . PortR9 4 15-16 - TO SH IBA 3.2 4bit A/D Conversion (Comparator) Input TMP47C215/415 The , + 0.3 V V [> [>-40 to V DQ + 0.3 30 3.2 mA -12 Output Voltage V OUT3 b u n buT2


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PDF TMP47C215/415 TMP47C215N TMP47C415N 47C215/415 TLCS-470 TMP47C415N SDIP42-P-600-1 TMP47P415VN 10to33pF CSA8.00MT
CSA8.00MT

Abstract: TLCS-470 TMP47C215N TMP47C415N TMP47P415VN 47C415 R5201
Text: /TEST/TESTP/SET/CLR >1 Output data PIN VKK Figure 3-2 . Ports P1, P2, P3 47C215/415 Figure 3-3 , addressing bit manipulation instructions [SET @L], [CLR @L], and [TEST @L]. Table 3-2 lists the pins (I/O , 1110 1111 R70 R71 R72 R73 Table 3-2 . Relationship between L register contents and I/O port bits a , (SI) -Data output Control output Figure 3-7. PortR9 4-15-16 TOSHIBA TMP47C215/415 3.2 4bit A/D , 3.2 l0UT3 P1, P2, P3 - 12 '0UT4 R4, R5, R6 -25 Output Currnent (Total) 2IOUT3 P1, P2, P3 -80


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PDF TMP47C215/415 TMP47C215N TMP47C415N 47C215/415 TLCS-470 SDIP42-P-600-1 TMP47P415VN TMP47C415N CSA8.00MT TMP47P415VN 47C415 R5201
TLCS-470

Abstract: TLCS470 Transistor 7f3
Text: In p u t data O u tp u t d a ti Figure 3-2 . Ports P1, P2, P3 82 TOSHIBA AMERICA , addressing bit manipu lation instructions [SET @L], [CLR @L], and [TEST @ LJ. Table 3-2 lists the pins (I/O , < -0 LD CLR L, #0011B @L Table 3-2 Relationship Between L Register Contents and I/O Port Bits , COMPONENTS, INC. 4-Bit Microcontroller TLCS-470 TMP47C215/415 3.2 4-B it A /D Conversion , qq + 0.3 Unit V V V T.B.D. 30 3.2 -12 -25 -80 -100 600 260 (10 S) -55 to 125 -30 to 70 mW "C


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PDF TMP47C215N TMP47C415N TMP47C415N 47C215/415 TLCS470 TMP47C415F SDIP42-P-60Q TLCS-470 Transistor 7f3
Not Available

Abstract: No abstract text available
Text: -1414-0.80D t I t t It t I t t 1 33 32 31 30 29 28 27 26 25 24 2s \ RAO (OCO) 22 RA1 (T1/IC0 , Control Circuit 2.8 Interrupt Control Circuit 2.9 Reset Circuit Hardware Functions 3.1 I/O Ports 3.2 , - 0086h and the final 32 -byte space can also be used for special applications. 1000 01


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PDF TMP47E885AF TLCS-470 TMP47E885AF 64x8-bit 12-bit P-QFP44-1414-0 TMP47P885F
Not Available

Abstract: No abstract text available
Text: Table 3-2 . Port Address Assignments and Available I/O Instructions Port Address (*) 00H 0 1 02 03 04 , /TESTP/SET/CLR Input data Output data VKK Figure 3-2 . Ports P1, P2, P3 Figure 3-3 , Table 3-2 lists the pins (I/O ports) that correspond to the L register contents. Example: To clear R43 , : 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 ; 0 0 1 Pin R70 R71 R72 R73 Table 3-2 . Relationship between L , - TO SHIBA 3.2 4bit A/D Conversion (Comparator) Input TMP47C215/415 The comparator input


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PDF TMP47C215/415 TMP47C215N TMP47C415N 47C215/415 TLCS-470 TMP47C415N P-SDIP42-600-1 TMP47P415VN
Not Available

Abstract: No abstract text available
Text: 32 31 30 29 28 27 26 25 24 23 22 R41 R40 _ -R92 (SCK) -R91 (SO) -R90 (SI) -R81(T2) ~R80 , /TESTP/SET/ CLR Figure 3-2 . Ports P1, P2, P3 Figure 3-3. Example of driving a VFT 4 - , bit manipulation instructions [SET @L], [CLR @L], and [TEST @L]. Table 3-2 lists the pins (I/O ports , CLR QL ; R43< -0 Table 3-2 . Relationship between L register contents and I/O port bits L register 3 , SH IB A 3.2 4 bit AD Conversion (Comparator) Input TMP47C215/415 The comparator input is


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PDF TMP47C215/415 TMP47C215N TMP47C415N TMP47C215/415 TLCS-470 TMP47C415N P-SDIP42-600-1 TMP47P415VN
Not Available

Abstract: No abstract text available
Text: IN / TEST/TESTP/SET / CLR Figure 3-2 . Ports P1, P2, P3 Figure 3-3. 4 - 16-13 Example , indirect addressing bit manipulation instructions [SET @L], [CLR @L], and [TEST @L]. Table 3-2 lists the , 1 1 0 1 Table 3-2 . Relationship between L register contents and I/O port bits a. R4 , 16-17 1999 - 09-01 TO SHIBA 3.2 TMP47C216/416 4bit A/D Conversion (Comparator) Input The , , R80, R81, R9 3.2 ■0UT3 P1, P2, P3 - ■0UT4 Output Current (per 1 pin) P1, P2


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PDF TMP47C216/416 TMP47C216F TMP47C416F 47C216/416 TLCS-470 P-QFP44-1414-0 TMP47P416VF 768kHz
FC1028

Abstract: 1414D 47C416 TLCS-470 TMP47C216F TMP47C416F TMP47P416VF
Text: /TEST/TESTP/SET/CLR >1 Output data PIN VKK Figure 3-2 . Ports P1, P2, P3 47C216/416 Figure 3-3 , addressing bit manipulation instructions [SET @L], [CLR @L], and [TEST @L]. Table 3-2 lists the pins (I/O , 110 0 110 1 1110 1111 R70 R71 R72 R73 Table 3-2 . Relationship between L register contents and I/O , (SI) -Data output Control output Figure 3-7. PortR9 4-16-17 TOSHIBA TMP47C216/416 3.2 4bit A/D , , R82 30 mA buT2 R71 to R73, R80, R81, R9 3.2 'oUT3 P1, P2, P3 - 12 '0UT4 R4, R5, R6 -25


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PDF TMP47C216/416 TMP47C216F TMP47C416F 47C216/416 TLCS-470 QFP44-P-1414D TMP47P416VF TMP47C416F 00kH2 FC1028 1414D 47C416 TMP47P416VF
Not Available

Abstract: No abstract text available
Text: circuit ♦Peripheral hardware functions 3.1 I/O ports 3.2 Interval timer 3.3 Timer/counters (TC1, TC2 , instruction. Table 3-2 . shows the port address allocation and the input/output instructions that access the , Output latch pulse n Port H _ X Figure 3-2 . Output Timing 3.1.2 Input/Output , set, clear, or test the bit specified by the L register. Table 3.2 shows the correspondence between , 0 0 R50 0 1 0 1 R51 0 1 1 0 R52 0 Table 3-2 . 2 1


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PDF TMP47E186/187 TMP47E186M /TMP47E187M TMP47E186M/187M TMP47E186M TMP47E187M P-SOP16-300-1 16x8-bit TMP47P186M TMP47P187M
KYOCERA KSS

Abstract: KSS CXO
Text: *3 2 P*2 P*1 P*0 *; 1, 2, 3 IN / TEST/TESTP/SET/ CLR Figure 3-2 . Ports P1, P2 , ], [CLR @L], and [TEST @L]. Table 3-2 lists the pins (I/O ports) that correspond to the L register , instruction. LD L , #0011B ; S et R43 pin address to L r e g is t e r CLR QL ; R43<-0 Table 3-2 . Relationship , read upon execution of an input instruction. Figure 3-7. Port R9 3.2 4 bit AD Conversion , , R5, R6 P1, P2, P3 R4, R5, R6 -0.3 to V qq + 0.3 V qd -40 to V qd + 0.3 30 3.2 12 Output


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PDF TMP47C216/416 TMP47C216F TMP47C416F TMP47C216/416 TLCS-470 TMP47C416F P-QFP44-1414-0 TMP47P416VF KYOCERA KSS KSS CXO
Not Available

Abstract: No abstract text available
Text: P12 P22 P13 P21 VSS R50 K01 P10 O X X CO 33 32 31 30 29 28 27 26 25 24 , Interrupt Controller 2.9 Reset Circuit Peripheral Hardware Function 3.1 Input/O utput Ports 3.2 Interval , located in the last 32 -byte space (addresses 1FE0h through 1FFFh) in the program memory with the lower , through 0086h and 32 -byte of the program memory are also used for special purposes. Address Reset


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PDF TMP47C800 TMP47C800N TMP47C800F 47C800 TLCS-470 P-SDIP42-600-1 TMP47P800N
dmb transistor

Abstract: No abstract text available
Text: 10 11 TMP47C800 (2) P-QFP44-1414-0.80D C OC OC O O X X i ! I I I t t I I I I 33 32 31 , Reset Circuit Peripheral Hardware Function 3.1 Input/Output Ports 3.2 Interval Timer 3.3 Timer/Counters , to port P1. The table is located in the last 32 -byte space (addresses 1FE0h through 1FFFh) in the , 32 -byte of the program memory are also used for special purposes. Address OOOOh Reset start address


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PDF TMP47C800 TMP47C800N TMP47C800F TMP47C800 TLCS-470 TMP47C800F P-SDIP42-600-1 P-QFP44-1414-0 dmb transistor
LTA 201P

Abstract: spw 080
Text: T O S H IB A CO R PO R A TIO N 1/ 32 TMP47C101/201 Pin Assignment (Top View) D IP 1 6 /5 0 P , nter 2 external input External interrupt 2 input 2/ 32 T O S H IB A C O R PO RATIO N TM , Controller Interrupt Controller Reset Circuit Peripheral Flardware Function · 3.1 I/O Ports · 3.2 Interval Timer · 3.3 Timer/Counters (TC1, TC2) T O S H IB A C O R PORATION 3/ 32 TMP47C101/201 2 , acceptance Reset 0 O 0 O 0 O 0 O G 0 O 0 O 0 Interrupt vector \ 0 G Q G O 4/ 32


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PDF TLCS-47E TMP47C101P, TMP47C201P, TMP47C101M, TMP47C201M TMP47C101/201 47C101/201 S0P16 LTA 201P spw 080
Not Available

Abstract: No abstract text available
Text: and hold • 8 analog inputs • Conversion time: 32 /us (at 6 MHz , Peripheral Hardware Function 3.1 Input/Output Ports 3.2 Interval Timer 3.3 Tim er/Counters (TC1, TC2) 3.4 , 4 bits to port P2 and the lower 4 bits to port P1. The table is located in the last 32 -byte space


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PDF TMP47C660A/860A TMP47C660AN TMP47C860AN TMP47C660AF, TMP47C860AF 47C660A/860A TLCS-470 TMP47C660AN TMP47C660AF
Not Available

Abstract: No abstract text available
Text: Timer Reset 3.1 I/O Ports 3.2 Interval Timer 3.3 3.4 Timer/Counters (TC1, TC2) A/D Converter , the lower 4 bits to port R5. The table is located in the last 32 -byte space (addresses,7 E 0 h


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PDF TMP47C243/443 P47C243N P47C443N TMP47C243M, TMP47C443M TMP47C243DM, TMP47C443DM 47C243/443 TLCS-470 TMP47C243M
TMP47C243N

Abstract: TMP47C243M TMP47C243DM TMP47C443DM tmp*47c443n
Text: Function · Watchdog Timer Reset Peripheral Hardware Function Watchdog Timer Reset 3.1 I/O Ports 3.2 , the lower 4 bits to port R5. The table is located in the last 32 -byte space (addresses,7 E 0 h through


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PDF TMP47C243/443 TMP47C243N TMP47C443N TMP47C243M, TMP47C443M TMP47C243DM, TMP47C443DM TMP47C243/443 TLCS-470 TMP47C243N TMP47C243M TMP47C243DM TMP47C443DM tmp*47c443n
Not Available

Abstract: No abstract text available
Text: consultation with TOSHIBA. 1/ 32 TOSHIBA CORPORATION ^□ ^72^ 003170^ bST TMP47C101/201 , +5 V OV(GND) 2/ 32 TOSHIBA CORPORATION C 172HC 0 0 3 1 7 1 0 37Q 1QC 1 TMP47C101/201 , • • • • • • • • • • 3.1 I/O Ports • 3.2 Interval Timer • 3.3 , Register 2.4 Data Memory (RAM) - Stack - Stack Pointer Word (SPW) - Data Counter (DC) 3/ 32 , number of bytes in the instruction i 0 0 0 0 0 0 0 0 0 0 0 0 4/ 32 0 0


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PDF TLCS-47E TMP47C101/201 47C101/201 P47C101P, P47C101M P47C201M TMP47C101P TMP47C101M
47c200b

Abstract: cq 724 g diode
Text: Circuit • Peripheral Hardware Function - 3.1 3.2 3.3 3.4 I/O Ports Interval Timer Timer , lower 4 bits to port P1. The table is located in the last 32 -byte space (addresses 7Efl through 7FFh , 1Fh). Each port is selected by specifying its port address in an I/O instruction. Table 3-2 lists the , instruction Output latch pulse S4 _ n _ Port output Figure 3-2 . Output Timing TOSHIBA


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PDF TLCS-47 TMP47C200B/400B/900 47C200B/400B 47C200A/400A. TMP47C200BN, TMP47C400BN TMP47C200BF, 47c200b cq 724 g diode
G03AB

Abstract: No abstract text available
Text: FUNCTION 3.1 I/O Ports 3.2 Interval Timer 3.3 Tim er/Counters(TC1, TC2) 310594 6-01-4 ^0^724^ , Figure 3-2 . Output Timing 3.1.2 I/O Ports The 47C101/201 have 4 I/O ports (11 pins) each as , instructions ([SET @L], [CLR @L], and [TEST @L]). Table 3-2 lists the pins (I/O ports) that correspond to the , 0 1 1 0 R52 0 0 1 1 R43 0 1 1 1 R53 Table 3-2 . Relationship between L register contents and I/O port bits PortR4 (Portaddress OP04/IP04) 3_2 _ 1 â


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PDF P47C101/201 TMP47C101P, TMP47C201P TMP47C101M, TMP47C201M 47C101/201 TLCS-47E TMP47C101M G03AB
vw 60330

Abstract: 47C103 47C203 60326
Text: FUNCTION 3.1 I/O Ports 3.2 Interval Timer 3.3 Timer/Counters (TC1, TC2) 3.4 Watchdog Timer 3.5 Serial , the last 32 -byte space (addresses,7E0H through 7FFh for the 47C203, 3E0h through 3FFh for the 47C103 , I/O instruction. Table 3-2 lists the port address assignments and the I/O instructions that can , / OUTB /SET / CLR instruction F I _ z x = : : : Figure 3-2 . Output Timing 3.1.2 I/O Ports


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PDF TMP47C103/203 TMP47C103N, TMP47C203N TMP47C103M, TMP47C203M 47C103/203 TLCS-47E TMP47C103N TMP47C103M vw 60330 47C103 47C203 60326
Not Available

Abstract: No abstract text available
Text: and the lower 4 bits to port P5. The table is located in the last 32 -byte space (addresses, 7Efl , in an I/O instruction. Table 3-2 lists the port address as­ signments and the I/O instructions that , 1 2 R62 1 j R61 \> -H 3 PIN j Figure 3-2 . Ports R5, R6 (3) Port R7 , 0032b44 7bT TMP47C103/203 Table 3-2 Port Address Assignments and Available I/O Instructions M , _ n _ Output latch pulse Port output Figure 3-8. Output Timing 3.2 3.2.1 Interval


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PDF TLCS-47E P47C103/203 47C103/203 TMP47C103N, TMP47C103M, TMP47C203N, TMP47C203M TMP47C103N TMP47C103M
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