The Datasheet Archive

GMII layout Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2015 - SNLS484

Abstract: No abstract text available
Text: 时间戳帧起始检测 ä¸»è¦æŠ€æœ¯è§„æ ¼ï¼š – GMII 和 RGMII MAC 接口选项 – 双电源电压(2.5V 和 1.1Vï , 该器 件通过 IEEE 802.3 æ ‡å‡† MII、IEEE 802.3 GMII 或 RGMII 直接与 MAC 层相连ã , 消费类电子产品 系统图 MII GMII RGMII 10BASE-T 100BASE-TX 1000BASE-T MA G NE T IC S • â , . 13 GMII Transmit Timing . 14 GMII Receive Timing , Recommendations. 100 10 Layout


Original
PDF DP83867 DP83867IR 565mW 545mW 25MHz 125MHz IEEE1588 SNLS484
2001 - TG1G-S001NZ

Abstract: pulse H5007 ethernet driver TG1G LXT1000 H5007 GMII magnetics LF9202 ethernet transformer center tap FERRITE BEAD 100M ethernet transformer centre tap
Text: Transceiver Design and Layout Guide Figure 16. Recommended LXT1000 GMII Output Circuit Driver 42 , LXT1000 Gigabit Ethernet Transceiver Design and Layout Guide Application Note January 2001 , Gigabit Ethernet Transceiver Design and Layout Guide Contents 1.0 General Description , . 9 3.1 3.2 4.0 Design and Layout Checklist , .10 3.1.5 Ground and Power Plane Layout .10 3.1.6


Original
PDF LXT1000 AN104. TG1G-S001NZ pulse H5007 ethernet driver TG1G H5007 GMII magnetics LF9202 ethernet transformer center tap FERRITE BEAD 100M ethernet transformer centre tap
2005 - IC PLUS

Abstract: GMII layout IP1001LF RGMII trace mils guidelines for routing analog signals IP1001 IC Plus Corp short distance rf tx ic EMC PCB Layout RGMII
Text: IP1001 LF DESIGN & LAYOUT GUIDELINES Index 1 2 3 4 5 6 7 Purpose , .3 1/7 Copyright © 2005, IC Plus Corp. April 17 2008. Ver:1.5 IP1001 PCB LAYOUT GUIDELINES IP1001 LF DESIGN & LAYOUT GUIDELINES 1 Purpose (1) Make a stable environment for IP1001 LF working , Isolation area 50 50 MDI 0+ MDI 0MDI 1+ MDI 1RJ45 Magnetic IP1001 MDI 2+ MDI 2- GMII , layout . (2) Avoid vias and layer changes. 2/7 Copyright © 2005, IC Plus Corp. April 17 2008. Ver


Original
PDF IP1001 IC PLUS GMII layout IP1001LF RGMII trace mils guidelines for routing analog signals IC Plus Corp short distance rf tx ic EMC PCB Layout RGMII
2003 - 88E1145

Abstract: GMII layout Marvell PHY 88E1145 88E1145 schematics 24-PORT marvell 88e1145 Prestera 98EX242 marvell rgmii layout marvell API
Text: and reference designs with schematics, layout and API software. Layer 2 enterprise software for , vendors. GMII GMII GMII GMII GMII GMII GMII Alaska Quad PHY (88E1145) Alaska , (88E1145) Alaska Quad PHY (88E1145) Alaska Quad PHY (88E1145) GMII GMII Prestera-EX242 24-Port GbE Packet Processor (98EX242) Alaska Quad PHY (88E1145) GMII GMII GMII GMII , (88E1145) Alaska Quad PHY (88E1145) Alaska Quad PHY (88E1145) GMII GMII GMII GMII GMII


Original
PDF PresteraTM-EX242 24-Port 98EX242 Prestera-EX242 Prestera-EX242 48-ports 98EX242-001 88E1145 GMII layout Marvell PHY 88E1145 88E1145 schematics marvell 88e1145 Prestera 98EX242 marvell rgmii layout marvell API
2003 - ZLAN-36

Abstract: GMII layout
Text: Interface 4.2 MII Interface 4.3 GMII Interface 5.0 Interface Connections 5.1 RMII Ports 5.2 MII Ports 5.3 GMII Ports 6.0 Layout Considerations February 2005 10/100/1000 Mbit/s Ethernet network. However , GND GND Figure 4 - ZL5011x GMII Interface Connections 6.0 Layout Considerations An , Ethernet Network. Network Ethernet Switch GMII ZL5011x TDM GMII ZL5011x TDM GMII ZL5011x TDM GMII ZL5011x TDM Figure 1 - Gigabit Ethernet Connection - Central Ethernet Switch 1 Zarlink


Original
PDF ZLAN-36 ZL5011x ZL50110/11/14/15/16/17/18/19/20 GMII layout
1998 - GMII layout

Abstract: TNETX4090 schematic diagram clock schematic SPWA025 TNETX4090 macronix rambus Concurrent RDRAM
Text: describes the GMII port layout . MII Port Considerations discusses the MII port layout . Design and Layout , GMII and PMA operation present design and layout challenges because data is transferred at 125 MHz in , Design and Layout Guidelines for the TNETX4090 Device APPLICATION REPORT: SPWA025A Worldwide , . 9 General Layout Considerations , . 12 Basic Channel Layout and Board Stack Up


Original
PDF TNETX4090 SPWA025A GMII layout TNETX4090 schematic diagram clock schematic SPWA025 macronix rambus Concurrent RDRAM
2003 - ZLAN-36

Abstract: gmii layout AE82 ZL5011x ac26 ZL50408 ZL50114 MT90882 MT90883 MVTX2804
Text: 5.3 GMII Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.0 Layout Considerations . . , . . . . . . . . 4 4.3 GMII Interface . . . . . . . . . . . . . . . . . . . . . . . . 5 5.0 , off-the-shelf PHYs connecting to a Network Ethernet Switch GMII GMII GMII GMII ZL5011x , GMII or PCS mode at 1000 Mbit/s speed. Table 1 shows a summary of the various CESoP processors and their MAC interfaces. Port Interface RMII RMII MII MII GMII PCS 10 Mbit/s 100 Mbit/s 10


Original
PDF ZLAN-36 ZL5011x ZL50110/11/14/15/16/17/18/19/20 MT90880/1/2/3 ZL50408, ZLAN-36 gmii layout AE82 ZL5011x ac26 ZL50408 ZL50114 MT90882 MT90883 MVTX2804
2008 - RGMII Layout Guide

Abstract: 88E1143 rgmii specification RGMII RGMII switch TCI6486 RGMII phy RGMII trace mils s3mii SN74TVC3306
Text: . 8 10 Layout Recommendations , . 22 List of Figures 1 GMII /MII PHY Connectivity Diagram . 9 2 GMII Switch Connectivity Diagram , . TCI6486/C6472 GMII /MII Port Signals , implementation of this specification including schematics and a PCB layout can be obtained from the TCI6486


Original
PDF TMS320C6472/TMS320TCI6486 TMS320TCI6486/TMS320C6472 TCI6486/C6472 TMS320C6472/TMS320TCI6486 RGMII Layout Guide 88E1143 rgmii specification RGMII RGMII switch TCI6486 RGMII phy RGMII trace mils s3mii SN74TVC3306
2012 - Not Available

Abstract: No abstract text available
Text: KSZ9031MNX Gigabit Ethernet Transceiver with GMII /MII Support Micrel Inc., is a leading global , -5 unshielded twisted pair (UTP) cable. The KSZ9031MNX offers the industry-standard GMII /MII (Gigabit Media Independent Interface / Media Independent Interface) for connection to GMII /MII MACs in Gigabit Ethernet , simplifies board layout by using on-chip termination resistors for the four differential pairs and by , PMA RX10 GMII /MII INTERFACE PCS10 AUTONEGOTIATION computer products. the-art wafer


Original
PDF KSZ9031MNX KSZ9031MNX 10Base-T/100Base-TX/1000Base-T) 1000Mbps 10/100Mbps.
2007 - RTL8212G

Abstract: RTL8212 rtl8211 RTL8212-GR RTL821 rtl836 RTL8369 QFN-76 QFN76 RTL8212N-GR
Text: .52 9.2. MII/ GMII /RGMII SIGNAL LAYOUT GUIDELINES , Reduced GMII (RGMII), page 23). 3. Correct typo for MDC clock operation frequency (section 7.4 MDC/MDIO , GMII Mode Timing (RXC and RXD parameters). Add GTXC Cycle Time parameters. Add RXC Time High/Low and , .8 6.1. 6.2. MII/ GMII TRANSMIT INTERFACE PINS .9 6.3. MII/ GMII RECEIVE INTERFACE PINS


Original
PDF RTL8212-GR RTL8212N-GR RTL8211N-GR JATR-1076-21 RTL8212/RTL8212N/RTL8211N DHS-QFP-128 RTL8212G RTL8212 rtl8211 RTL8212-GR RTL821 rtl836 RTL8369 QFN-76 QFN76 RTL8212N-GR
2005 - RTL8212

Abstract: RTL8369 QFN-76
Text: .59 MII/ GMII /RGMII SIGNAL LAYOUT GUIDELINES , .17 GMII /MII TRANSMIT INTERFACE PINS .18 GMII /MII RECEIVE INTERFACE PINS , .29 8.2. GIGABIT MEDIA INDEPENDENT INTERFACE ( GMII /MII) .30 8.2.1. Reduced GMII (RGMII


Original
PDF RTL8212-GR RTL8212N-GR RTL8211N-GR JATR-1076-21 RTL8212/RTL8212N/RTL8211N kin8212N) QFP-128 RTL8212 RTL8369 QFN-76
2004 - RJ45 1000M PHY

Abstract: 88E1000 AMD79C901 49fct3807 88E3081 CRS15 rmii trace layout guidelines
Text: 2.2.1 GMII 2.2.2 TBI 2.3 MII Management Interface 3.0 Interface Reference Design 3.1 Fast Ethernet 3.1.1 GPS 3.1.2 MI 3.1.3 RMI 3.2 Gigabit Etherne 3.2.1 GMI 3.2.2 TBI 3.3 Layout Guidelines January 2004 , following interfaces are available: · · GMII - Gigabit MII (IEEE 802.3) TBI - Ten-Bit Interface (IEEE 802.3 , interfaces. 2.2.1 GMII This is the standard IEEE 802.3 Ethernet Interface, supporting 10/100/1000 M , never be used. 4 Zarlink Semiconductor Inc. ZLAN-86 The table below highlights the GMII signals


Original
PDF ZLAN-86 RJ45 1000M PHY 88E1000 AMD79C901 49fct3807 88E3081 CRS15 rmii trace layout guidelines
2002 - GMII layout

Abstract: gmii phy 1000BASE-X PE-TBI 8B10B TP-PMD DEVICE 1000-base-x
Text: Resets the GMII signal set to and from the GMII PHY. Layout of PE-TBI module Structure The , HOST D 1000 BASE-X SERDES or multispeed GMII PHY · Works with Alcatel PE-MCXMAC 10 , , the PE-TBI converts the 8-bit GMII transmit stream produced by the PE-MCXMAC into the 10-bit symbols , converts them into 8-bit data for the PE-MCXMAC's GMII interface. The PE-TBI also offers 1000BASE , Exchange TBI encapsulates packets conveyed via the Transmit GMII PEANX signals and passes encoded


Original
PDF 1000BASE-X 1000BASE-X PD-59050 001-FO GMII layout gmii phy PE-TBI 8B10B TP-PMD DEVICE 1000-base-x
2008 - RGMII Layout Guide

Abstract: No abstract text available
Text: Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.1 GMAC GMII /TBI Interface Usage (Host-side Only) . . . . . . . . . . . 35 6.2.1.1 GMAC GMII /TBI Pin Mappings (Host-side Only) . . . . . . . . . . . 36 6.2.1.2 GMAC GMII /TBI Connection Diagrams (Host-side only) . . . . . . 37 6.2.1.3 GMAC GMII /TBI Pin Descriptions (Host-side Only) . . . . . . . . . 39 6.2.2 Host GMAC , . . . . . . . . . . . . 74 8.4 GMII Timing (Host Interface) . . . . . . . . . . . . . . . . .


Original
PDF DS-0142-C, DS-0142-C RGMII Layout Guide
2003 - ZLAN-30

Abstract: 49fct3807
Text: GMII Ports 5.0 Layout Considerations 1 1 1 2 3 3 4 4 5 5 5 5 6 6 7 7 7 8 9 10 11 12 13 March 2005 , Overview 2.1 GPSI Interface 2.2 MII Interface 2.3 RMII Interface 2.4 GMII Interface 3.0 Interface , the switch and the PHY) Table 3 - RMII Interface Description 2.4 GMII Interface The GMII , outputs, the rest of the signals are inputs. This interface is meant to operate at 10/100/1000M. The GMII , I I I I I GMII Signal Name TXD[7:0] TXEN TXER TXCLK MTXCLK RXD[7:0] RXDV RXER RXCLK CRS 1


Original
PDF ZLAN-30 MDS10x, MVTX1100 MDS21x ZL5041x, MVTX260x MVTX280x ZL5040x 49fct3807
2001 - LP 8029 l2

Abstract: bt 2323 m decoder LXT1000 TG1G bt 2323 m H5007 DATASHEET LP 8029 l2 AF10 DFE equalizer error filter SCRAMBLE 1000base SX transmitter sc
Text: a GMII interface, 4DPAM5 encoder, scrambler, and 8B/10B encoder, Viterbi Decision Feedback , compliant. GMII and Ten-Bit Interface (TBI) MAC interface configurations. Integrated 10/100 transceiver , Transceiver Design and Layout Guide As of January 15, 2001, this document replaces the Level One document , GMII Mode (1000 BASE-T) .27 2.3.2.3 MII Mode (10 , .65 3.1.2 Ground Plane Layout


Original
PDF LXT1000 LXT1000 100-meter 8B/10B LP 8029 l2 bt 2323 m decoder TG1G bt 2323 m H5007 DATASHEET LP 8029 l2 AF10 DFE equalizer error filter SCRAMBLE 1000base SX transmitter sc
2001 - Block diagram of 8-1 multiplexer design logic

Abstract: E1110 GMII layout
Text: interfaces for MII, GMII and TBI (fiber). The E1110 is fully MAC Layer IEEE 802.3z compliant. It also , variety of PHY interfaces is supported to include MII, GMII and TBI, which offers the most flexibility , and can be used for managed switching solutions MII/ GMII /TBI To PHY modules · Indication based , the entire design solution including application and design support, physical layout , prototyping , GMII /MII/TBI Port 1 Tel: 81 3 5463 7165 Fax: 81 3 5463 7820 LSI Logic web site TX/RX FIFO


Original
PDF E1110 18-micron C20041 Block diagram of 8-1 multiplexer design logic GMII layout
2001 - LXT1000

Abstract: GMII magnetics LXT970 Q100 GMII layout
Text: . 6 GMII Interface , ) GMII Interface (" GMII Interface" on page 6) TBI Mode ("TBI Mode" on page 8) XI Input ("XI Input" on , Answers 2.0 Questions and Answers 2.1 PBGA Design Considerations Q1. 2.2 GMII Interface , Gigabit Ethernet Transceiver Design and Layout Guide for more information.) RX_CLK and TX_CLK run at , ) must be synchronized to GTX_CLK and meet the GMII set-up and hold requirements. Q12. What are


Original
PDF LXT1000 LXT1000 GMII magnetics LXT970 Q100 GMII layout
2007 - BCM56800

Abstract: ethernet BCM higig specification Gigabit bcm pause frame cx4 to sma higig pause frame 1000BASE-X LFSC3GA25E 1gbps serdes
Text: test was limited to the physical layer (up to GMII ) of the Gigabit Ethernet protocol stack , Physical Layer Reconciliation GMII PCS PMA PHY PMD MDI Medium 1000 Mbps According to the , -4 to SMA conversion board. · Gigabit Media Independent Interface ( GMII ). The GMII is designed to , intermixing PHYs and DTEs at gigabit speeds. The GMII is intended for use as a chip-to-chip interface. No mechanical connector is specified for use with the GMII . The GMII is optional. The 1000BASE-X Gigabit


Original
PDF TN1157 1000BASE-X BCM56800 1-800-LATTICE ethernet BCM higig specification Gigabit bcm pause frame cx4 to sma higig pause frame LFSC3GA25E 1gbps serdes
2006 - 2x19

Abstract: msap STM-16 TXC-06743 serdes 8b 10b 844P
Text: the most optimal configuration appropriate for board design. Designers can re-use PCB layout , options. Application Diagram GMII OC-48/STM-16 or 4x OC-12/STM-4 Ethernet PHY TBI PHY , Software Up to: 2x GMII , 2x SerDes for GigE [1.25Gbps], 12x SMII FE Host API SW Driver & on-chip , High-order +TU-3 SDRAM GMII / SerDes 4x 19/77 MHZ Telecom Bus or MPI 2x GMII and/or 12x SMII , TelecomBus for protection, Backplane, TDM tributaries TBI for Escon, DVB-ASI, FC or GigE GMII


Original
PDF OC-48/STM-16 2x19/77 OC-48/4x OC-12 4x19/77 2x19 msap STM-16 TXC-06743 serdes 8b 10b 844P
2008 - 88E1111

Abstract: Marvell PHY 88E1111 Datasheet Marvell PHY 88E1118 Marvell 88E1112 Marvell 88E1111 88E1118 Marvell PHY 88E1118 Datasheet Marvell PHY 88E1111 layout 88E1112 88e111
Text: Reconciliation GMII PCS PMA PHY PMD MDI Medium 1000 Mbps According to the 802.3-2002 standard, two , Gigabit Media Independent Interface ( GMII ). The GMII is designed to connect a gigabit-capable MAC or , intermixing PHYs and DTEs at gigabit speeds. The GMII is intended for use as a chip-to-chip interface. No mechanical connector is specified for use with the GMII . The GMII is optional. The objective of this , ) block supports full compatibility, from the Serial I/O to the GMII interface of the IEEE 802.3-2002


Original
PDF TN1120 88E1111/88E1112 1-800-LATTICE 88E1112 88E1111 Marvell PHY 88E1111 Datasheet Marvell PHY 88E1118 Marvell 88E1112 Marvell 88E1111 88E1118 Marvell PHY 88E1118 Datasheet Marvell PHY 88E1111 layout 88e111
2009 - KSZ9021GN

Abstract: KSZ9021 9021GN GMII layout KSZ90 DSA0011674 KSZ9021GN KSZ9021GN
Text: KSZ9021GN Product Brief Single-port Gigabit Transceiver with GMII /MII Support Description The , such as GEPON ONU router. The KSZ9021GN provides the industry standard GMII /MII (Gigabit Media Independent Interface / Media Independent Interface) for direct connection to GMII /MII MACs in Gigabit , . 10/100 /1000 Mbps MII / GMII Ethernet MAC KSZ 9021GN MDC / MDIO Management Ma g ne ti cs MII / GMII On-c hip T erm inati on Res is tors Functional Diagram RJ-45 Connector


Original
PDF KSZ9021GN KSZ9021GN 10/100/1000Base-T M9999-121108 KSZ9021 9021GN GMII layout KSZ90 DSA0011674 KSZ9021GN KSZ9021GN
Not Available

Abstract: No abstract text available
Text: KSZ9021GN Product Brief Single-port Gigabit Transceiver with GMII /MII Support Description The , such as GEPON ONU router. The KSZ9021GN provides the industry standard GMII /MII (Gigabit Media Independent Interface / Media Independent Interface) for direct connection to GMII /MII MACs in Gigabit , . 10/100 /1000 Mbps MII / GMII Ethernet MAC KSZ 9021GN MDC / MDIO Management Ma g ne ti cs MII / GMII On-c hip T erm inati on Res is tors Functional Diagram RJ-45 Connector


Original
PDF KSZ9021GN KSZ9021GN 10/100/1000Base-T M9999-121108
2004 - traffic light controller vhdl coding

Abstract: ENG-46158 1000BASE-X sfp sgmii 1000base-x xilinx sgmii specification ieee vhdl code for mac transmitter verilog code for 10 gb ethernet vhdl code for ethernet mac spartan 3 gtx 970 DS264
Text: 802.3-2008 standard Gigabit Media Independent Interface ( GMII ) to Serial-GMII (SGMII) bridge or SMGII to GMII , -4, Spartan-6, Spartan-3, Spartan-3E, Spartan-3A/3A DSP GMII Resources2 Slices 140­1100 GTs 0-1 LUTs 170­1090 , ) Netlist 1000BASE-X PCS/PMA using a transceiver 1000BASE-X PCS with Ten-Bit Interface3 GMII to SGMII Bridge , external Physical-Side Interface (PHY) device Internal or external GMII to MAC or custom logic. See Voltage , Form-Factor Pluggable (SFP) optical transceiver to complete the Ethernet port. The GMII of the Ethernet


Original
PDF 1000BASE-X DS264 ENG-46158) traffic light controller vhdl coding ENG-46158 1000BASE-X sfp sgmii 1000base-x xilinx sgmii specification ieee vhdl code for mac transmitter verilog code for 10 gb ethernet vhdl code for ethernet mac spartan 3 gtx 970
2004 - sgmii specification ieee

Abstract: ENG-46158 virtex-7 1000BASE-X sfp sgmii traffic light controller vhdl coding ISERDES vhdl code for ethernet mac spartan 3 SPARTAN 6 ethernet vhdl ethernet spartan 3a vhdl ethernet spartan 3e
Text: IEEE 802.3-2008 standard Gigabit Media Independent Interface ( GMII ) to Serial-GMII (SGMII) bridge or SMGII to GMII bridge, as defined in the Serial-GMII specification (ENG-46158) LogiCORE IP Facts Table , -5, Virtex-4, Spartan-6, Spartan-3, Spartan-3E, Spartan-3A/3A DSP GMII · Features · Supported physical , ) Netlist 1000BASE-X PCS/PMA using a transceiver 1000BASE-X PCS with Ten-Bit Interface3 GMII to SGMII Bridge , with the external Physical-Side Interface (PHY) device Internal or external GMII to MAC or custom logic


Original
PDF 1000BASE-X DS264 ENG-46158) sgmii specification ieee ENG-46158 virtex-7 1000BASE-X sfp sgmii traffic light controller vhdl coding ISERDES vhdl code for ethernet mac spartan 3 SPARTAN 6 ethernet vhdl ethernet spartan 3a vhdl ethernet spartan 3e
Supplyframe Tracking Pixel