The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
74LVC273APG 74LVC273APG ECAD Model Renesas Electronics Corporation DUAL NEG. FLIP FLOP
74LVC273ASO 74LVC273ASO ECAD Model Renesas Electronics Corporation DUAL NEG. FLIP FLOP
74LVC273APGG 74LVC273APGG ECAD Model Renesas Electronics Corporation DUAL NEG. FLIP FLOP
74LVC646APG 74LVC646APG ECAD Model Renesas Electronics Corporation DUAL NEG. FLIP FLOP
74LVCH244APG8 74LVCH244APG8 ECAD Model Renesas Electronics Corporation DUAL NEG. FLIP FLOP
74LVC273APYG8 74LVC273APYG8 ECAD Model Renesas Electronics Corporation DUAL NEG. FLIP FLOP

Flip Flops Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
16-LINE TO 4-LINE PRIORITY ENCODERS

Abstract: 74 series logic gates Flip flops "J-K Flip flops" J-K Flip flops NAND Gates HD74 Synchronous 8-Bit Binary Counters HD74S synchronous binary counter with latch
Text: HD74 Series HD74S Series Dual 4-input Expanders 60 — • FLIP FLOPS Function HD74 Series HD74S Series J-K Master-Flip Flop (AND Inputs) 72 — Dual J-K Flip Flops 73 " — Dual D-type Edge-triggered Flip Flops 74 ^ 74 ' Dual J-K Flip Flops (with PR and CLR) 76 — Dual J-K Flip Flops 107 " — Dual J-K Negative-edge-triggered Flip Flops (with PR and CLR) — 112 - Dual J-K Negative-edge-triggered Flip Flops (with PR) — 113 Dual J-K Negative-edge-triggered Flip Flops (with PR, Common CLR


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PDF HD74/HD74S HD74S HD74Series 16-bit DP-14 DP-16 DP-20 16-LINE TO 4-LINE PRIORITY ENCODERS 74 series logic gates Flip flops "J-K Flip flops" J-K Flip flops NAND Gates HD74 Synchronous 8-Bit Binary Counters synchronous binary counter with latch
4-bit bidirectional shift register 74 194

Abstract: 16-LINE TO 4-LINE PRIORITY ENCODERS 74 series logic gates 4-bit even parity checker J-K Flip flops 4-bit shift register 74 194 Flip Flops HD74 H183 74 series 7 segment decoders
Text: Function H 1)7', Series HD74S Series Dual 4-input Expanders 60 — • FLIP FLOPS Function HD74 Series HD74S Series J-K Master-Flip Flop (AND Inputs) 72 — Dual J-K Flip Flops 73 - — Dual D-type Edge-triggered Flip Flops 74 74 Dual J-K Flip Flops (with PR and CLR) 76 — Dual J-K Flip Flops 107 " — Dual J-K Negative-edge-triggered Flip Flops (wi th PR and CLR) — 112 - Dual J-K Negative-edge-triggered Flip Flops ( wi th PR) — 113 Dual J-K Negative-edge-triggered Flip


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PDF HD74/HD74S HD74S HD74Series 16-bit DP-16 DP-20 DP-24 4-bit bidirectional shift register 74 194 16-LINE TO 4-LINE PRIORITY ENCODERS 74 series logic gates 4-bit even parity checker J-K Flip flops 4-bit shift register 74 194 Flip Flops HD74 H183 74 series 7 segment decoders
Flip Flops

Abstract: 74 series logic gates DP-14 H183 HD74 2 input nand gate 24v 74 series 7 segment decoders quad jk flip flop
Text: Dual 4-input Expanders _ • FLIP FLOPS Function HD74 Series IID74S Series J-K Master-Flip Flop , Dual J-K Flip Flops (with FR and CI.RJ 76 Dual J-K Flip Flop* 107 /S Dual J-K Negiitivc-cd*e-triggered Flip Flops (with PR and CI.R) _ 112 - Dual J-K Ncgative-rdge-trigger«! Flip Flops (wich PR) — 113 DmI J-K Nefahte-edgr-tr^ered Flip Flops (with PR. Common CLR. and CnDM CK) 1U - Monostable MuJtivibrator 121-^ Dual Retrifctferable Monnstable Muhivibrators 123 w — Hex D-type Flip Flops {with CI.R


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PDF HD74/HD74S HD74S HD74Series 16-bit DP-14 DP-16 DP-20 Flip Flops 74 series logic gates DP-14 H183 HD74 2 input nand gate 24v 74 series 7 segment decoders quad jk flip flop
1998 - octal Bilateral Switches

Abstract: MM74HC14M MM74HC138M CD4025BCM MM74HC00M MM74HC74AM MM74HC125M MM74HC04M cd4046bcm cd4052bcm
Text: MM74HCT08M Quad 2-Input AND Gate MM74HCT32M Quad 2-Input OR Gate MM74HCU04M Hex Inverter Flip Flops & , 0.38 0.48 0.45 1.63 1.63 1.63 0.30 0.34 0.34 0.35 0.30 0.30 Flip Flops & Registers 74ACT74SC Dual D , -Input OR Gate 74AC86SC Quad 2-input Exclusive-OR Gate Flip Flops & Registers 74AC74SC Dual D Flip-Flop , Trigger Input Flip Flops & Registers 74ACTQ273SC Octal D Flip-Flop with Clear 74ACTQ16374SSC 16-Bit D , -Input OR Gate 74VHC86M Quad 2-Input Exclusive OR Gate Flip Flops & Registers 74VHC74M Dual D Flip-Flop with


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PDF MM74HC MM74HC00M MM74HC02M MM74HC04M MM74HC08M MM74HC14M MM74HC32M MM74HC86M MM74HC132M MM74HC74AM octal Bilateral Switches MM74HC138M CD4025BCM MM74HC125M cd4046bcm cd4052bcm
Flip Flops

Abstract: JD 1801 1N3064 1N916 AM29825 SN54ALS29825 SN74ALS29825 SN74ALS29826 D2829 d708d
Text:  SN54ALS29825, SN74ALS29825, SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS , 655012 • DALLAS. TEXAS 75265 SN54ALS29825, SN74ALS29825, SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS , €¢ DALLAS, TEXAS 75265 SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS FUNCTION TABLE , Instruments POST OFFICE BOX 656012 • DALLAS. TEXAS 75265 SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH , SN54ALS29825 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS switching characteristics PARAMETER FROM


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PDF SN54ALS29825, SN74ALS29825, SN74ALS29826 D2829, AM29825 AM29826 300-mil SDAS147B Flip Flops JD 1801 1N3064 1N916 SN54ALS29825 SN74ALS29825 SN74ALS29826 D2829 d708d
Flip Flops

Abstract: No abstract text available
Text: Flops with 3-State Outputs. 10-bit D-type Flip Flops with Dual Outputs. 10-bit Bus Interface Flip Flops with 3 , Bus Transceivers with 3-State Outputs. 20-bit D-type Flip Flops with 3-State Outputs. 10-bit D-type Flip Flops with Dual Outputs. 10-bit Bus Interlace Flip Flops with 3-State Outputs. 18


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PDF HD74LVC/LV Flip Flops
1999 - XC9500XL

Abstract: CS48 PC44 PQ208 TQ100 TQ144 XAPP114
Text: flip flops , it is important to realize that the flip flops consume negligible power compared to the , driving pins and flip flops . The switching speed of the product terms and output pins become the , accurate static power estimation can be measured. For sequential circuits, the binary values of flip flops , estimate of the distribution of internal components (p-terms, flip flops , pins, etc.). Frequently, it is , . If buried flip flops (i.e. the circuit state) have various flip flops high with others low, this


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PDF XC9500XL XAPP114 XC9500XL CS48 PC44 PQ208 TQ100 TQ144
1998 - 44k1

Abstract: J-K Flip flops D Flip Flops MSM13Q MSM98Q MSM98S 64512 642k
Text: 29 72 21 D Flip Flops 28 28 28 28 28 72 32 8 10 10 10 10 76 12 JK Flip Flops 17 17 17 17 17 8 8 Toggle Flip Flops 18 18 , S-R Latches Scannable Flip Flops I/O1 Input Buffers Input Buffers with Pull Up/Pull Down I/O


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PDF J2N0015-38-82 MSM10S MSM38S MSM12R MSM13R MSM32R MSM13Q MSM98Q MSM98S MSM98R 44k1 J-K Flip flops D Flip Flops MSM98Q MSM98S 64512 642k
Not Available

Abstract: No abstract text available
Text: HD74ALVCH16821 3.3-V 20-blt Bus Interface Flip Flops with 3-state Outputs Preliminary Description The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops . On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (ÔË) input can be used to place the , components. The output enable (OE) input does not affect the internal operations of the flip flops . Old data


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PDF HD74ALVCH16821 20-blt HD74ALVCH16821 10-bit 20-bit HD74AI.
2000 - D Flip Flops

Abstract: MG113P MG73Q MSM13Q MSM98Q 32-768K "Single-Port RAM"
Text: 32 32 32 D Flip Flops 8 10 10 10 10 76 12 12 12 Scannable Flip Flops 17 17 17 17 17 8 8 8 8 JK Flip Flops 18 18 18 18 18 0 4 4 4 Toggle Flip Flops 8 8 7 7 7 0 2 2


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PDF FJXLSC-MACROLIB-04 MSM10S MSM38S MSM12R MSM13R MSM32R MSM13Q MSM98Q MG73Q D Flip Flops MG113P 32-768K "Single-Port RAM"
Not Available

Abstract: No abstract text available
Text: HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs Preliminary Description The H D 74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops . On the positive transition o f the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input can be used to place the , components. The output enable (OE) input does not affect the internal operations o f the flip flops . Old data


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PDF HD74ALVCH162821 20-bit 74ALVCH162821 10-bit LYCHI62821
Not Available

Abstract: No abstract text available
Text: HD74ALVCH16821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs HITACHI ADE-205-171 (Z) Preliminary, 1st. Edition January 1997 Description The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops . On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered , affect the internal operations of the flip flops . Old data can be retained or new data can be entered


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PDF HD74ALVCH16821 20-bit ADE-205-171 HD74ALVCH16821 10-bit CH16821 TTP-56D
5 inputs OR gate truth table

Abstract: HiNil IN4148 4 inputs gates truth table single mode j-k flip flops
Text: 580 Pleasant Street Watertown, MA 02172 (617) 924-9280 TSC311/312/313 Flip Flops • Master , €¢ Indeterminate state 3-9 Equivalent Circuits TYPICAL OUTPUT vcc O- S pec ifi cations 311 Flip Flops 311 , Clock inputs 1 UL S".R Direct S-R inputs 2 UL Q,Q Outputs 5 UL 3-10. Flip Flops 311,312, 313 PINS , 3 1 1 0 4 0 0 1 5 1 0 1 6 0 0 0 3-13. Flip Flops 311,312, 313 t Qa Qb Qc 0 0 0 0 1 1 0 0 2 , slave and enables data transfer J-K MODE 5 j 1 K J M s 1 t2 fi 3-11 Flip


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PDF TSC311/312/313 5 inputs OR gate truth table HiNil IN4148 4 inputs gates truth table single mode j-k flip flops
dx 400

Abstract: HD-6101 HD-6101C-9 HD-6103 HM-6100 dx400
Text: requests are generated only when the sense flip flops are set by an edge and interrupts are enabled by writing to control reg A. Sense flip flops are reset on the following conditions. SENSE FLIP FLOPS , system performance. The PIE samples the sense flip flops and generates an interrupt request for enabled , the HM-6100 when sense flip flops are set during SKIP instructions. This output is open drain. 40 , information — not guaranteed. 5-32 Programmable Sense Inputs The sense inputs are used to set sense flip


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PDF HD-6101C-9 1500C HD-6101C-9 HD-6103 dx 400 HD-6101 HM-6100 dx400
Not Available

Abstract: No abstract text available
Text: HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs HITACHI ADE-205-186A (Z) 2nd. Edition September 1997 Description The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops . On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output , internal operations of the flip flops . Old data can be retained or new data can be entered while the


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PDF HD74ALVCH162821 20-bit ADE-205-186A HD74ALVCH162821 10-bit HD74AL CH162821 TTP-56D
LS112A

Abstract: SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A SN74S112A
Text: SN54LS112A, SN54S112, SN74LS112A, SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH , SN54LS112A, SN54S112, SN74LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR , SN54LS112A, SN54S112, SN74LS112A, SN74S112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR , • DALLAS. TEXAS 75265 SN54S112, SN74S112A DUAL J K NEGATIVE EDGE TRIGGERED FLIP FLOPS WITH , FLIP FLOPS WITH PRESET AND CLEAR switching characteristics, Vcc ~ 5 V, Ta " 25 °C (see Note 4


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PDF SN54LS112A, SN54S112, SN74LS112A, SN74S112A LS112A SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A
1998 - ts5667

Abstract: D Flip Flops TS7798 PM7346 PM7366 TS977 "D Flip Flops" rfpo TS56
Text: is used to keep track of bit position within the J2 frames. D flip flops are used to control the output of each gating signal. Setting and resetting of these flip flops is done at count values that , clocks passed to the FREEDM-8. Reset of the counter and D flip flops occur every J2 frame boundary. The , flip flops , respectively. Feedback is used by each D flip flop to sustain gating signals until the , flops and then multiplexed to a single output flip flop by logic using the clock gating signals to


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PDF PM7366 PMC-971136 PM7366 PM-971136 ts5667 D Flip Flops TS7798 PM7346 TS977 "D Flip Flops" rfpo TS56
2009 - RAMB16BWERs

Abstract: AN1971 SPARTAN-3A 1800 SMPTE-424 digital clock using gates C259C digital clock using logic gates SPARTAN-3A DSP 1800A Xilinx Spartan 6 Eval Kit sdi converter
Text: Used Available Utilization Slice Flip Flops 3,947 33,280 11% 4 Input LUTs 6,613 , Used Available Utilization Slice Flip Flops 3,517 33,280 11% 4 Input LUTs 5,676 , Utilization Used Available Utilization Slice Flip Flops 913 33,280 3% 4 Input LUTs , Slice Flip Flops 940 33,280 3% 4 Input LUTs 1,348 33,280 4% Used Available , 6. SDI FPGA IP Audio Only Logic Utilization Used Available Utilization Slice Flip Flops


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PDF LMH0340 AN-1971 RAMB16BWERs AN1971 SPARTAN-3A 1800 SMPTE-424 digital clock using gates C259C digital clock using logic gates SPARTAN-3A DSP 1800A Xilinx Spartan 6 Eval Kit sdi converter
SN54HC564

Abstract: SN74HC564
Text: SN54HC564, SIH74HC564 OCTAL D-TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS D2684 , OCTAL D-TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS logic diagram (positive logic) X o o cn , SN54HC564, SIH74HC564 OCTAL D-TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS absolute maximum ratings , OCTAL D-TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS timing requirements over recommended , EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS switching characteristics over recommended operating


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PDF SN54HC564, SIH74HC564 D2684, 1982-REVISED 300-mil SN54HC564 SN74HC564
dx 400

Abstract: sf hd 850 HD-6101 HD-6101-2 HD-6101-9 HD-6101C-9 HM-6100 skip-2
Text: test the state of the sense flip flops . If the input conditions have set the sense flip flop, the PIE , requests by clearing the sense flip flops . C/3 < OOUJ Q- :r OC LU a. Programmable Outputs FLAGs (1-4 , Sense Inputs The sense inputs are used to set sense flip flops (SENSEFF) inside the PIE. For each sense , FF's are sampled when LXWIAR is high. Interrupt requests are generated only when the sense flip flops are set by an edge and interrupts are enabled by writing to control reg A. Sense flip flops are reset


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PDF HD-6101 HM-6100 HD-6101 dx 400 sf hd 850 HD-6101-2 HD-6101-9 HD-6101C-9 skip-2
2007 - RAMB36

Abstract: H.264 integer transform fpga 7831 8627 H.264 microsoft 1080p field pattern virtex 4 vs spartan 3e VHDL code motion 1080i Vs 1080p DS602
Text: Facts Core Specifics 720i/p Virtex-5 5083 Slice Flip Flops 10258 Slice LUTS 8 RAMB18x2, 20 RAMB36 ITU-R-BT.601 5072 Slice Flip Flops 10270 Slice LUTS 8 RAMB18x2, 16 RAMB36 CIF 5022 Slice Flip Flops 10240 Slice LUTS 8 RAMB18x2, 14 RAMB36 Xilinx ISETM 8.2.03i (from ngd_build , -5, Virtex-4, SpartanTM-3 5083 Slice Flip Flops 10258 Slice LUTS 8 RAMB18x2, 20 RAMB36 Synplicity


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PDF DS602 264/MPEG-4 1080i 1080p/60 1080i/p 720i/p 1080P/30, 1080i/60, 720P/60 1080P/60, RAMB36 H.264 integer transform fpga 7831 8627 H.264 microsoft 1080p field pattern virtex 4 vs spartan 3e VHDL code motion 1080i Vs 1080p DS602
NT 101

Abstract: 1N3064 1N916 AM29825 SN74ALS29825 SN74ALS29826
Text: 5 to r > SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS d2829 , SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS description (continued) PUU , By Its Respective Manufacturer SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3 , SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS switching characteristics , Respective Manufacturer SN74ALS29825. SN74ALS29826 8 BIT BUS INTERFACE FLIP FLOPS WITH 3-STATE OUTPUTS


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PDF SN74ALS29825. SN74ALS29826 d2829, 1986-revised AM29825 AM29826 300-mil NT 101 1N3064 1N916 SN74ALS29825 SN74ALS29826
T flip flop IC

Abstract: T flip flop IC no T flip flop IC CMOS D flip flop IC harris 6121 6121 harris 6121
Text: within the 6121 IOC. Each controller has a set of control and status flip flops which are defined below , to be programmed as discussed above. Also, all five flag flip flops are cleared as are the flag sample and interrupt sample flip flops . The interrupt enable flip flops are all set. The strobe flip , flag, flag sample, interrupt sample, interrupt inhibit and strobe flip flops are not disturbed by the , and strobe flip flops . It does not set up the IOC for programming, nor does it disturb the state of


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PDF HD-6121 T flip flop IC T flip flop IC no T flip flop IC CMOS D flip flop IC harris 6121 6121 harris 6121
ALS564A

Abstract: SN54ALS564A
Text: SN54ALS564A, SN74ALS564A OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS D2661, APRIL 1982 - REVISED MAY 1986 3-State Buffer-Type Inverting Outputs Drive Bus-Lines Directly , , SN74ALS564A OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS logic diagram (positive logic) V , Respective Manufacturer SN54ALS564A, SN74ALS564A OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE , SN54ALS564A, SN74ALS564A OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS switching


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PDF SN54ALS564A, SN74ALS564A D2661, 300-mil ALS564A SN54ALS564A SN74ALS564A
FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Text: -bit parallel output serial shift register 8-bit serial/parallel input shift register Hex D-type flip flops Quad D-type flip flops Synchronous up/down counter binary 74191 Synchronous up/down counter BCD , -input exclusive-NOR gates with open collector outputs Octal D-type flip flops Quad SR latches 9-bit odd/even , 4-bit data. Octal D-type latches Octal D-type flip flops 4-bit bistable latches Hex D-type flip , flip flops 8-bit shift register Dual 4-bit shift register Quad bilateral switches Decade counter


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PDF 74INTEGRATED Line-to-10 150ns 16-DIL 150ns 18-pin 250ns 300ns FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
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