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SN74ACT1073DWR SN74ACT1073DWR ECAD Model Texas Instruments 16-Bit Bus Termination Networks With Bus Hold Function 20-SOIC -40 to 85
SN74ACT1071D SN74ACT1071D ECAD Model Texas Instruments 10-Bit Bus Termination Networks With Bus Hold Function 14-SOIC -40 to 85
SN74ACT1071DR SN74ACT1071DR ECAD Model Texas Instruments 10-Bit Bus Termination Networks With Bus Hold Function 14-SOIC -40 to 85
SN74ACT1073NSR SN74ACT1073NSR ECAD Model Texas Instruments 16-Bit Bus Termination Networks With Bus Hold Function 20-SO -40 to 85
SN74ACT1073DW SN74ACT1073DW ECAD Model Texas Instruments 16-Bit Bus Termination Networks With Bus Hold Function 20-SOIC -40 to 85
SNJ54S181FK SNJ54S181FK ECAD Model Texas Instruments Arithmetic Logic Units/Function Generators 28-LCCC -55 to 125

FUNCTIONAL DIAGRAM OF 7400 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2000 - 7400 series pinout diagram

Abstract: pin diagram 7400 series 7400 chip
Text: the default power state of the 7400 . The 7400 is fully powered and the internal functional units are , execution, or external hardware. D Doze : All the functional units of the 7400 are disabled except for the , 7400 ) is the first implementation of the fourth (G4) full implementation of the PowerPC Reduced , 7400 microprocessor design is superscalar, capable of issuing three instructions per clock cycle into , . . . . . . . . . . . . . . . . . . . . . . 3 1. 7400 MICROPROCESSOR BLOCK DIAGRAM . . . . . . . .


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PDF 18SPECint95, 16SPECfp95 266Mhz 200Mhz 400Mhz, 64-bit 32-bit 400Mhz 100Mhz PowerPC7400 7400 series pinout diagram pin diagram 7400 series 7400 chip
1992 - application circuits of ic 74123

Abstract: IC AND GATE 7408 7408 AND GATE pin DIAGRAM OF IC 7408 2n3904 c33 IC 7400 nand function 7400 PIN DIAGRAM internal diagram of 7400 IC pin DIAGRAM OF IC 74123 IC 7408 application circuit
Text: ) GAIN (%) IN B 0.5V REF 50 0 Fig. 1 Functional Block Diagram of the GT4123 and , , VCA reduces and VCB increases in proportion so that less of the Channel A signal and more of the , . The internal topology of the devices is shown in Figure 1. The SPAN or control range is internally set so that a CONTROL voltage of 0 volts completely cuts off Channel A and fully turns on Channel B. Similarly, a CONTROL voltage of 1 volt will fully turn on Channel A and completely turn Channel B off. IN


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PDF GT4123 GT4123A GT4123 GT4123A EL-2020 GB4551 GX4314, application circuits of ic 74123 IC AND GATE 7408 7408 AND GATE pin DIAGRAM OF IC 7408 2n3904 c33 IC 7400 nand function 7400 PIN DIAGRAM internal diagram of 7400 IC pin DIAGRAM OF IC 74123 IC 7408 application circuit
1996 - FUNCTIONAL DIAGRAM OF 7400

Abstract: pin diagram 7400 series 7400 PIN DIAGRAM schematic diagram TMS34010 7400 series logic ICs 7400 TTL 7400 chip 7400 fan-out 7400 functional diagram TTL 7400
Text: . 5-84 QAN8 Overall Design Description Figure 1 is a functional block diagram of the board. RGB , . Figure 2 is a functional block diagram of the VME Interface logic implemented in the pASIC. The major , control signals and not an attempt to control the device timing. Figure 3 is a functional block diagram of the video logic implemented in the pASIC. The major components in the diagram are the local bus , logic required by the LSI video components. A design that was previously implemented using a variety of


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PDF TMS34020 7400-series QL12x162PL84C) FUNCTIONAL DIAGRAM OF 7400 pin diagram 7400 series 7400 PIN DIAGRAM schematic diagram TMS34010 7400 series logic ICs 7400 TTL 7400 chip 7400 fan-out 7400 functional diagram TTL 7400
7408 AND GATE

Abstract: pin DIAGRAM OF IC 7400 IC 7400 nand function IR33C IC 7400 pin diagram internal circuit diagram of 7400 IC function DIAGRAM OF IC 7400 IC 7408 application circuit internal diagram of 7400 IC IC AND GATE 7408
Text: volts, the opposite occurs. 3-65 Fig. 1 Functional Block Diagram of the GT4123 and GT4123A , professional video and multimedia markets. The internal topology of the devices is shown in Figure 1. The SPAN or control range is internally set so that a CONTROL voltage of 0 volts completely cuts off Channel A and fully turns on Channel B. Similarly, a CONTROL voltage of 1 volt will fully turn on Channel A and completely turn Channel B off. Figure 2 shows the CONTROL transfer characteristics of the GT4123 and GT4123A


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PDF T4123 GT4123A GT4123 EL-2020 GB4551 GX4314 7408 AND GATE pin DIAGRAM OF IC 7400 IC 7400 nand function IR33C IC 7400 pin diagram internal circuit diagram of 7400 IC function DIAGRAM OF IC 7400 IC 7408 application circuit internal diagram of 7400 IC IC AND GATE 7408
2008 - 7400 pin configuration drawing

Abstract: intel xeon 7400 series 7400 series list 7400 flotherm TDP 243 Y G751 T0146 CEK604 mPGA604
Text: ® Processor 7400 Series TMDG B-8 Load Plate Drawing (Sheet 1 of 1 , required for the Intel® Xeon® processor 7400 series. It is also the intent of this document to comprehend , the processor cooling solution. In case of conflict, the data in the Intel® Xeon® Processor 7400 , within the processor. Note: Not all Intel Xeon processor 7400 series are capable of supporting , Diagram The high end point of the Thermal Profile represents the processor's TDP and the associated


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PDF A95692-002 CEK604-2U-04 D67766002 FHP8871 7400 pin configuration drawing intel xeon 7400 series 7400 series list 7400 flotherm TDP 243 Y G751 T0146 CEK604 mPGA604
IC TTL 7400 diagram and truth table

Abstract: No abstract text available
Text: hundreds of different 7400 se­ ries part numbers currently used in most digital systems. compatible , Functional Description The Logic Array Block The Logic Array Block, shown in Figure 2, is the heart of the , feedback of all signals is provided within an LAB, giving each functional block complete access to the , Macrocell Array is the I/O Control Block of the LAB. Figure 5 shows the I/O block diagram . The tristate , , unlimited hierarchy levels, symbol editing, and a library of 7400 series devices in addi­ tion to basic


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PDF CY7C340 IC TTL 7400 diagram and truth table
2005 - IC 7400 SERIES list

Abstract: IC 7400 diagram and truth table pin configuration ic 7410 IC 7410 truth table pin diagram of ic 7410 pin configuration of ic 7410 tPHL 7400 ACML-7410 pin diagram ic 7420 IC 7410
Text: information. 2 Functional Diagram Quad Channel ACML- 7400 VDD1 GND1 VIN1 VIN2 VIN3 VIN4 NC GND1 1 , distortion of 3 ns. They are capable of running at a 100 MBaud data rate ACML- 7400 , ACML-7410 and ACML , DC and timing specifications are specified over the temperature range of -40° C to +105° C. ACML- 7400 , specifications apply to ACML- 7400 , ACML-7410 and ACML-7420 and are applicable to ambient temperature of -40° C , consumption at VDD1 of ACML- 7400 , ACML-7410 and ACML-7420 when there is no signal to all inputs. 2. IDD1(F) is


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PDF ACML-7400, ACML-7410 ACML-7420 ACML-7420 ACML-7400 AV02-2675EN IC 7400 SERIES list IC 7400 diagram and truth table pin configuration ic 7410 IC 7410 truth table pin diagram of ic 7410 pin configuration of ic 7410 tPHL 7400 pin diagram ic 7420 IC 7410
74LS324

Abstract: 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74C923 equivalent Flip-Flop 7473 74LS324 equivalent 74C08 equivalent
Text: (Complementary Metal Oxide Silicon) series are a pin-for-pln functional equivalent to the 7400 TTL family. They , Schottky, a type of TTL with a current and power reduction by a factor of 5 (compared to 7400 TTL), and an , (compared to 7400 TTL), and an anti- saturation schottky diode. S = The 74S series is a line of super high , (Complementary Metal Oxide Silicon) series are a pin-for-pln functional equivalent to the 7400 TTL family. They , of TTL with a current and power reduction by a factor of 5 (compared to 7400 TTL), and an anti


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PDF G0G513S 74C00 74H00 74LS00 74S00 74H01 74LS01 74C02 74LS02 74S02 74LS324 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74C923 equivalent Flip-Flop 7473 74LS324 equivalent 74C08 equivalent
2002 - 53A18

Abstract: 30460
Text: consists of various functional and parametric tests of each die. Test patterns, timing, voltage margins , x8 configurable with BHE-pin GENERAL PHYSICAL SPECIFICATIONS ·Backside die surface of polished , 13 14 15 16 1 7 18 19 20 21 22 23 2 4 25 26 27 FUNCTIONAL SPECIFICATIONS A bare die is tested for only DC parameters and functional items. Please refer to the packaged product data sheet for functional and parametric specifications. For bare die, these specifications are provided for reference only


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PDF 1000E-C/W 512Kx16) 100ns 120ns 320um 3640um 3640um 140um 53A18 30460
2008 - instruction set architecture intel xeon 7400

Abstract: intel xeon 7400 series intel xeon 7400 ITT 7400 peci specification ITT G 91 15 TCA 700 y E7400 7400 series ITT TCA 700 Y pin diagram 7400 series
Text: . 51 Intel® Xeon® Processor 7400 Series Package Drawing (Sheet 1 of 2). 52 Intel® Xeon® Processor 7400 Series Package Drawing (Sheet 2 of 2). 53 Top Side , Architecture. The Intel® Xeon® Processor 7400 Series will be available with 12 MB or 16 MB of on-die level 3 , bandwidth. All versions of the Intel® Xeon® Processor 7400 Series will include manageability features , ® Xeon® Processor 7400 Series is available in a Flip-Chip Micro Pin Grid Array 8 package, consisting of


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IC 7400 diagram and truth table

Abstract: IC TTL 7400 diagram and truth table IC 74151 diagram and truth table programmer manual EPLD cypress pin diagram of 74151 TTL IC rs flip-flop IC 7400 PLDS-MAX cy3342 programming manual EPLD CY7C341
Text: . By standardizing on a few MAX building blocks, the designer can replace hundreds of different 7400 , FOR 7C344) C340-4 Figure 4. Macrocell Block Diagram Functional Description j ^ P-TERMS , Functional Description (continued) the overall speed performance of the device. The MAX architec ture solves , such as multiple hierarchy levels, symbol edit ing, and a library of 7400 series devices as well as , largest of previous generation EPLDs. The density and flexibility of the CY7C340 family is accessed using


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PDF CY7C340 CY3200 CY3201 CY3202 CY3340 CY3340F CY3342 CY3342F CY3342R CY3344 IC 7400 diagram and truth table IC TTL 7400 diagram and truth table IC 74151 diagram and truth table programmer manual EPLD cypress pin diagram of 74151 TTL IC rs flip-flop IC 7400 PLDS-MAX programming manual EPLD CY7C341
TTL 7400

Abstract: 7400 TTL earom TTL 7400 data sheet D9 DG transistor VSS28
Text: . FUNCTIONAL BLOCK DIAGRAM cs Copyright © 1977 by NCR Corporation Dayton, Ohio, U.S.A. All Rights Reserved , °C Stresses above "absolute maximum ratings" may result in damage to the device. Functional operation of , 100 ms Simultaneous Erasure of All Data Minimum Data Retention — 10" Read Accesses/Word Before , charge into the oxidenitride interface at the gate insulator of the 8192 MNOS memory transistors. When , in the threshold voltage of the selected memory transistors. Stored data may be accessed a minimum


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PDF 8192-BIT 11-Bit TTL 7400 7400 TTL earom TTL 7400 data sheet D9 DG transistor VSS28
2011 - Not Available

Abstract: No abstract text available
Text: Quad IF Receiver AD6657A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND , 24 Functional Block Diagram . 1 , ; functional operation of the device at these or any other conditions above those indicated in the operational , performance, low power, and small size are desired. The device consists of four high performance ADCs and NSR digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated


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PDF AD6657A 11-bit, MO-275-EEAB-1 144-Ball BC-144-1) AD6657ABBCZ AD6657ABBCZRL AD6657AEBZ
2011 - AD951x

Abstract: No abstract text available
Text: AD6657A FUNCTIONAL BLOCK DIAGRAM AGND DRVDD DRGND AD6657A VIN+A VIN­A VCMA VIN+B VIN­B VCMB VIN+C , Functional Block Diagram . 1 General Description , time is dependent on the value of the decoupling capacitors. Data Output Timing Diagram N­1 N VIN N , stress rating only; functional operation of the device at these or any other conditions above those , , and small size are desired. The device consists of four high performance ADCs and NSR digital blocks


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PDF 11-bit, ANSI-644 10-21-2010-B MO-275-EEAB-1 144-Ball BC-144-1) AD6657ABBCZ AD6657ABBCZRL AD6657AEBZ AD951x
2011 - Not Available

Abstract: No abstract text available
Text: Quad IF Receiver AD6657A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND , Functional Block Diagram . 1 Timing , ; functional operation of the device at these or any other conditions above those indicated in the operational , performance, low power, and small size are desired. The device consists of four high performance ADCs and NSR digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated


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PDF AD6657A 11-bit, MO-275-EEAB-1 144-Ball BC-144-1) AD6657ABBCZ AD6657ABBCZRL AD6657AEBZ
pin diagram 7400 series

Abstract: CI 7474 hs 111-0 7400 fan-out 74164 TTL CI 7400 7474 pin out diagram CI 7400 ttl 74164 HS5212
Text: parallel and serial output. All models have a maximum conversion time of 13 (u s which allows full accuracy , 5211/14), ±10 volts (HS 5212/15), and 0 to +10 volts (HS 5216). For each of these input ranges, the user has the option of specifying a model complete with an internal reference or for improved absolute , the entire operating temperature range. All models of the HS 5210 Series may be procured for , Logic "1" Serial Output Parallel Output (See Timing Diagram ) Fanout-High Fanout- Low INPUT HIGH


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PDF 12-Bit 24-Pin, MIL-STD-883 24-pin o11-o11- HS52XXC HS52XXB 12-Bits pin diagram 7400 series CI 7474 hs 111-0 7400 fan-out 74164 TTL CI 7400 7474 pin out diagram CI 7400 ttl 74164 HS5212
MMS-128

Abstract: L122N
Text: Generator STo1 MMS- FOi C4Ï Figure 1 - Functional Block Diagram 3-3 MT8920B CMOS , device as shown in the functional block diagram in Figure 1. The parallel port provides direct access to , performed by the address generator shown in the functional block diagram (see Figure 1). Figures 4 c & d , testing. Figure 20 - ST-BUS Timing Diagram 3-24 CMOS MT8920B Figure 21 - Format of 2048 , pulse used to synchronize the STPA to the_2048 kbit/s ST-BUS stream. The first falling edge of C4i


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PDF MT8920B 120nsec MT8920BE MT8920BC MT8920BP MT8920BS MT8920B CL-150pF MMS-128 L122N
FD100 diode

Abstract: 8832 "pin compatible" pin diagram 7400 series 7400 fan-out si 7831 pin diagram 7400 AM8832X DM8831J DM8831N DM8832J
Text: assurance testing in compliance with MIL-STD-883 FUNCTIONAL DESCRIPTION The Am78/8831 and Am78/8832 line , of different channels are tied together, and outputs of all channels except one are forced into the third high impedance state by having at least one of the channel disable inputs HIGH. The channel that is enabled has both channel disable inputs LOW, and the low-output impedance of this output at both Jogic levels controls the level of the bus, provides good capacitance drive and insures good waveform


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PDF Am78/8831 Am78/8832 DM78/8831 DM78/8832 MIL-STD-883 Am9615 FD100 diode 8832 "pin compatible" pin diagram 7400 series 7400 fan-out si 7831 pin diagram 7400 AM8832X DM8831J DM8831N DM8832J
cy7c345

Abstract: 7C340 Signal Path Designer IC TTL 7400 free
Text: , the designer can replace hundreds of different 7400 se ries p art num bers curren tly used in m ost , capable of implementing high density custom logic functions · Advanced 0.8 micron double metal CMOS EPROM , compatible machines - Hierarchical schematic capture with 7400 series TTL and custom Macrofunctions - State , simulation - Graphical interactive entry of waveforms T h e Cypress M ultiple A rray M a trix (M A X TM , onolithic M emories Inc. IBM® is a registered tradem ark of International Business Machines Corporation. IBM


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PDF CY7C340 cy7c345 7C340 Signal Path Designer IC TTL 7400 free
1997 - W5W26

Abstract: honeywell strip recorder 112
Text: reports . q q q q q EN0I- 7400 04/96 3 DPR180 FUNCTIONAL SPECIFICATIONS Technical , Action ENOI- 7400 04/96 Up to 36 input contacts, organized In groups of 6 contacts per card Dry , DPR180 180 MM DIGITAL STRIP CHART RECORDER EN0I- 7400 04/96 PRODUCTION SPECIFICATION SHEET , documented charts at any speed, and in different formats, providing an attractive presentation of the process data. The large, bright display, with fluorescent chart illumination, provides easy viewing of


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PDF DPR180 EN0I-7400 W5W26 honeywell strip recorder 112
2003 - U1 LM 555

Abstract: PDM-101 R101 CHROMASIC 1
Text: , Green, and Blue) 7400 cd Indicates 50% of peak 0.32 Red, 0.50 Green, 0.18 Blue 0'/0m Footcandles , 617 423 9998 · info@colorkinetics.com · www.colorkinetics.com DLE R-101 functional flow diagram , module intended for integration into a wide variety of OEM lighting products and custom installations , temperature of the sub-system. With simple control and power input, DLE R-101 delivers a broad range of color , bit control of the emitted color. Thus, DLE R-101 can be instructed to produce over 16 million


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PDF R-101 DMX512 R-101 PDM-101 PDM-101 24VDC U1 LM 555 R101 CHROMASIC 1
7400 signetics

Abstract: 9321DC 80286 address decoder 8309 aml 10 series electrical connections 9321DM Am9321
Text: . Functional terms- taoder/Demultiplexer On the basis of an applied instruction, fanels of communication are , OSO'0 ? Am9321 Dual Demultiplexer/One-of-Four Decoder Distinctive Characteristics • Dual 1- of , compliance with • Active LOW enable for each decoder Ml L-STD-883 FUNCTIONAL DESCRIPTION The Am9321 dual demultiplexer/one-of-four decoder consists of two identical independent decoders. Each decoder accepts two , in decoding in high-speed memory systems. LOGIC SYMBOL mr TTTT vcc Fin lb GND Pin 8 LOGIC DIAGRAM


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PDF Am9321 L-STD-883 Am9321 7400 signetics 9321DC 80286 address decoder 8309 aml 10 series electrical connections 9321DM
ic 7483 BCD adder

Abstract: 9N01 ic 7483 full adder IC 7490 pin configuration function of ic 7490 9N03 7401 ic configuration TIC 8213 pin configuration of ic 7492 Fairchild 9311
Text: SELECTOR GUIDE/ FUNCTIONAL INDEX MSI ARITHMETIC OPERATORS ADDERS, A.L.U.'S, COMPARATORS, MULTIPLIERS Function Type No. Description Number of Bits t pd ns 9380 9304 93H183 9382 9383 9340 93 L 40 9341 93S41 , 7400 8200 8210 8211 8213 8220 8223 8280 8281 8283 i i FAIRCHILD PIN FOR PIN REPLACEMENT FAIRCHILD FUNCTIONAL EQUIVALENT NATIO NAL 8290 FAIRCHILD PIN FOR PIN REPLACEMENT 93196 93197 9300 9309 9310 9311 9312 9316 9322 FAIRCHILD FUNCTIONAL EQ UIVALENT N ATIO NAL 8533 8550 8551 8560 8563 8570 8580


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PDF 93H183 93S41 93S42 93L24 93S62 93H87 8-20LENT 9N107, FJH101 FJH111 ic 7483 BCD adder 9N01 ic 7483 full adder IC 7490 pin configuration function of ic 7490 9N03 7401 ic configuration TIC 8213 pin configuration of ic 7492 Fairchild 9311
earom

Abstract: CI 2811 7400 TTL ITT 7400 TTL 7400 rise and fall time
Text: o-»-a2 o-»- a3 o—► A4 O—-A5 O-H R O FUNCTIONAL BLOCK DIAGRAM C/Î -W 3 0) u 13 U < a) J o , * Stresses above "absolute maximum ratings" may result in damage to the device. Functional operation of , Time 100 ms Simultaneous Erasure of All Data Minimum Data Retention — 10" Read Accesses/Word Before , interface at the gate insulator of the 8192 MNOS memory transistors. When the writing voltage is removed, the charge trapped at the interface is manifested as a negative shift in the threshold voltage of the


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PDF 8192-BIT 11-Bit earom CI 2811 7400 TTL ITT 7400 TTL 7400 rise and fall time
CY7C341

Abstract: No abstract text available
Text: to be routed throughout the chip. The speed and density of the CY7C341 allows it to be used in a wide range of applications, from replacement of large amounts of 7400 series TTL logic, to complex controllers and multi-function chips. W ith greater than 37 times the functionality of 20-pin PLDs, the CY7C341 allows the replacement of over 75 TTL devices. By replacing large am ounts of logic, the CY7C341 , % user configurable, allowing the devices to accommodate a variety of independent logic functions. The


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PDF CY7C341 84-pin CY7C341 20-pin
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