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LTC3444EDD#PBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TRPBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD#TR Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC3444EDD Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
CYCLONE-3-MERCURYCODE-REF Texas Instruments Cyclone III-based MercuryCode
STELLARIS-3P-CODER-DPROBE430-DEVBD Texas Instruments Red Suite 2

FET MARKING CODE Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
FMC141401-02

Abstract: fujitsu gaas marking code Fujitsu K022 FLL300-2 FUJITSU L101 FSX52WF FLL55 fujitsu x51 FLL300-1 FLL200-2
Text: the FET in a circuit, the circuit gate and drain connections should be shorted to ground. 3) When soldering the FET leads, an iron with a grounded tip is required. B. CIRCUIT INSTALLATION 1) Screw , . Prior to soldering, the FET and the amplifier case should be cleaned using acetone followed by an , . During reflow, pressure on the FET is recommended to minimize solder thickness. The gate terminal and , source flange, contamination and long term degradation of thermal resistance between the FET package and


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2001 - MARKING code VO SMD fet

Abstract: marking cdm smd 2a 3 PIN fet FET Design Catalog
Text: , packages, availability and ordering Ordering code (12NC) Marking /Packing IC packing info Download PDF File , INTEGRATED CIRCUITS CBT3125 Quadruple FET bus switch Product data File under Integrated , Quadruple FET bus switch CBT3125 DESCRIPTION The CBT3125 quadruple FET bus switch features , +85 °C ORDER CODE CBT3125D CBT3125DB CBT3125DS CBT3125PW DRAWING NUMBER SOT108-1 SOT337-1 SOT519 , /packaging. 2001 Dec 12 2 853-2309 27452 Philips Semiconductors Product data Quadruple FET


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PDF CBT3125 ICL03 CBT3125 125-type JESD78 SA00562 08-Jan-03) MARKING code VO SMD fet marking cdm smd 2a 3 PIN fet FET Design Catalog
2010 - FET marking code g5d

Abstract: PG2179TB marking code C3E SOT-89 marking code C1E mmic marking code C1G mmic PC8230TU PG2163T5N sot-23 g6g 2SC3357/NE85634 marking code C1H mmic
Text: ). 53 6. MARKING /PART NUMBER , . 54 6.2 Discrete rank, marking and specification list (Target devices: Minimold, S01, 75, 79A, 84C , Circuits 5 (2) GaAs Device products HJ-FETs (Hetero Junction FET ) Discretes FETs MES , PRODUCTS OPERATED AT 3 TO 10 V 20.0 NE55xxxxxx : Si LDMOS FET NESG2xxxx : SiGe HBT 10.0 NE5511279A , (NE68939) 2SC5289 (NE69039) NE5500134 Mobile Comm., PDC, GSM, Power Amp., Power MOS FET


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PDF R09CL0001EJ0100 PX10727EJ02V0PF) FET marking code g5d PG2179TB marking code C3E SOT-89 marking code C1E mmic marking code C1G mmic PC8230TU PG2163T5N sot-23 g6g 2SC3357/NE85634 marking code C1H mmic
nec mosfet marked v75

Abstract: NEC Ga FET marking code T79 marking code C1G mmic FET marking code g5d LGA 1155 PIN diagram MMIC SOT 363 marking CODE 77 marking code C1H mmic PB1507 PC8230TU marking code C1E mmic
Text: ). 55 6. MARKING /PART NUMBER , . 56 Selection Guide PX10727EJ02V0PF 5 6.2 Discrete rank, marking and specification list , ) GaAs Device products HJ-FETs (Hetero Junction FET ) Discretes FETs MES FETs Power FETs , AT 3 TO 10 V 20.0 NE55xxxxxx : Si LDMOS FET NESG2xxxx : SiGe HBT 10.0 NE5511279A (@7.5 V


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PDF G0706 PX10727EJ02V0PF nec mosfet marked v75 NEC Ga FET marking code T79 marking code C1G mmic FET marking code g5d LGA 1155 PIN diagram MMIC SOT 363 marking CODE 77 marking code C1H mmic PB1507 PC8230TU marking code C1E mmic
2010 - SLG55021

Abstract: SLG55021-xxyyzzV SLG55021-xxyyzzVTR SLG55020 FET marking code Silego Technology high voltage gate driver
Text: Source Voltage Package Top Marking System Definition 8 7 6 5 Part ID Assembly Code , Input Shut Down# - Low True Signal which immediately turns FET off GND 4 GND Ground D 5 Input FET Drain Connection S 6 Input Source Connection G 7 Output FET Gate Drive Output Output CMOS Open Drain - Power Good, indicates external FET fully on PG 8 CMOS Logic Level. High True Overview The SLG55021 N-Channel FET Gate Driver is used


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PDF SLG55021 SLG55020 SLG55020 SLG55021 SLG55021-xxyyzzV SLG55021-xxyyzzVTR FET marking code Silego Technology high voltage gate driver
2010 - SLG55321

Abstract: datecode G1
Text: FET Drain Connection (Connect to FET with highest VD voltage) S/DIS1 6 Input/Output CMOS , /G2/G3 7 Output FET Gate Drive for FET1, FET2, FET3. A minimum of a 1k resistor must be , exceed 5V. Overview The SLG55321/320 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level input. Intended as a , `Low Drive' version of the device, SLG55320 is available to support applications where FET Vgs cannot


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PDF SLG55321 SLG55320 SLG55321 datecode G1
2010 - SLG55221

Abstract: FET MARKING 600 V logic level fet fet MARKING g2 fet n-channel pin configuration
Text: GND 4 GND Ground D 5 Input FET Drain Connection (Connect to FET with highest VD , 7 Output FET Gate Drive for FET1, FET2 PG 8 Output CMOS Power Good Signal CMOS Logic Level Discharge Connection for Load2 Overview The SLG55221/220 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS , Drive' version of the device, SLG55220 is available to support applications where FET Vgs cannot exceed


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PDF SLG55221 SLG55220 SLG55221 FET MARKING 600 V logic level fet fet MARKING g2 fet n-channel pin configuration
2010 - SLG55221

Abstract: fet n-channel pin configuration FET marking code
Text: GND 4 GND Ground D 5 Input FET Drain Connection (Connect to FET with highest VD voltage) S/DIS1 6 Input/Output G1/G2 7 Output FET Gate Drive for FET1, FET2 PG , Overview The SLG55221/220 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level input. Intended as a supporting control , available to support applications where FET Vgs cannot exceed 8V. Ordering Information Part Number


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PDF SLG55221 SLG55220 SLG55221 fet n-channel pin configuration FET marking code
2010 - slg55221

Abstract: SILEGO
Text: #. Discharge Connection for Load2 GND 4 GND Ground D 5 Input FET Drain Connection (Connect to FET with highest VD voltage) S/DIS1 6 Input/Output G1/G2 7 Output FET Gate , Connection for Load1 Overview The SLG55251 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level input. Intended , VG not ramping FET = OFF - 0.1 - 1 A VG ramping FET = OFF to ON - 600


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PDF SLG55251 slg55221 SILEGO
2007 - 200 Amp mosfet

Abstract: mosfet tetrode BCR108S BG5412K FET marking code
Text: . Manufacturer 2005, June Date code (Year/Month) Pin 1 marking Laser marking BCR108S Type code , =D* 5=S Marking 6=D* K2s * For amp. A; * for amp. B 180° rotated tape loading orientation , VG1S 5 VGG Drain current ID = (VGG ), amp. B Drain current of FET A and FET B VDS = 5V, VG2S = 4V as function of Gate 1 FET B (connected to VGG, VGG =gate1 supply voltage) 28 mA 22 56K mA FET A 24 68K 18 82K 16 ID 20 18 ID 22 100K 16 14


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PDF BG5412K BG5421K OT363 200 Amp mosfet mosfet tetrode BCR108S BG5412K FET marking code
2007 - BCR108S

Abstract: BG5412K FET marking code
Text: ) Pin 1 marking Laser marking BCR108S Type code Standard Packing Reel ø180 mm = 3.000 Pieces , =S Marking 6=D* K2s * For amp. A; * for amp. B 180° rotated tape loading orientation available 1 , Drain current of FET A and FET B VDS = 5V, VG2S = 4V as function of Gate 1 FET B (connected to VGG, VGG =gate1 supply voltage) 28 mA 22 56K mA FET A 24 68K 18 82K 16 , 8 8 FET B 6 6 4 4 2 2 0 0 1 2 3 4 V 0 0 6 0.2


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PDF BG5412K OT363 BCR108S BG5412K FET marking code
2008 - Not Available

Abstract: No abstract text available
Text: 10.0 10 3.2 × 1.6 × 1.6 (EIA code : 1206) CH8 Description CH8 uses an external FET . It is , 20 1.6 × 0.8 × 0.8 (EIA code : 0603) Table 29. Recommended Parts for FET (CH8) VENDOR TYPE , -channel switching dc/dc converter, and seven channels have integrated power FET . CH2/4 are configured for H bridge , TPS65530ARSLR TOP-SIDE MARKING TPS65530A Package drawings, thermal data, and symbolization are available , FET 3 SW4I I Boost-side terminal of coil for CH4 4 VOUT4 O Output of CH4 5


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PDF TPS65530A SLVS835C
2007 - Not Available

Abstract: No abstract text available
Text: × 1.15 (EIA code : 1206) Table 25. Recommended Parts for FET (CH8) VENDOR TYPE NO. ID (DC , -channel switching dc/dc converter, and seven channels have integrated power FET . CH2/4 are configured for H bridge , TPS65530RSLR TOP-SIDE MARKING TPS65530 Package drawings, thermal data, and symbolization are available , FET 3 SW4I I Boost-side terminal of coil for CH4 4 VOUT4 O Output of CH4 5 , . 12 VCC2 P Power supply at CH2 buck-side FET from battery 13 SW2S O Buck-side


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PDF TPS65530 SLVS744C
2007 - Not Available

Abstract: No abstract text available
Text: 2005, June Date code (Year/Month) Pin 1 marking Laser marking BCR108S Type code Standard , =G2 3=G1* 4=D* 5=S Marking 6=D* K2s * For amp. A; * for amp. B 180° rotated tape , current of FET A and FET B VDS = 5V, VG2S = 4V as function of Gate 1 FET B (connected to VGG, VGG =gate1 supply voltage) 28 mA 22 56K mA FET A 24 68K 18 82K 16 ID 20 18 ID 22 100K 16 14 120K 12 150K 10 14 12 180K 10 8 8 FET B


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PDF BG5412K OT363
2008 - Not Available

Abstract: No abstract text available
Text: — 1.6 (EIA code : 1206) CH8 Description CH8 uses an external FET . It is based on , (EIA code : 0603) Table 29. Recommended Parts for FET (CH8) VENDOR TYPE NO. ID (DC) (N-ch) (A , -channel switching dc/dc converter, and seven channels have integrated power FET . CH2/4 are configured for H bridge , TPS65530ARSLR TOP-SIDE MARKING TPS65530A Package drawings, thermal data, and symbolization are available , for CH4 low-side FET 3 SW4I I Boost-side terminal of coil for CH4 4 VOUT4 O


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PDF TPS65530A SLVS835A
DEVICE MARKING CODE 41

Abstract: sot markings sot23 markings marking code T1 Code sot-23 on semiconductor marking CODE box SOT23 marking 41 sot23
Text: -23 package has a device marking and a date code etched on the device. The generic example below depicts both the device marking and a representation of the date code that appears on the SOT-23 package. ABCD , ANY FET product. Precautions include, but are not limited to, the implementation of static safe workstations and proper han dling techniques. Additionally, it is very important to keep FET devices in their , Fold Box Add an "RLR" suffix and the appropriate Style code * to the device title to order the Fan Fold


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PDF OT-23 DEVICE MARKING CODE 41 sot markings sot23 markings marking code T1 Code sot-23 on semiconductor marking CODE box SOT23 marking 41 sot23
2014 - UB261

Abstract: No abstract text available
Text: QW-R502-A27.b UB261  Preliminary CMOS IC MARKING INFORMATION PACKAGE VOLTAGE CODE (Note) SOT-26 MARKING XX Note: Refer to Serial Code List  SERIAL CODE LIST Model Code , : Ordering Number UB261G-xx-AG6-R xx: Output Voltage, refer to Marking Information. www.unisonic.com.tw , control: FET gate connection pin For current sense and charger detection input pin For charge control: FET gate connection pin Test pin for delay time measurement Positive power input Negative power


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PDF UB261 UB261 OT-26 QW-R502-A27
2001 - R3212

Abstract: R3210
Text: Ground and Case Output +5V, VDD 230 200 0.071 (1.8) SQ. Marking is shown on top 0.165 (4.2) PAD 1 , ( ). PAD 4 ( VDD ) 053, (1.4) Max 0.200 ± .005 (5.1) PAD 3 (OUTPUT) 3.3V Power Supply GND To adapt Fet , DISABLE "ONE" OR "ZERO" VDD 1 4 FET PROBE 350 MHz SCOPE Y-OUTPUT "R" Package COUNTER To , TRISTATE Model R3210 R3212 FIXED OUTPUT Model R1210 R1212 Marking Letter ID* GO GP Marking Letter ID* GK GL Frequency Stability ±100 ppm ±50 ppm * See Marking Specification Input


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PDF R1210, R1212 R3210, R3212 R1210 R3212 R3210
1998 - NEC Relay Date Codes

Abstract: FET marking codes NEC MARKING codes nec gaas fet marking
Text: DATA SHEET Solid State Relay OCMOS FET PS7241-2B 8-PIN SOP, 400 V BREAK DOWN VOLTAGE NORMALLY CLOSE TYPE 2-ch Optical Coupled MOS FET DESCRIPTION The PS7241-2B is a solid state relay containing , FET 6. MOS FET 7. MOS FET 8. MOS FET 1 2 3 7.0±0.3 4.4 4 2.05+0.08 ­0.05 0.15+0.10 , Voltage Power Dissipation Peak Forward Current MOS FET Break Down Voltage Continuous Load Current Pulse , Forward Voltage Reverse Current MOS FET Off-state Leakage Current Output Capacitance Coupled LED Off-state


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PDF PS7241-2B PS7241-2B PS7241-2B-F3, E72422 NEC Relay Date Codes FET marking codes NEC MARKING codes nec gaas fet marking
2001 - date code marking NEC

Abstract: code marking NEC NEC MARKING CODE RELAY code marking NEC NEC Date code Marking nec gaas fet marking gaas fet marking a gaas fet marking C LOT CODE NEC Nec AC 160
Text: ) Rank Code Nothing Ink marking N Laser marking 2 Preliminary Data Sheet P13560EJ2V0DS PS7200H , PRELIMINARY DATA SHEET Solid State Relay OCMOS FET PS7200H-1A 4-PIN SOP, 2.2 LOW ON-STATE RESISTANCE 1-ch Optical Coupled MOS FET DESCRIPTION The PS7200H-1A is a low on-state capacitance solid , -1A PACKAGE DIMENSIONS (UNIT: mm) 4.0±0.5 TOP VIEW 4 3 1. LED Anode 2. LED Cathode 3. MOS FET 4. MOS FET , 0.25 M 0.5±0.3 MARKING EXAMPLE 200H 001 No.1 pin Mark *1 Applicable type numbers are


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PDF PS7200H-1A PS7200H-1A date code marking NEC code marking NEC NEC MARKING CODE RELAY code marking NEC NEC Date code Marking nec gaas fet marking gaas fet marking a gaas fet marking C LOT CODE NEC Nec AC 160
R3212

Abstract: R1212 R3210
Text: the marking is: PN Date Code ID Year Week MF R (3) Electronics Models (1) (2) ENVIRONMENTAL , 230 200 0.071 (1.8) SQ. 160 140 Marking is shown on top 0.205, (5.2) Maximum 0.165 , .005 (5.1) "R" Package FET PROBE VDD 053, (1.4) Max VDD PAD 3 (OUTPUT) 3.3V Power Supply MA 1 350 MHz SCOPE Y-OUTPUT 4 IMF LOAD 2 GND To adapt Fet probe to , Marking Letter ID* Model Marking Letter ID* Frequency Stability R3210 45/55 Model


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PDF R1210, R1212 R3210, R3212 R1210 R3212 R1212 R3210
2004 - 10BQ040

Abstract: EIA-541 IRFR120 IRFU120 IRLR8103V IRLR8503 RLR8503 fet dpak FET marking code
Text: offers an extremely low combination of Qsw & RDS(on) for reduced losses in control FET applications , Total Gate Charge Control FET * Qg ­ 15 20 VGS= 5V, ID= 15A, VDS =16V, Total Gate Charge Sync FET * Qg ­ 13 17 VGS = 5V, VDS < 100mV Pre-Vth Gate-Source Charge Qgs1 , , microprocessor power applications. The IRLR8503 (Figure 1) was optimized for the control FET socket, while the IRLR8103V was optimized for the synchronous FET function. Table 2 ­ New Charge Parameters New Charge


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PDF 5095A IRLR8503PbF IRLR8503 combi19 EIA-481 EIA-541. EIA-481. 10BQ040 EIA-541 IRFR120 IRFU120 IRLR8103V RLR8503 fet dpak FET marking code
2004 - IRF FET

Abstract: MOSFET LOSSES SYNC BUCK FET MARKING QG fet data book free download IRFR120 EIA-541 IRLR8103V IRLR8503 RLR8503 fet D-PAK package
Text: offers an extremely low combination of Qsw & RDS(on) for reduced losses in control FET applications , Total Gate Charge Control FET * Qg ­ 15 20 VGS= 5V, ID= 15A, VDS =16V, Total Gate Charge Sync FET * Qg ­ 13 17 VGS = 5V, VDS < 100mV Pre-Vth Gate-Source Charge Qgs1 , , microprocessor power applications. The IRLR8503 (Figure 1) was optimized for the control FET socket, while the IRLR8103V was optimized for the synchronous FET function. Table 2 ­ New Charge Parameters New Charge


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PDF 5095A IRLR8503PbF IRLR8503 combi318 EIA-481 EIA-541. EIA-481. IRF FET MOSFET LOSSES SYNC BUCK FET MARKING QG fet data book free download IRFR120 EIA-541 IRLR8103V RLR8503 fet D-PAK package
2009 - Not Available

Abstract: No abstract text available
Text: /appnotes/an-1152.pdf PQFN 5x6 Outline "C" Part Marking INTERNATIONAL RECTIFIER LOGO DATE CODE , digits") MARKING CODE (Per Marking Spec) LOT CODE (Eng Mode - Min last 4 digits of EATI#) (Prod , and synchronous FET in one package Low charge control MOSFET (8.3 nC typical) Low RDSon synchronous , FET TOP VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.3V Q2 - Synchronous FET TOP VGS 10V 5.0V 4.5V , Q1 - Control FET 10000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds +


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PDF IRFH7911PbF
FET marking code

Abstract: fet junction transistor
Text: protective cover UL/Cul, TUV approval and CE marking Specifications Type FET version Current 10 A , GN single-phase GND DC output FET transistor versions 10, 15 and 30 A Bipolar , protective cover Code 84 137 850 84 137 860 84 137 870 84 134 850 84 134 860 84 134 870 84 137 750 , (rms) Input/output capacitance (pF) Material housing Material baseplate Weight FET 10A : 1 - 200 FET 15A : 1 - 100 FET 30A : 1 - 50 Bipolar 10A : 3 - 60 FET 10A : 14 FET 15A : 1 FET 30A : 1


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