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TPS650006RTET Texas Instruments 2.25MHz Step-Down Converter with Dual LDOs & SVS Power Management IC (PMIC) 16-WQFN -40 to 85
THS770006IRGET Texas Instruments High-Speed Fully Differential ADC Driver Amplifier with +6dB Fixed Gain 24-VQFN -40 to 85
TPS650006RTE Texas Instruments IC 1.4 A SWITCHING REGULATOR, 2847 kHz SWITCHING FREQ-MAX, PQCC16, 3 X 3 MM, PLASTIC, QFN-16, Switching Regulator or Controller
TPS650006RTER Texas Instruments 2.25MHz Step-Down Converter with Dual LDOs & SVS Power Management IC (PMIC) 16-WQFN -55 to 125
THS770006IRGER Texas Instruments High-Speed Fully Differential ADC Driver Amplifier with +6dB Fixed Gain 24-VQFN -40 to 85
6P30006ANLGI8 Integrated Device Technology Inc VFQFPN-24, Reel
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EYN257T-0006-FF Black Box Corporation Newark element14 246 $34.48 $25.98

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EYN257T-0006-FF Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2005 - EYN257T-0025-FF

Abstract: EYN257T-0006-FF
Text: 1/22/2014 EYN257T-0006-FF , DB9 Serial Null-Modem Cables (EYN257T-0010-MF) - Black Box Change , Quantity Homepage Fem ale/Fem ale 1.8 m DB9 Serial Null-Modem Cables EYN257T-0006-FF £12.17 3.0 m DB9 Serial Null-Modem Cables EYN257T-0010- FF £12.85 4.5 m DB9 Serial Null-Modem Cables EYN257T-0015- FF £14.20 7.6 m DB9 Serial Null-Modem Cables EYN257T-0025- FF  , -0010-MF 1/2 1/22/2014 EYN257T-0006-FF , DB9 Serial Null-Modem Cables (EYN257T-0010-MF) - Black Box


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PDF EYN257T-0006-FF, EYN257T-0010-MF) RS-232/V 115-ohm 286/11985/DB9-Serial-Null-Modem-Cables/V3 O3/EYN257T-0010-MF EYN257T-0025-FF EYN257T-0006-FF
ADC71

Abstract: No abstract text available
Text: ± 0.006 (J) ± 0 .0 0 3 (K ) * * * * T o 14 Bits (B Grade) % o fF S R J % o fF S R % o fF S R % o fF S R LSB % o fF S R Guaranteed * * * % ofF S R /% A V s % ofF S R /% A V s , linearity error less than ±0.003% (± 0.006 % for J and A grades) at 25°C. 2. Conversion time is 35|is , ADADC72KD AD ADC72AD AD ADC72BD ± 0.006 % of FSR ±0.003% of FSR ± 0.006 % of FSR ±0.003% of FSR ± 0.006


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PDF 16-Bit ADC71/AD ADC72 16-Bh ADC71 ADC72 16-bit 32-pin
Not Available

Abstract: No abstract text available
Text: DATE 2 -2 -0 6 .100 [2.54] TYP. .050 [1.27] TYP. .050 [1.27] 0.035 [0.89] ±.003 [0.08] (8) f r i 0006 [0.15]~| 065 [1.65] ±.003 [0.08] (2) f r i 0.006 [0.1571 3-21-06 REV A6 A7 ECN APP'D. BY JM SAW -7549 + 4 - f-f I f-f-PIN # 1 7 .100 [2.54] L T B .153 [3.89] -25Y 6-35] .128 [3.25] B .125 [3.18] ( 2) fr| 0006 [0.15]1 t .085 [2.16] .450 [11.43]- , SEE PR026-01. 1 ff T .267 [6.78] MAX 3. DIMENSIONS AND TOLERANCES COMPLY WITH FCC/CFR 47


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PDF CT710116
2009 - NCP1294

Abstract: No abstract text available
Text: MARKING DIAGRAM GATE 1 ISENSE SYNC FF UV OV RTCT ISET 16 1 16 NCP1294EG AWLYWW , ˆ’72 V to 5.0 V/5.0 A Converter 160 k 20.25 k FF 10 GATE IRF634 SS LGND 330 pF , /Capacitor RTCT 6.0 V −0.3 V 1.0 mA 10 mA Feed Forward FF 6.0 V −0.3 V 1.0 , 90 125 ns Feed Forward ( FF ) Discharge Voltage IFF = 2.0 mA Discharge Current FF = 1.0 V − FF to GATE Delay Overcurrent Protection Overcurrent Threshold ISET = 0.5 V, Ramp


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PDF NCP1294 NCP1294 NCP1294D
2009 - NCP1294

Abstract: flyback transformer pin connections TL431 smd marking CT-39 948F
Text: GATE 1 16 ISENSE SYNC FF UV OV RTCT ISET 1 VC PGND VCC VREF LGND SS COMP VFB , 0.22 mF 11 V 51 k VIN (36 V to 72 V) GATE FF ISET OV UV VCC 10 22 mF , FF 6.0 V -0.3 V 1.0 mA 25 mA Error Amp Output COMP 6.0 V -0.3 V 10 mA , 90 125 ns Feed Forward ( FF ) Discharge Voltage IFF = 2.0 mA Discharge Current FF = 1.0 V FF to GATE Delay - Overcurrent Protection Overcurrent Threshold ISET = 0.5 V, Ramp


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PDF NCP1294 NCP1294 SOIC-16 TSSOP-16 NCP1294D flyback transformer pin connections TL431 smd marking CT-39 948F
2005 - Not Available

Abstract: No abstract text available
Text: GATE ISENSE SYNC FF UV OV RTCT ISET 1 VC PGND VCC VREF LGND SS COMP VFB 16 CS51 , 1. Application Diagram, 36 V−72 V to 5.0 V/5.0 A Converter 160 k 20.25 k FF 10 GATE , RTCT 6.0 V −0.3 V 1.0 mA 10 mA Feed Forward FF 6.0 V −0.3 V 1.0 mA 25 , ( FF ) Discharge Voltage IFF = 2.0 mA Discharge Current FF = 1.0 V FF to GATE Delay â , Soft−Start Clamp Offset FF = 1.25 V Soft−Start Fault Voltage OV = 2.15 V or LV = 0.85 V


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PDF CS51221 CS51221 CS51221D
1996 - qs7202

Abstract: QS32383 QS3383
Text: 512 x 9 1024 x 9 READ POINTER RESET LOGIC EXPANSION LOGIC FLAG LOGIC EF FF HF , 26 FL/RT FF 9 25 RS Q0 10 24 EF Q1 11 23 XO/HF NC 12 22 , Q3 Q0 Q1 Q2 Q3 Q8 GND D6 XI 8 EF 29 Q8 FF RS 5 Q2 XI D2 , FF RS FL/RT XI XO/HF 2 I/O I Read Clock I Write Clock O Empty Flag O , . 3 1 2 QS7201, QS7202 CONTROL OUTPUTS Full Flag ( FF ) The Full flag indicates that the FIFO


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PDF QS7201, QS7202 QS3383 QS7201 QS32383 QS7201 QS7202 MDSF-00001-06 QS32383 QS3383
2009 - NCP1294 D

Abstract: MOC81025 V33MLA1206A23 NCP1294 NCP1294EDBR2G NCP1294EDR2G BAS21 NCP1294D NCP1294EG 948F
Text: MARKING DIAGRAM GATE 1 ISENSE SYNC FF UV OV RTCT ISET 16 1 16 NCP1294EG AWLYWW , 2200 pF 0.01 mF 0.22 mF 11 V 51 k VIN (36 V to 72 V) GATE FF ISET OV UV , Feed Forward FF 6.0 V -0.3 V 1.0 mA 25 mA Error Amp Output COMP 6.0 V -0.3 V , 90 125 ns Feed Forward ( FF ) Discharge Voltage IFF = 2.0 mA Discharge Current FF = 1.0 V FF to GATE Delay - Overcurrent Protection Overcurrent Threshold ISET = 0.5 V, Ramp


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PDF NCP1294 NCP1294 SOIC-16 TSSOP-16 NCP1294D NCP1294 D MOC81025 V33MLA1206A23 NCP1294EDBR2G NCP1294EDR2G BAS21 NCP1294D NCP1294EG 948F
2005 - CS51221 D

Abstract: 948F CS51221 CS51221ED16 CS51221ED16G CS51221EDR16 CS51221EDR16G CS51221EDTB16G CS51221EDTB16R2G
Text: GATE ISENSE SYNC FF UV OV RTCT ISET 1 VC PGND VCC VREF LGND SS COMP VFB 16 CS51 , 330 pF 200 2200 pF 0.01 mF 0.22 mF 11 V 51 k VIN (36 V to 72 V) GATE FF , Feed Forward FF 6.0 V -0.3 V 1.0 mA 25 mA Error Amp Output COMP 6.0 V -0.3 V , 90 125 ns Feed Forward ( FF ) Discharge Voltage IFF = 2.0 mA Discharge Current FF = 1.0 V FF to GATE Delay - Overcurrent Protection Overcurrent Threshold ISET = 0.5 V, Ramp


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PDF CS51221 CS51221 SOIC-16 TSSOP-16 CS51221D CS51221 D 948F CS51221ED16 CS51221ED16G CS51221EDR16 CS51221EDR16G CS51221EDTB16G CS51221EDTB16R2G
QD03-2

Abstract: No abstract text available
Text: ] NC ] FL/RT ] RS ]E F ] XÖ/HF D1 [ 6 DO [ 7 xm FF [ Q0 [ Q1 C Q2 [ Q3 C Q8 C GND [ x i[ 8 FF , Clock In Expansion Clock Out/ Half-Full Flag FF RS FL/RT X \ XO/HF 2 QUALITY SEMICONDUCTOR , ( FF ) The Full flag indicates that the FIFO is full. The Full flag is asserted when there is only one , Zero Unchanged Increment*2* OUTPUTS FF HF H (3) (4) Mode Reset Retransmit Read/Write RS L H H , Increment*2' EF L (3) (4) OUTPUTS FF HF H (3) (4) H (3) (4) _ Notes: _ 1. The expansion inJXI


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PDF QS7201, QS7202 QS7201 10-ns 66-MHz QS7202 74bbfi03 QD03-2
20K180

Abstract: AD301A D566A AD565ATD
Text: * FUNCTIONAL BLOCK DIAGRAM R E F OUT V CC « P O L A R O FF (ÌÒ ) 10V S P A N t © D *COUT I I 4 A , % of F.S. Range pF V LSB % of F.S. Range LSB % of F.S. Range LSB to T m ax -1.5 ±1/4 ( 0.006 ) ±1/2 (0.012) -1.5 ±1/8 (0.003) ±1/4 ( 0.006 ) ACCURACY (Error Relative to Full Scale) +25°C T m in t0 T m a x ±1/2 (0.012) ±3/4 (0.018) ±1/4 ( 0.006 ) ±1/2 (0.012) DIFFERENTIAL NONLINEARITY , F.S. Range LSB % of F.S. Range LSB -1.5 ±1/4 ( 0.006 ) ±1/2 (0.012) -1.5 ±1/8 (0.003) ±1/4 ( 0.006


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PDF AD565A: AD566A: AD565A AD566A AD566A AD565A AD565A) AD566A) MIL-STD-883-Compliant 12-Bit 20K180 AD301A D566A AD565ATD
ADC71KD

Abstract: ADC72kd ADC72JD ADC71
Text: ±0.003% (± 0.006 % for J and A grades) at 25°C. 2. Conversion time is 35p.s typical to 14 bits with short , ) ± 0.006 % ofFSR ±0.003% of FSR ± 0.006 % of FSR ±0.003% of FSR ± 0.006 % of FSR ±0.003% of FSR Specification , % o fF S R J % o fF S R % o fF S R % o fF S R L SB % o fF S R G u a ra n te e d 0 .0 0 3 0.001 35 , p p m o fF S R /° C ppm o f FSRTC p p m o fF S R /° C CSB COB, CTC7 5 5 (m ax) 5 (m ax) 4 00 6 .3


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PDF 16-Bit ADADC71/ADADC72 645mW ADC71 ADC72 32-pin ADC71KD ADC72kd ADC72JD
Not Available

Abstract: No abstract text available
Text: than Ro n ° f m etal-gate CMOS analog switches. The O N /O FF control inputs are com patible with , 7 8 ]x c Ya 13 FUNCTION TABLE O n/O ff Control Input State of Analog Switch L H , r. t f Static or Dynamic Voltage Across Switch — Input Rise and Fall Time, O N /O FF , o G u a ra n te e d L im it - 5 5 to 25°C V|H Minimum H igh-Level Voltage O N/O FF , 6.3 8.4 1.5 2.1 3.15 6.3 8.4 V V|L M aximum Low -Level Voltage O N/O FF Control


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PDF C74VHC4066/D VHC4066 MC14066 HC4066A.
Not Available

Abstract: No abstract text available
Text: . The O N /O FF control inputs are com patible with standard CMOS outputs; with p ull-up resistors , ]x c FUNCTION TABLE O n/O ff Control Input State of Analog Switch L H Off On PIN , (Referenced to GND) - 0 . 5 to V q q + 0.5 V ■in DC Current Into or Out of O N/O FF , , All Package Types 100 20 Input Rise and Fall Time, O N /O FF Control Inputs (Figure 10) V q q , Minimum H igh-Level Voltage O N/O FF Control Inputs (Note 1) R0n = Per Spec 2.0 3.0 4.5 5.5


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PDF C74LVX4066/D 74LVX4066 MC74LVX4066 LVX4066 MC14066 HC4066A.
2007 - PGB1010603

Abstract: 04000015NR PGB1010603NR PGB1010402 iec 286 ST23 PGB1040805 free computer hardware notes PGB1010603MR B10106
Text: 0.20 (0.118" +/- 0.008") 0.15 +/- 0.08 ( 0.006 " +/- 0.003") 1.91 (0.075") 1.09 (0.043 , ") Description 0.15 +/- 0.08 ( 0.006 +/- 0.003") TYP Reflow Solder Wave Solder Reflow Solder 1.02 , 01 0603 MR Capacitance ( fF ) Voltage (V) LINES PROTECTED: 1000 01 = 1 line 50 02 800 = 2 , 00 fF = 1 pF 0.10 800 Dimensions: mm (inch) PGB102ST23 PGB1010603 PGB1010402 1.66 +/- 0.06 (0.066" +/- 0.003") 600 1.04 PGB1010603 0.15 +/- 0.08 PGB102ST23 ( 0.006 " +/- 0.003


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PDF PE7025-30 PGB1010603 04000015NR PGB1010603NR PGB1010402 iec 286 ST23 PGB1040805 free computer hardware notes PGB1010603MR B10106
Not Available

Abstract: No abstract text available
Text: 60 6 12 f-F re q u e n c y -G H z 70 18 Figure 1 This device is susceptible to damage , 0.002 0.002 0.003 0.003 0.003 0.003 0.004 0.004 0.004 0.005 0.005 0.005 0.005 0.005 0.006 0.006 0.007 0.007 0.007 0.006 0.004 0.006 S 21 ANG 33 33 23 13 3 -7 -1 7 -2 6 -3 7 -5 0 -6 6 -8 3 -1 0 5 -1 2 5 -1 4 , 0.003 0.003 0.004 0.004 0.004 0.004 0.004 0.004 0.005 0.005 0.006 0.006 0.006 0.007 0.007 0.007 0.006 0.004 0.006 S12 ANG 44 40 29 18 7 -3 -1 4 -2 3 -3 4 -4 6 -6 2 -81 -1 0 5 -1 2 5 -1 4 4 -1 5 7 -1 6 7 -1


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PDF TGS8632-XCC 18-GHz lnstrumentsTGS8632-XCC 43-dB circui632-XCC
HC4016

Abstract: 74HC4066
Text: 9 8 ]Y C ]xc FUNCTION TABLE O n/O ff Control Input L H State of Analog Switch Off On PIN , Voltage Across Switch O perating Temperature, All Package Types Input Rise and Fall Time, O N /O FF , /O FF Control Inputs Test Conditions R 0 n = Per Spec < 85°C 1.5 3.15 6.3 8.4 0.3 0.9 1.8 2.4 , 12.0 12.0 V|L M aximum Low -Level Voltage O N/O FF Control Inputs R 0 n = Per Spec V in M aximum Input Leakage Current O N/O FF Control Inputs M aximum Q uiescent Supply Current (per


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PDF MC54/74HC4066 HC4066 MC14016 MC14066. MC54/74HC4066/D C54/74HC4066/D HC4016 74HC4066
2013 - Not Available

Abstract: No abstract text available
Text: 0.18 (0.017" +/- 0.007”) ( 0.006 " +/- 0.003”) 1.91 (0.075") Description 0.15 +/- 0.08 ( 0.006 +/- 0.003") TYP Reflow Solder Wave Solder Reflow Solder 2.29 (0.090") 1.27 (0.050 , " +/- 0.004") 0.71 (0.028”) 0.86 (0.034”) 25 50 0 * Note: 1,000 fF = 1 pF Body Capacitance ( fF ) Reflow Solder Recommended for reflow soldering only WR = 3000 pieces, tape & reel , ( 0.006 +/- 0.003") TYP Wave Solder 1.02 (0.040") 0 1.02 (0.040") 1000 175 1.09


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PDF PE7025-30
sj 5550

Abstract: No abstract text available
Text: ] 6.98 [.275] 3 4 5 7 2. 1 6 [ . O85] D SPACES AT 2.54 [. 1 OO] 2.54 [. 1 OO] I ff ff II II II II II , ] DIA /4 0.006 ooooooooooooooooooooo-ooooooooooooooooooooo ooooooooooooooooooooo- RECOMMENDED P.C. BOARD LAYOUT SECTION T —" 3.05 [. 1 2 O] DIA (2 PLC) 0.006 2.54 [. 1 OO] OBSOLETE £ 5.08 [ . 2OO] OBSOLETE


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PDF 0S12-0038-05 EC0-09-024606 11MAY05 02NOV09 31MAR2000 19MAY05 us049721 2-0038-05-ALEX\5532447 sj 5550
Philips FA 261

Abstract: No abstract text available
Text: 3.000 - 22 CJE = 284.7 fF 23 VJE = 600.0 mV 24 MJE = 303.6 m 25 T F , equivalent circuit, SOT323. EV List of components (see Fig.18) DESIGNATION VALUE 2 fF c* 100 fF - L1 0.34 nH V T F= 1.701 V L2 0.10 nH ITF = 30.64 mA L3 0.34 nH 29 PTF = 0.000 deg Lb 0.60 nH 30 CJC = 242.4 fF Le 0.60 nH 31 V JC = , not been extracted, the default values are shown. mV 38 Note F 36 (note 1) 100 fF


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PDF BFS505 OT323 MBC87I0 OT323. OT323 Philips FA 261
2005 - 2005 pwm

Abstract: ISL6740A ISL6740AIVZA ISL6740 PTC NTC
Text: SC S/D Internal OT Shutdown 130 - 150 C Bi-Directional Synchronization UV/ FF + - S , Minimum Duty Cycle VERROR < CT Valley Voltage Maximum Duty Cycle VERROR > 4.75V, VUV/ FF = 2.5V , Accuracy TA = 25 C (Note 7) o TA = 105 C, |(F20V - F9V)/F9V|, UV/ FF = 2.00V (Note 4) o TA = 25 C, |(F20V - F9V)/F9V|, UV/ FF = 2.00V o TA = -40 C, |(F20V - F9V)/F9V|, UV/ FF = 2.00V (Note 4) Frequency Variation with VDD o Frequency Variation with VUV/ FF TA = 25 C, |(F4.25V ­ F2.00V)/ F2


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PDF ISL6740A FN9195 ISL6740 2005 pwm ISL6740A ISL6740AIVZA ISL6740 PTC NTC
aeg Si 42

Abstract: No abstract text available
Text: ] K 6.99 [.275] a 4 5 -7 2. 1 6 [ . O 8 5] D SPACES AT 2.54 [. 1 OO] ff f f f 0 ^ 0 ^ ft liii H g g g i 10.16 [.400] ff f f f liiii - SPACES AT 2.54 [. 1 OO] = G ff f| Éiil H m ® m fi h g m ® si h , ] 6.35+0.5 1 [.250+.020] A A r" A v -V 5.33 [.2 1 O] w w - 5.00 [.1 97] SECTION J —" 0.006 6.99 r-275] D , ] 0.94- 1 .09 [.037-, 043] DIA ^ -0- 0.006 RECOMMENDED P.C. BOARD LAYOUT THIS DRAWING IS A CONTROLLED


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PDF 0S12-0287-05 ECO-09-021 0DEC05 12SEP09 aeg Si 42
si4870

Abstract: No abstract text available
Text: (o n ) { & ) 0.006 @ V G S = 10 V Id (A) ±16 < > < * O o S O -8 D D I O D D , = 10 V, lD = 16 A 40 0.005 0.0075 40 0.65 1.1 0.006 Q V GS = 4.5 V, lD = 13 A 0.009 S V 5 A O , Total Gate Charge G ate-Source Charge G ate-D rain Charge Turn-O n Delay Tim e Rise Time Turn-O ff Delay , nC Q g s Q g d td (o n ) tr 22 30 150 140 80 ns td (o ff ) tf trr = 2.3 A, dl/dt = 100 A , apacitance 0.008 VGS = 4.5 \ 'w O I 0.006 VGS = 1 0 V -O I ro 0.004 o 0.002


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PDF 4870DY 26-Apr-99 si4870
2005 - 2005 pwm

Abstract: ISL6740 ISL6740A ISL6740AIVZA
Text: k GND SC S/D Internal OT Shutdown 130 - 150 C Bi-Directional Synchronization UV/ FF , Minimum Duty Cycle VERROR < CT Valley Voltage Maximum Duty Cycle VERROR > 4.75V, VUV/ FF = 2.5V , Accuracy TA = 25 C (Note 7) o TA = 105 C, |(F20V - F9V)/F9V|, UV/ FF = 2.00V (Note 4) o TA = 25 C, |(F20V - F9V)/F9V|, UV/ FF = 2.00V o TA = -40 C, |(F20V - F9V)/F9V|, UV/ FF = 2.00V (Note 4) Frequency Variation with VDD o Frequency Variation with VUV/ FF TA = 25 C, |(F4.25V ­ F2.00V)/ F2


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PDF ISL6740A FN9195 ISL6740 2005 pwm ISL6740 ISL6740A ISL6740AIVZA
1996 - PC 272c

Abstract: BF 179C ic 3773 BIT 3713 272c M68HC16 M68HC11 stk 4281 AM31 17C4
Text: byte of the address is assumed to be $00. Addresses $00­$ FF are thus accessed directly, using two-byte , Failure None NOCOP FFFC, FD Clock Monitor Fail None CME FFFE, FF RESET None , : PC point to the address of the first word of the instruction + $ 0006 . During execution of the , plus $ 0006 . The range of displacement for each type of branch is relative to this value. In addition , subroutine instruction is executed, PK : PC contain the address of the calling instruction plus $ 0006 . All


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PDF M68HC11 M68HC16 16-bit CPU16 PC 272c BF 179C ic 3773 BIT 3713 272c stk 4281 AM31 17C4
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