The Datasheet Archive

SF Impression Pixel

Search Stock

Hirose Electric Co Ltd
EX80-54S-SH(30) I/O Connectors EX80-54S-SH(30) ECAD Model
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000 Buy
Sager EX80-54S-SH(30) 0 500 - - - $6.13 $5.45 Buy Now

EX80-54S-SH(30) datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
EX80-54S-SH(30) EX80-54S-SH(30) ECAD Model Hirose Electric Connectors, Interconnects - Rectangular Connectors - Arrays, Edge Type, Mezzanine (Board to Board) - CONN RECEPT 54POS Original PDF

EX80-54S-SH(30) Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
100S

Abstract: DC250V no28
Text: EX 80 - 54 (50) S - SH (05) 1 2 3 4 5 EX 80 - 54 (50) P (01) 2 50 54 .5450 S. DIP0.9mm P. DIP0.9mm P1. DIP2.2mm 5 SH . 4 1 1 EX 2 , 30 28.2 (PCB =1 ) .45 6.8±0.05 2.8() 1.2 NO.100 3.9 9.6 11.7 7.8 (7 , () NO.50 33 (32.4) (31.5) 30 28.2 16.6±0.05 0.6±0.05 0.4±0.05 NO.2 16.6 HRS No , .28 No.29 No. 30 No.54 0.9 19.2 16.2 14.4 9.7 0.6 10.9 No.27 31.5 19.2 16.2


Original
PDF 100ps/div 100mV/div EX800. 100mA DC250V AC350V1 EX80-54 CL232-0606-5-05 CL232-0606-5-06 100S DC250V no28
EX80-54(50)P

Abstract: EX80-54S Bellows sh 523 EX80-100
Text: information qReceptacles EX 80 - 54 (50) S - SH (05) 1 2 3 4 5 : 54(50). 50 contacts , connectors (Shell ground tab length 2.2 mm) 5 Receptacle, with shutter SH : Built-in shutters 6 Separate , be placed on the PCB 1mm min. thick. 2 sPlugs q100 pos. 45.3 33 30 28.2 NO.2 Power , contact No.28 Power contact No.29 Signal contact No. 30 Signal contact No.54 Removable vacuum pick-up , sReceptacles (Without shutter) q100 pos. 43.4 33 30 28.2 16.6 0.6 NO.52 Power contact NO.51 Power


Original
PDF 100ps/div 100mV/div EX80-54(50)P EX80-54S Bellows sh 523 EX80-100
2010 - docking connector 35

Abstract: EX80-100
Text: -Nickel / tinned copper plated sOrdering information qReceptacles EX 80 - 54 (50) S - SH (05) 1 2 , ground tab length 2.2 mm) 5 Receptacle, with shutter SH : Built-in shutters 6 Separate specifications , Station Connectors sPlugs q100 pos. 45.3 33 30 28.2 16.6 NO.50 0.6 NO.2 Power contact NO.1 Power , thickness : 1 mm min.) 6.8±0.05 2.8(Through hole) 33 (32.4) (31.5) 30 28.2 16.6±0.05 0.6±0.05 0.4±0.05 0.9 , No.28 Power contact No.29 Signal contact No. 30 0.4 R0 .45 Ø1 8 25.2 27.3 30.2 Shell


Original
PDF 100ps/div 100mV/div EX80-P docking connector 35 EX80-100
2008 - EX80-54S

Abstract: pcb design 0,4 mm pitch EX80-100
Text: Contacts Insulator Shell Ordering information Receptacles EX 80 - 54 (50) S - SH (05) 1 2 3 , connectors (Shell ground tab length 2.2 mm) 5 Receptacle, with shutter SH : Built-in shutters 6 Separate , , Docking your Hirose sales representative. Plugs 100 pos. 45.3 33 30 28.2 NO.2 Power contact , 17.5 2-Ø1.3 +0.1(Through hole) 0 15.1 4.5 41.1 R0 Ø1.7 33 (32.4) (31.5) 30 28.2 , BRecommended PCB mounting pattern Power contact No.28 Power contact No.29 Signal contact No. 30 Signal


Original
PDF EX80-P EX80-54S pcb design 0,4 mm pitch EX80-100
2004 - EX80-54S

Abstract: EX80A-240S EX80-100
Text: qReceptacles EX 80 - 54 (50) S - SH (05) 1 2 3 4 5 : 54(50). 50 contacts mounted in a 54 , tab length 2.2 mm) 5 Receptacle, with shutter SH : Built-in shutters 6 Separate specifications : See , representative. sPlugs q100 pos. 45.3 33 30 28.2 NO.2 Power contact 16.6 (7) 10.9 NO , contact No.1 Power contact No.28 Power contact No.29 Signal contact No. 30 Signal contact No , shutter) q100 pos. 43.4 33 30 28.2 16.6 0.6 NO.52 Power contact NO.51 Power contact 8.8


Original
PDF
2011 - Not Available

Abstract: No abstract text available
Text: Temperature Range Symbol VDD Topr Ratings Min. 2.4 - 30 Typ. 2.8 Max. 5.5 100 Unit V Electrical , " PD="L" PD=2.8V Ta = 30 Ta = - 30 to 100 difference of IOUT : 0uA / 2uA VDD=2.45.5V VOS =5.0V IOS = , ±1.0 ±2.5 VDD = 2.8V Ta = - 30 to 100 Tacc Thys 7.5 ±1.0 10.0 ±2.5 12.5 Symbol Limits Min. Typ. Max , . 4/9 2011.07 - Rev.D BDJ1HFV Series Reference Data Technical Note 15 2.0 Ta= 30 °C 1.5 Ta= 30 °C 10 IDD [A] Vtemp [V] 1.0 PD="H" 5 0.5 PD="L" 0 0 1 2 3 4 5 6 7 VDD [V


Original
PDF BDJ0701HFV 11047EDT01 R1120A
54ls174

Abstract: No abstract text available
Text: +5.5 - 30 to +5 -0.5 to +Vcc 54LS 7.0 -0.5 to +7.0 - 30 to +1 -0.5 to +Vcc -65 to +150 54S 7.0 -0.5 , Waveform 3 25 30 35 35 54LSs CL = 15pF Min Max 30 30 30 35 54S CL = 15pF Min Max 75 13 17 22 MHz ns ns ns , Min 20 20 20 5 25 54 LS Max Min 7.0 10 5.0 3.0 5.0 54S Max ns ns ns ns ns UNIT AC ELECTRICAL , 25 44 51 51 Min 30 46 46 52 54 LS CL = 50pF Max Min 55 17 23 29 54S CL = 50pF Max MHz ns ns ns UNIT , Min 30 35 20 5 25 54 LS Max Min 10 10 7 5 7 54S Max ns ns ns ns ns UNIT Vec NOTES: 1. For


OCR Scan
PDF 54LS174, 54S174 16-Pin 54LSXXX 54XXX 54SXXX 500ns 500ns 1N916 54ls174
LS03210

Abstract: 54S02 54LS02 54LS
Text: , 54S02/BDA Ceramic LLCC 54LS02/B2C INPUT AND OUTPUT LOADING AND FAN-OUT TABLE pins description 54s 54ls A, B Inputs 1SUL 1LSUL Y Output 10SUL 10LSUL _!- Whlre a 54S Unit Load (SUL) is SO^A l,„ and , pin assignments, see Package Section. May 30 , 1986 This Material Copyrighted By Its Respective , PARAMETER 54LS 54S UNIT Vcc Supply voltage range 7.0 7.0 V V| Input voltage range -0.5 to +7.0 -0.5 to +5.5 V II Input current range - 30 to +1 - 30 to +5 mA Vo Voltage applied to output in HIGH output


OCR Scan
PDF 54LS02, 54S02 54LS02/BCA, 54S02/BCA 54LS02/BDA, 54S02/BDA 54LS02/B2C 10SUL 10LSUL WFH010S LS03210 54S02 54LS02 54LS
counter 54LS/74LS

Abstract: N74LS197F N74LS197N S54LS197F S54LS197W tm03 74S197
Text: 54/74197-See 8291 54S /74S197-See 82S91 54LS/74LS197 LOGIC SYMBOL 10 3 11 FEATURES • High , AND FAN-OUT TABLE(a) PINS DESCRIPTION 54/74 54S /74S 54LS/74LS CPo Clock (active LOW going edge , Manufacturer DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE(C) PARAMETER TEST CONDITIONS 54/74 54S /74S , CHARACTERISTICS: TA=25°C (See Section 4 for Test Circuits and Conditions) 54/74 54S /74S 54LS/74LS PARAMETER TEST CONDITIONS Cl = rl = 15pF 2kq UNIT Min Max Min Max Min Max cp0 30 MHz


OCR Scan
PDF 54/74197-See 54S/74S197-See 82S91 54LS/74LS197 modulo-16 54S/74S; 54LS/74LS. counter 54LS/74LS N74LS197F N74LS197N S54LS197F S54LS197W tm03 74S197
54S273

Abstract: IS1618
Text: otherwise noted.) 54 L S 7.0 -0.5 to +7.0 - 30 to +1 -0.5 to +VCc -65 to +150 54S 7.0 -0.5 to +5.5 - 30 to +5 , REQUIREMENTS TA = 25°C, V c c SYMBOL PARAM ETER = 5.0V 5 4LS M in Max Min 7.0 10 5.0 3.0 5.0 3.0 5.0 54S M , 4LS M ax Min 7.0 10 5.0 3.0 5.0 3.0 5.0 54S M ax ns ns ns ns ns ns UNIT *w(L) tw ts(H) th(H) ts(L , PINS All All Inputs Outputs DESCRIPTIO N 54S 1SUL 10SUL 54LS 1LSUL 10LSUL N O TE: A 54S Unit Load , -18 -400 4 +125 -55 54 LS Nom 5.0 M ax 5.5 Min 4.5 2.0 +0.8 +0.7 -18 -1000 20 +125 54S Nom 5.0 Max 5.5


OCR Scan
PDF 54LS273, 54S273 20-pin 54LSXXX 54SXXX 500ns 500ns 515ns 1N3064, 54S273 IS1618
2011 - Not Available

Abstract: No abstract text available
Text: Temperature Range Symbol VDD Topr Ratings Min. 2.4 - 30 Typ. 2.8 Max. 5.5 100 Unit V Electrical , " PD="L" PD=2.8V Ta = 30 Ta = - 30 to 100 difference of IOUT : 0uA / 2µA VDD=2.45.5V VOS =5.0V IOS = , 12.5 VDD = 2.8V Ta = - 30 to 100 Symbol Limits Min. Typ. Max. Unit Conditions Vtemp Temperature , . 4/9 2011.07 - Rev.B BDJ0HFV Series Reference Data Technical Note 15 2.0 Ta= 30 °C 1.5 Ta= 30 °C 10 IDD [A] Vtemp [V] 1.0 PD="H" 5 0.5 PD="L" 0 0 1 2 3 4 5 6 7 VDD [V


Original
PDF BDJ0650HFV 11047EBT05 R1120A
74LS152

Abstract: 74151A multiplexers 74151 PIN DIAGRAM 74151A 74ls151 pin diagram 74LS151 74152A pin diagram of 74153 pin diagram of 74157 TTL 74153
Text: X X 28 25 18 30 5.0 D160 4L,6B,9B 3 8-lnput 54S /74S151 X X 12 11 8.0 225 12.5 D160 4L,6B , Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S /74S157, 54LS/74LS157, 54S /74S158, 54LS/74LS158, 54S /74S257,54LS/74LS257, 54S /74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa , /74153, 54S /74S153, 54LS/74LS153, 54S /74S253, 54LS/74L8253 1 6 5 4 3 10 11 12 13 15 JM I I I I I I U , 13- S2 Z z TT Vcc = Pin 16 GND = Pin 8 □160 54/74151A, 548/74S151, 54LS/74LS151, 54S


OCR Scan
PDF 54LS/74LS170, 54LS/74LS670 93L09 54LS/74LS298 93L22, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257 74LS152 74151A multiplexers 74151 PIN DIAGRAM 74151A 74ls151 pin diagram 74LS151 74152A pin diagram of 74153 pin diagram of 74157 TTL 74153
MUX 74157

Abstract: 74157 mux 74153 mux mux 74153 74298 quad 2 in mux ttl 74157 TTL 74153 74153 8bit 74157 pin diagram pin diagram of 74153
Text: Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S /74S157, 54LS/74LS157, 54S /74S158, 54LS/74LS158, 54S /74S257,54LS/74LS257, 54S /74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa , /74153, 54S /74S153, 54LS/74LS153, 54S /74S253, 54LS/74L8253 1 6 5 4 3 10 11 12 13 15 JM I I I I I I U , 13- S2 Z z TT Vcc = Pin 16 GND = Pin 8 □160 54/74151A, 548/74S151, 54LS/74LS151, 54S , Parallel-in/Parallel-out 54/74174 6 — 6S _r 35 21 230 D152 4L,7B,9B 8 Parallel-in/Parallel-out 54S /74S174 6


OCR Scan
PDF 54LS/74LS170, 54LS/74LS670 93L09 54LS/74LS298 93L22, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257 MUX 74157 74157 mux 74153 mux mux 74153 74298 quad 2 in mux ttl 74157 TTL 74153 74153 8bit 74157 pin diagram pin diagram of 74153
74153 mux

Abstract: MUX 74157 74174 shift register 74157 mux CI 74151 mux 74153 74LS152 D flip-flop 74175 pin 74152 mux MUX 74151
Text: Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S /74S157, 54LS/74LS157, 54S /74S158, 54LS/74LS158, 54S /74S257,54LS/74LS257, 54S /74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa , /74153, 54S /74S153, 54LS/74LS153, 54S /74S253, 54LS/74L8253 1 6 5 4 3 10 11 12 13 15 JM I I I I I I U , 13- S2 Z z TT Vcc = Pin 16 GND = Pin 8 □160 54/74151A, 548/74S151, 54LS/74LS151, 54S , Mux X 30 17 300 D177 4L,7B,9B 11 Serial-in/Serial-out 93L28 16 2x2D Mux _ X 15 42 80 D177 4L,7B,9B


OCR Scan
PDF 54LS/74LS170, 54LS/74LS670 93L09 54LS/74LS298 93L22, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257 74153 mux MUX 74157 74174 shift register 74157 mux CI 74151 mux 74153 74LS152 D flip-flop 74175 pin 74152 mux MUX 74151
54LS74A

Abstract: Di801 max5539 54S74
Text: - 30 to +1 -0.5 to +Vcc -65 to +150 54S 7.0 -0.5 to +5.5 - 30 to +5 -0.5 to +Vcc -65 to +150 UNIT , Outputs DESCRIPTION 54S 1SUL 3SUL 2SUL 2SUL 10SUL 54 LS 1LSUL 2LSUL 2LSUL 1LSUL 10LSUL NOTE: Where a 54S Unit Load (SUL) is 50|iA l|H and -2.0mA l|L, and 54LS Unit Load (LSUL) is 20yA l|H and -0.4mA l|L , 2.0 +0.7 +0.7 -18 -400 4 +125 -55 54 LS Nom 5.0 Max 5.5 Min 4.5 2.0 +0.8 +0.7 -18 -1000 20 +125 54S , Short-circuit output current3 Supply current4 (total) Vcc = Max Vcc = Max -20 4 -100 8 -40 30


OCR Scan
PDF 54LS74A, 54S74 54LS7 54LSXXX 54SXXX 28Oil 500ns 500ns 54LS74A Di801 max5539 54S74
74S196

Abstract: 82s90 pin diagram decade counter 74196 BCD counter circuit diagram max plus S54LS196W S54LS196F N74LS196N N74LS196F counter 54LS/74LS 82s90 counter
Text: 54/74196 - See 8290 54S /74S196 - See 82S90 54LS/74LS196 LOGIC SYMBOL FEATURES • Performs , TABLE(a) PINS DESCRIPTION 54/74 54S /74S 54LS/74LS cpo Clock (active LOW going edge) input to -5- 2 , CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE(d) PARAMETER TEST CONDITIONS 54/74 54S /74S 54LS/74LS UNIT , Section 4 for Test Circuits and Conditions) 54/74 54S /74S 54LS/74LS PARAMETER TEST CONDITIONS cL = Rl = 15pF 2k!2 UNIT Min Max Min Max Min Max Maximum count frequency Figure 1 CP0 30


OCR Scan
PDF 54S/74S196 82S90 54LS/74LS196 54LS/74LS. 54S/74S: 54S/74S; 74S196 pin diagram decade counter 74196 BCD counter circuit diagram max plus S54LS196W S54LS196F N74LS196N N74LS196F counter 54LS/74LS 82s90 counter
s436

Abstract: No abstract text available
Text: D am ping O utput Resistor Reduces Transients SN 54S 436 . . J OR W PACKAGE SN 74S 436 . . . D OR N , n d S N 54S 436 . . . FK PACKAGE (TOP VIEW) < ^ U U N D Z >\(D LJLJLJLJLJ ' s 1Y 2A NC 2Y 3A , sh ow n are fo r D. J, N. ana W packages. PRODUCTION D A TA docum ents contain in fo rm atio n c u , operating conditions SN 54S 436 SN74S436 MAX 5 .5 2 TTL Devices MIN Vcc V |h V|_ S u p p lv , c = MA;< V Cc = M A X V c c - MAX v/CC * M S ' v Cc = M A X A ll o th e r m putb 54S


OCR Scan
PDF SN54S436, SN74S436 DS16149 DS16179 SN54S436 s436
54LS04/BCAJC

Abstract: 54LS04 54S04/BCA 54s04 54SCL Signetics 54LS04
Text: Vo t stg Over operating free-air temperature range unless otherwise noted 54 7.0 -0.5 to +5.5 - 30 to +5 -0.5 to +Vqq 5 4LS 7.0 -0.5 to +7.0 - 30 to +1 -0.5 to +Vqq -65 to +150 54S 7.0 -0.5 to +7.0 - 30 , TABLE PINS A Y Input Output D ESCRIPTIO N 54 1UL 10UL 54S 1SUL 10SUL 5 4LS 1LSU L 10LSUL N O TE: Where a 54 Unit Load (UL) is understood to be 40nA Iih and -1.6 m A l|L, a 54S Unit Load (SUL) is 50nA , 54S Norn 5.0 Max 5.5 UNIT Supply voltage High-level input voltage Low-level input voltage Input


OCR Scan
PDF 54LS04, 54S04 5404/BCA, 54LS04/BCA, 54S04/BCA 54LS04/BDA, 54S04/BDA 5404/BDA 54LS04/B2A, 54S04/B2A 54LS04/BCAJC 54LS04 54s04 54SCL Signetics 54LS04
2009 - ROHM marking

Abstract: No abstract text available
Text: - 30 TYP. 2.8 - MAX. 5.5 100 UNIT V ELECTRICAL CHARACTERISTICS ( unless otherwise , SYMBOL UNIT V CONDITIONS Ta = 30 Ta = - 30 to 100 difference of IOUT : 0A / 2A VDD , ±1.0 ±2.5 CONDITIONS 2/9 VDD = 2.8V Ta = - 30 to 100 2009.08 - Rev.A Technical , Ta= 30 °C Ta= 30 °C 1.5 Vtemp [V] IDD [A] 10 PD="H" 1.0 5 0.5 PD="L" 0 0.0 , VDD=2.8V 0 -2 Vtemp [mV] Vtemp[V] 1.5 1.0 -4 -6 -8 0.5 VDD=2.8V, Ta= 30


Original
PDF 09047EAT05 R0039A ROHM marking
2011 - Not Available

Abstract: No abstract text available
Text: Temperature Range Symbol VDD Topr Ratings Min. 2.4 - 30 Typ. 2.8 Max. 5.5 100 Unit V Electrical , " PD="L" PD=2.8V Ta = 30 Ta = - 30 to 100 difference of IOUT : 0uA / 2uA VDD=2.45.5V VOS =5.0V IOS = , ±1.0 ±2.5 VDD = 2.8V Ta = - 30 to 100 Tacc Thys 7.5 ±1.0 10.0 ±2.5 12.5 Symbol Limits Min. Typ. Max , . 4/9 2011.07 - Rev.D BDJ1HFV Series Reference Data Technical Note 15 2.0 Ta= 30 °C 1.5 Ta= 30 °C 10 IDD [A] Vtemp [V] 1.0 PD="H" 5 0.5 PD="L" 0 0 1 2 3 4 5 6 7 VDD [V


Original
PDF BDJ0901HFV 11047EDT01 R1120A
74ls74 pin configuration

Abstract: 7474 D flip-flop S5474F 74H74 7474 D flip flop 74ls74 N7474N S54S74F/883B N74H74N N74LS74F
Text: 54/7474 54H/74H74 54S /74S74 54LS/74LS74 LOGIC SYMBOL DESCRIPTION The "74" is a Dual Positive , (a) PINS 54/74 54H/74H 54S /74S 54LS/74LS D°ata Input i'i'^a! 40 -1.6 50 -2.0 50 -2.0 20 -0.36 CP , CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (b) PARAMETER TEST CONDITIONS 54/74 54H/74H 54S /74S 54LS/74LS UNIT Min Max Min Max Min Max Min Max Ice Supply current Vcc = Max VCp = 0V Mil 30 42 50 8.0 mA Com 30 50 50 8.0 mA NOTES a. The slashed numbers indicate different parametric values


OCR Scan
PDF 54H/74H74 54S/74S74 54LS/74LS74 54H/74H 54S/74S 54LS/74LS 74ls74 pin configuration 7474 D flip-flop S5474F 74H74 7474 D flip flop 74ls74 N7474N S54S74F/883B N74H74N N74LS74F
CI 7408

Abstract: logic diagram of 7432 7408 s.i TTL 7486 FL 9014 CI 74LS08 7408 7486 nor 7432 TTL 7408 fairchild
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S /74S08, 54LS/74LS08 54/7409, 54S /74S09, 54LS/74LS09 Vcc ) EI EI na fri EI iyi FI ¿J a lil liJ Li] Iii liJ 111 , lillkililliJliJlilliJliJ GND D20 54/7432, 54S /74S32 54LS/74LS32 ei ei ei m ei iti fi Elfi LlJ liJ LiJ LiJ Iii Iii Lü D18 54/7411, 54H/74H11, 54S /74S11, 54LS/74LS11, 54S /74S15, 54LS/74LS15 Vcc El El El [il El FI RI sras L i—=r\ Ii] Iii Ii] Iii Iii Ii] LI GND D21 54/7486, 54S /74S86, 54LS/74LS86, 54LS


OCR Scan
PDF 54H/74H08, 54S/74S08, 54LS/74LS08 54S/74S09, 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32 54H/74H11, CI 7408 logic diagram of 7432 7408 s.i TTL 7486 FL 9014 CI 74LS08 7408 7486 nor 7432 TTL 7408 fairchild
7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram 74LS112 74LS74 TTL 74107 7476 CI 7473 7473 pin diagram Jk 7476 74h106
Text: /74H106 4 — 0 —15 — Q 1-0 CP 6-0 CP 16— K _ CD Q 0-14 « 0 D62 54S /74S112, 54LS/74LS112 , 0-3 8_ K Cd 0 D63 54S /74S113, 54LS/74LS113 3 — 0 -5 11 a 1-0 CP 13-0 CP 2— K 0 0—6 12- K Q Vcc = Pin 14 GND = Pin 7 Vcc = Pin 14 GND = Pin 7 D64 54S /74S114, 54LS/74LS114 4 J , /74H71 (AOI) (2+2) J, (2+2) K X _ 30 22 95 D52a 3I, 6A, 9A 4 Single JK 54H/74H101 (AOI) (2+2)J, (2+2)K , JK 54H/74H72 3J, 3K X X 30 22 80 D53a 3I, 6A, 9A 7 Single JK 54H/74H102 3J, 3K T X X 50 16 100 D53b


OCR Scan
PDF 54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54H/74H73 54H/74H103 54S/74S113 7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 74LS74 TTL 74107 7476 CI 7473 7473 pin diagram Jk 7476 74h106
TTL 74ls74

Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
Text: Cd D60 9024, 54/74109, 54S /74S109, 54LS/74LS109 5 11 ~LT 2 — J SD 0 _6 14 0 4 — CP 12 CP 3-0 K Co Q »1 13 —0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S /74S74, 54LS/74LS74 4 10 J , X 50 16 115 D51 3I, 6A 3 Single JK 54H/74H71 (AOI) (2+2) J, (2+2) K X _ 30 22 95 D52a 3I, 6A, 9A , , 3K X X 20 25 50 D53a 3I, 6A, 9A 6 Single JK 54H/74H72 3J, 3K X X 30 22 80 D53a 3I, 6A, 9A 7


OCR Scan
PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 TTL 74ls74 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
54S00

Abstract: 54LS00 54LS00/BCBJC Ceramic diodes for short circuit in 5400 5400 nand
Text: +5.5 - 30 to +5 -0.5 to +Vcc 54LS 7.0 -0.5 to +7.0 - 30 to +1 -0.5 to +Vcc -65 to +150 54S 7.0 -0.5 to +7.0 - 30 to +5 -0.5 to +Vcc UNIT V V mA V °C RECOMMENDED OPERATING CONDITIONS SYMBOL , PINS A, B Y Inputs Output DESCRIPTION 54 1UL 10UL 54S 1SUL 10SUL 54 LS 1LSUL 10LSUL NOTE: Where a 54 Unit Load (UL) is understood to be 40^A liH and -1.6mA l|L, a 54S Unit Load (SUL) is 50|iA l!Hand , 5.0 Max 5.5 Min 4.5 2.0 +0.7 -18 -400 4 +125 -55 54S Norn 5.0 Max 5.5 UNIT V V +0.8 -18 -1000 20


OCR Scan
PDF 54LS00, 54S00 540Q/BCA, 54LS00/BCA, 54S00/BCA 54LS00/BDA, 54S00/BDA 5400/BDA 54LS00/B2A, 54S00/B2A 54S00 54LS00 54LS00/BCBJC Ceramic diodes for short circuit in 5400 5400 nand
Supplyframe Tracking Pixel