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EPM5130QC1 Altera Corporation ComS.I.T. 92 - -

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EPM5130

Abstract: LD128
Text: Altera Corporation Data S heet EPM5130 EPLD See Note (4) EPM5130-1 EPM5130-2 EPM5130 AC , internal Timing Parameters Symbol Parameter See Note (8) EPM5130-1 EPM5130-2 EPM5130 , factory Availability EPM 5130-1, EPM5130-2 , EPM5130 Page 166 Altera Corporation Data Sheet , EPM5130 EPLD Features u High-density 128-macrocell general-purpose M A X , plastic O T P J-lead packages General Description The EPM5130 E P L D (see Figure 21) is a


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PDF EPM5130 128-macrocell 32-bit 16-bit LD128
EPM5130

Abstract: EPM5130A-15 74N10
Text: EPM5130A-15 Min Max 3 3 8 8 5 C1 = 35 pF C1 = 35 pF C1 = 5 pF 2 1 1 1 7 6 0 1 3 3 10 3 5 5 EPM5130A-20 , Operating Conditions External Timing Parameters Symbol *PD1 tpD2 *SU Note (6) EPM5130-1 Conditions C1 = , ) Note (9) 50 62.5 40 50 40 25 33.3 40 25 14 11 25 33.3 30 14 10 10 6 8 30 16 14 30 EPM5130-2 Min Max , Parameters Symbol *IN ho lSEXP tLAD fLAC Note (10) Conditions EPM5130-1 Min Max 5 6 12 12 10 EPM5130-2 Min Max 7 6 14 14 12 5 11 11 8 EPM5130 Min Max Unit 11 11 20 14 13 6 13 13 12 ns ns ns ns


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PDF EPM5130 128-macrocell, 32-bit 16-bit 100-pin 84-pin EPM5130A-15 74N10
EPM5130

Abstract: No abstract text available
Text: Conditions See Note (4) External Timing Parameters Symbol EPM5130-1 Parameter Conditions EPM5130-2 Min Min C1 = 35 pF Max Max EPM5130 Min Max Unit tpD1 Input to , clock frequency S ee Note (7) 62.5 50 40 MHz Parameter EPM5130-1 Conditions EPM5130-2 Min Min Max Max MHz 30 ns EPM5130 Min Max Unit tlN Input , EPM5130 EPLD □ High-density 128-macrocell general-purpose MAX 5000 EPLD □ 128 macrocells


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PDF EPM5130 128-macrocell 32-bit 16-bit
EPM5130

Abstract: 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130
Text: f /0 t EXP 1LAD t LAC { OD tz x tx z Note (9) Conditions EPM5130-1 EPM5130-2 EPM5130 , Operating Conditions External Timing Parameters Symbol tp D 1 tp D 2 *SU Datasheet Note (5) EPM5130-1 EPM5130-2 EPM5130 Parameter Input to non-registered output I/O input to non-registered output Global , frequency for the EPM5130. Figure 24. EPM5130 Maxim um Output Drive Characteristics & l cc vs. Frequency , . Pin-Out Information Tables 5 and 6 provide pin-out information for the EPM5130. Table 5. EPM5130


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PDF EPM5130 128-macrocell, 32-bit 16-bit 100-pin 84-pin in100-Pin ALTED001 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130
EPM5130

Abstract: EPM5130A-20 KSD 101-G EPM5130A-15 100-Pin Package Pin-Out Diagram 4536C
Text: Information AC Operating Conditions Note (6) External Timing Parameters EPM5130A-15 EPM5130A-20 Symbol , Note (10) EPM5130A-15 EPM5130A-20 Symbol Parameter Conditions Min Max Min Max Unit Input pad and , Timing Parameters EPM5130-1 EPM5130-2 EPM5130 Symbol Parameter Conditions Min Max Min Max Min Max , internai Timing Parameters Note (10) EPM5130-1 EPM5130-2 EPM5130 Symbol Parameter Conditions Min Max , Timing) in this data book. Tables 6 and 7 provide pin-out information for the EPM5130. Table 6. EPM5130


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PDF EPM5130 128-macrocell, 32-bit 16-bit 100-pin 84-pin STS372 EPM5130A-20 KSD 101-G EPM5130A-15 100-Pin Package Pin-Out Diagram 4536C
EPM5130

Abstract: D1398
Text: Maximum clock frequency Note (9) 100.0 71.4 MHz EPM5130A-15 EPM5130A-20 Min Min , ) External Timing Parameters Symbol EPM5130-1 Parameter Conditions EPM5130-2 Min Min , ) 25 20 EPM5130-1 Note (10) Parameter Conditions EPM5130-2 Min Min Max , Operating Conditions Note (6) EPM5130A-15 External Timing Parameters Parameter Symbol Conditions Min Max EPM5130A-20 Min Max Unit •PD1 Input to non-registered output


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PDF 128-macrocell, 32-bit 16-bit 100-pin 84-pin STS372 D004247 EPM5130 D1398
EPM5130

Abstract: 5962-9314401MZC 5962-9324702MXC 5962-8946901YC 5962-8686401 5962-8854901xa EP1800I 5962-9314402MXA 5962-8946804 Altera EPM5128
Text: EP1800I EP1810 EP1810 EPM5032 EPM5032 EPM5064 EPM5128 EPM5128 EPM5128 EPM5128 EPM5128 EPM5130 EPM5130 EPM5130 EPM5130 EPM5130 EPM5192 EPM5192 EPM7192E EPM7192E EPM7256E EPM7256E EPM7256E EPM7256E EPF8820A


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PDF MIL-STD-883, MIL-STD-883 MIL-STD883-qualified, MIL-STD-883-compliant EPM5130 5962-9314401MZC 5962-9324702MXC 5962-8946901YC 5962-8686401 5962-8854901xa EP1800I 5962-9314402MXA 5962-8946804 Altera EPM5128
1995 - EPM5130

Abstract: EPM5192 EPM5064 EPM5032 EPM5128 EPM5064-1 EPM5032-15 ALTERA MAX 5000 EPM5064-2 ALTERA MAX 5000 programming
Text: , EPM5128, EPM5130 & EPM5192 AC Operating Conditions EPM5064-1 EPM5064-2 EPM5128-1 EPM5128-2 EPM5130-1 , -2 EPM5128-1 EPM5128-2 EPM5130-1 EPM5192-1 Note (6) Parameter Conditions EPM5064 EPM5128 , EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Usable gates 600 1,250 2,500 2,500 3 , ns v v 30 ns 35 ns v EPM5064 v v v EPM5128 v v v EPM5130 , EPM5130 JLCC PLCC PGA PQFP EPM5192 JLCC PLCC PGA EPM5032 EPM5064 EPM5128 44


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PDF 28-pin 100-pin 15-ns EPM5192 84-Pin EPM5130 EPM5192 EPM5064 EPM5032 EPM5128 EPM5064-1 EPM5032-15 ALTERA MAX 5000 EPM5064-2 ALTERA MAX 5000 programming
Altera EPM5128

Abstract: WKX 62 EPM5016 epm5130 pinouts for 7400 series EPM5128 PACKAGING EPM5064 EPM5192 program EPM5032 PLDS-MAX
Text: available. Figure 1 shows the MAX 5000 modular architecture. Figure 1. MAX 5000 Modular Architecture EPM5130 , ) and higher-density EPLDs (EPM5064, EPM5128, EPM5130 , and EPM5192). The higher-speed devices achieve , The EPM5016 and EPM5032 EPLDs have a single Logic Array Block (LAB). The EPM5064, EPM5128, EPM5130 , densities. Migration from one type of device to another is easy. For example, the EPM5128 and EPM5130 EPLDs , programmable tri-state buffers and I/O pins. In the EPM5064, EPM5128, EPM5130 , and EPM5192 EPLDs, multiple LABs


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PDF EPM5016 EPM5192 20-pin 100-pin 15-ns Altera EPM5128 WKX 62 epm5130 pinouts for 7400 series EPM5128 PACKAGING EPM5064 program EPM5032 PLDS-MAX
epm5064

Abstract: EPM5130 EPM5128 APPLICATION NOTE CERAMIC CHIP CARRIER LCC 68 socket EPM5130 adapter
Text: 128 8 256 PIA 60 25 4 14 50 EPM5130 2,500 128 8 256 PIA 84 25 4 14 50 EPM5192 3,750 192 12 384 , MHz (see Table 2). Table 2. MAX 5000 Device Speed Grades Device EPM5032 EPM5064 EPM5128 EPM5130 , EPM5128 EPM5130 EPM5192 28 PDIP 28 Pin Count PLCC 28 44 68 84 84 PGA PQFP 68 100 84 100 , , EPM5128, EPM5130 , and EPM5192 contain multiple LABs. Each LAB consists of a macrocell array and an , , EPM5130 , and EPM5192 devices, multiple LABs are connected by a PIA. All macrocells feed the PIA to provide


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PDF 28-pin 100-pin 15-ns 84-Pin EPM5192 epm5064 EPM5130 EPM5128 APPLICATION NOTE CERAMIC CHIP CARRIER LCC 68 socket EPM5130 adapter
1999 - EPM5130

Abstract: max 5000
Text: EPM5128 2,500 128 8 256 PIA 60 25 4 14 50 EPM5130 2,500 128 8 256 PIA 84 25 4 14 50 EPM5192 3,750 , EPM5128 EPM5130 EPM5192 Speed (tPD1) 20 ns v 25 ns v v v v v v v v v v v 30 ns 35 ns v The MAX 5000 , EPM5064 EPM5128 EPM5130 EPM5192 28 Pin Count PDIP 28 PLCC 28 44 68 84 84 PGA PQFP 68 100 , single LAB, while the EPM5064, EPM5128, EPM5130 , and EPM5192 contain multiple LABs. Each LAB consists of , groups of programmable tri-state buffers and I/O pins. In the EPM5064, EPM5128, EPM5130 , and EPM5192


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PDF 28-pin 100-pin 15-ns 84-Pin EPM5192 EPM5130 max 5000
1995 - EPM5130

Abstract: L9116 EPM5064 EPM5032-2 epm5130g EPM5192 EPM5032 EPM5128 EPM5064-1 EPM5032-15
Text: , EPM5128, EPM5130 & EPM5192 AC Operating Conditions EPM5064-1 EPM5064-2 EPM5128-1 EPM5128-2 EPM5130-1 , -2 EPM5128-1 EPM5128-2 EPM5130-1 EPM5192-1 Note (6) Parameter Conditions EPM5064 EPM5128 , EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Usable gates 600 1,250 2,500 2,500 3 , ns v v 30 ns 35 ns v EPM5064 v v v EPM5128 v v v EPM5130 , EPM5130 JLCC PLCC PGA PQFP EPM5192 JLCC PLCC PGA EPM5032 EPM5064 EPM5128 44


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PDF 28-pin 100-pin 15-ns EPM5192 84-Pin EPM5130 L9116 EPM5064 EPM5032-2 epm5130g EPM5192 EPM5032 EPM5128 EPM5064-1 EPM5032-15
PDN9917

Abstract: EPM5130 ALTERA MAX 5000 programming EPM5128 ALTERA MAX 5000 EPM5192 PLMJ5128A PLMG5128A PLMJ5192A PLMG5130A
Text: programming adapter EPM5130 (A) PGA programming adapter EPM5130 (A) J-lead programming adapter EPM5130 (A) QFP


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PDF PLMG5128A PLMJ5128A PLMG5130A PLMJ5130A PLMQ5130A PLMG5192A PLMJ5192A EPM5128 EPM5130 PDN9917 ALTERA MAX 5000 programming ALTERA MAX 5000 EPM5192 PLMJ5128A PLMG5128A PLMJ5192A PLMG5130A
EPM5130

Abstract: EPM5064 MC3334 44 pin plcc socket program EPM5032 EPMS128 EPM5064-1
Text: Parameters Note (1 ) EPM5064-2 EPM5128-2 EPM5064 EPM5128 EPM5130 EPM5192 EPM5064-1 EPM5128-1 EPM5130-1 , Note (6) EPM5064-1 EPM5128-1 EPM5130-1 EPM5192-1 EPM5064-2 EPM5128-2 EPM5064 EPM5128 EPM5130 , EPM5064 1,250 64 4 128 PIA 36 25 4 14 50 EPM5128 2,500 128 8 256 PIA 60 25 4 14 50 EPM5130 2,500 , . See Table 2, Table 2. MAX5000Device Speed Grades Device 15 ns EPM5032 EPM5064 EPM5128 EPM5130 , EPM5130 EPM5192 MAX 5000 EPLDs have between 32 and 192 macrocells that are combined into groups called


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PDF 28-pin 100-pin 15-ns EPM5192 84-Pin EPM5130 EPM5064 MC3334 44 pin plcc socket program EPM5032 EPMS128 EPM5064-1
EPM5130

Abstract: J-Lead, EPM5128 APPLICATION NOTE ALTERA MAX 5000 MAX5000 macrocell Altera EPM5128 EPM5064-1
Text: -2 EPM5128-2 EPM5064 EPM5128 EPM5130 EPM5192 EPM5064-1 EPM5128-1 EPM5130-1 EPM5192-1 Symbol *PD1 tpD2 , ) EPM5064-1 EPM5128-1 EPM5130-1 EPM5192-1 EPM5064-2 EPM5128-2 EPM5064 EPM5128 EPM5130 EPM5192 , PIA 60 25 4 14 50 EPM5130 2,500 128 8 256 PIA 84 25 4 14 50 EPM5192 3,750 192 12 384 PIA 72 25 , EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Speed (tPD1) 20 ns 25 ns s/ v ' v ' v/ v/ 30 ns 35 ns y , Device 28 EPM5032 CerDIP PDIP PLCC EPM5064 EPM5128 EPM5130 EPM5192 PLCC PLCC PGA PLCC PLCC PGA PGA PQFP


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PDF 5000architecture 28-pin 100-pin 15-ns 84-Pin EPM5192 EPM5130 J-Lead, EPM5128 APPLICATION NOTE ALTERA MAX 5000 MAX5000 macrocell Altera EPM5128 EPM5064-1
1995 - EPM5128GM

Abstract: EPM5128GC EPM5128JC EPM5032DC EPM5128GC-1 EPM5130QC-2 epm5130qc EPM5130LC EPM5032DC-20 EPM5032DC-15
Text: EPM5130JC-1 ADV 9609 EPM5130GM883B 1/31/96 (5962-9314401MZX) EPM5130GM883B-2 1/31/96 (5962-9314402MZX) EPM5130GM EPM5130JC-2 EPM5130JI-2 EPM5130JI EPM5130JM EPM5130LC-2 EPM5130LI-2 EPM5130LI EPM5130QC-2 EPM5130QI EPM5130WC-1 EPM5130WC-2 EPM5130WC 1/31/96 9/30/96 9/30/96 9/30/96 1/31/96 9/30/96 9/30/96 9/30/96 , part numbers found Obsolete Part Numbers Part Number Format Part Number EPM5130GC-2 EPM5130GI Buying , 12/31/96 12/31/96 12/31/96 12/31/96 12/31/96 EPM5130GC-1 Notes ADV 9609 No direct replacement PDN


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PDF 28-pin 100-pin 15-ns EPM5032PC-17 EPM5032SC-15 EPM5032SC-17 EPM5032SC-20 EPM5032SC-25 EPM5032SC-15, EPM5128GM EPM5128GC EPM5128JC EPM5032DC EPM5128GC-1 EPM5130QC-2 epm5130qc EPM5130LC EPM5032DC-20 EPM5032DC-15
EPM5130

Abstract: EPM5016
Text: EPM5130 EPM5128 EPM5064 EPM5Q32 EPM5016 Macrocells Maximum Flip-Flops Maximum Latches Pins , ) and higher-density EPLDs (EPM5064, EPM5128, EPM5130 , and EPM5192). The higher-speed devices achieve , , EPM5130 , and EPM5192 EPLDs contain multiple LABs. Each LAB contains a macrocell array, an expander , from one type of device to another is easy. For example, the EPM5128 and EPM5130 EPLDs have the same , programmable tri-state buffers and I/O pins. In the EPM5064, EPM5128, EPM5130 , and EPM5192 EPLDs, multiple


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PDF 20-pin 100-pin 15-ns EPM5130 EPM5016
EPM5130

Abstract: No abstract text available
Text: Modular Architecture EPM5192 EPM5130 EPM5128 EPM5064 EPM5032 EPM5016 Macrocells Maximum , (EPM5016 and EPM5032) and higher-density EPLDs (EPM5064, EPM5128, EPM5130 , and EPM5192). The higher-speed , , EPM5128, EPM5130 , and EPM5192 EPLDs contain multiple LABs. Each LAB contains a macrocell array, an , easy. For example, the EPM5128 and EPM5130 EPLDs have the same logic capacity, but have packages , , EPM5128, EPM5130 , and EPM5192 EPLDs, multiple LABs are connected by a Programmable Interconnect Array


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PDF EPM5016 EPM5192 20-pin 100-pin 15-ns EPM5130
EPM5130

Abstract: No abstract text available
Text: -1 EPM5128-1 EPM5130-1 EPM5192-1 External Timing Parameters Parameter Symbol Note (1 , Sheet Internal Timing Parameters EPM5064-1 EPM5128-1 EPM5130-1 EPM5192-1 N o ie (6 , /6000 workstations Table 1. MAX 5000 Device Features EPM5032 EPM5064 EPM5128 EPM5130 , ✓ EPM5064 ✓ ✓ ✓ EPM5128 ✓ ✓ ✓ EPM5130 ✓ â , CerDIP PDIP PLCC EPM5064 EPM5128 PLCC PLCC PGA EPM5130 PLCC EPM5192 PGA PLCC


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PDF 28-pin 100-pin 15-ns EPM5130
EPM5130

Abstract: program EPM5032
Text: 128 8 256 PIA 60 25 4 14 50 EPM5130 2,500 128 8 256 PIA 84 25 4 14 50 EPM5192 3,750 192 12 384 , 5000 Device Speed Grades Device 15 ns EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Speed (tPD1) 20 ns , EPM5130 EPM5192 28 Pin Count PDIP 28 PLCC 28 44 68 84 84 PGA PQFP 68 100 84 100 M A X , Sheet Table 8. EPM5064, EPM5128, EPM5130 & EPM5192 MAX 5000 Device Capacitance Symbol C IN C I/O , 725 MAX 5000 Programmable Logic Device Family Data Sheet Table 11. EPM5064, EPM5128, EPM5130 &


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PDF 28-pin 100-pin 15-ns 84-Pin EPM5192 EPM5130 program EPM5032
L9132

Abstract: EPM5130 altera 5032 EPLD 5128 EPM5192
Text: Table 1. MAX 5000 De vi ce Features Feature EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Usable gates , ns 20 ns 25 ns 30 ns 35 ns EPM5032 ✓ EPM5064 y EPM5128 v/ EPM5130 y EPM5192 s , PDIP PLCC PGA PQFP EPM5032 28 28 28 EPM5064 44 EPM5128 68 68 EPM5130 84 100 100 EPM5192 84 , contain 1 to 12 LABs. The EPM5032 has a single LAB, while the EPM5064, EPM5128, EPM5130 , and EPM5192 , buffers and I/O pins. In the EPM5064, EPM5128, EPM5130 , and EPM5192 devices, multiple LABs are connected


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PDF 28-pin 100-pin 15-ns pack24 EPM51921/0 84-Pin L9132 EPM5130 altera 5032 EPLD 5128 EPM5192
adv9606

Abstract: EPM5130 EPM5064 ALTERA MAX 5000 EPM5032 max EPM5192 micron EPM5032 EPM5128
Text: shipments. In addition, Altera will transition the EPM5032, EPM5064, and EPM5130 devices to the 0.65-micron process as per the following schedule: Device EPM5032 EPM5064 EPM5130 Planned Transition Date


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PDF 65-micron EPM5128 EPM5192, EPM5192 EPM5032, EPM5064, adv9606 EPM5130 EPM5064 ALTERA MAX 5000 EPM5032 max micron EPM5032
1995 - Not Available

Abstract: No abstract text available
Text: -1 EPM5064-2 EPM5128-1 EPM5128-2 EPM5130-1 EPM5192-1 Symbol t PD1 t PD2 t SU tH t CO1 t CH t CL t ASU t , Family Data Sheet EPM5064-1 EPM5064-2 EPM5128-1 EPM5128-2 EPM5130-1 EPM5192-1 EPM5064 EPM5128 EPM5130 , EPM5064 1,250 64 4 128 PIA 36 25 4 14 50 EPM5128 2,500 128 8 256 PIA 60 25 4 14 50 EPM5130 2,500 , Device 15 ns EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Speed (tPD1) 20 ns v 25 ns v v v v v v v v v v v , EPM5064 EPM5128 EPM5130 EPM5192 MAX 5000 EPLDs have between 32 and 192 macrocells that are combined


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PDF 28-pin 100-pin 15-ns EPM5192 84-Pin
Not Available

Abstract: No abstract text available
Text: (1) EPM5064-1 EPM5128-1 EPM5130-1 EPM5192-1 Conditions Parameter EPM5064-2 EPM5128 , Internal Timing Parameters Symbol EPM5064-1 EPM5128-1 EPM5130-1 EPM5192-1 Note (6) Parameter , Device Features Feature EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Usable gates 600 , ✓ ✓ ✓ EPM5128 v/ ✓ ✓ EPM5130 n/ ✓ EPM5192 ✓ â , EPM5128 JLCC PLCC PGA EPM5130 PLCC EPM5192 JLCC PLCC PGA Note: (1) Contact Altera


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PDF 28-pin 100-pin 15-ns 84-Pin 000500b
EPM5130

Abstract: No abstract text available
Text: MPM5130 MPLD □ Features □ □ □ □ □ □ □ General Description CMOS, M ask-Program m ed Logic Device (MPLD) capable of implementing high-density custom logic functions High-volume replacement for EPM5130 EPLD designs Zero-power operation (typically 25 |iA standby , ) packages Altera's MPM5130 MPLD provides a high-volume replacement for EPM5130 designs. It is pin , ltera's MAX+PLUS or MAX+PLUS II development system and prototyped with EPM5130 EPLDs. The source files


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PDF MPM5130 EPM5130 100-pin
Supplyframe Tracking Pixel