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EP610ILC-10 Altera Corporation Bristol Electronics - -
EP610ILC10 Altera Corporation ComS.I.T. - -
EP610ILI-12 Altera Corporation Bristol Electronics - -
EP610ILI12 Altera Corporation ComS.I.T. - -
EP610IPC-25 Altera Corporation America II Electronics - -
EP610IPC10 Altera Corporation ComS.I.T. - -
EP610IPC15 Altera Corporation ComS.I.T. - -

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EP610I datasheet (20)

Part Manufacturer Description Type PDF
EP610I-10 Altera High-performance, 16-macrocell Classic EPLD Original PDF
EP610I-10 Altera Classic EPLD Family Scan PDF
EP610I-10CERDIP24 Altera SPLD Original PDF
EP610I-10PDIP24 Altera SPLD Original PDF
EP610I-12PDIP24 Altera SPLD Original PDF
EP610I-12PLCC28 Altera SPLD Original PDF
EP610I-15 Altera High-performance, 16-macrocell Classic EPLD Original PDF
EP610I-15CERDIP24 Altera SPLD Original PDF
EP610I-15PLCC28 Altera SPLD Original PDF
EP610IDC-10 Altera CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 10 Speed Grade, 24DIP Original PDF
EP610IDC-10N Altera IC CPLD 16MACROCELL 300GATE 10NS LE 5V 24CDIP Scan PDF
EP610IDC-15 Altera CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP Original PDF
EP610IDC-15N Altera IC CPLD 16MACROCELL 300GATE 15NS LE 5V 24CDIP Scan PDF
EP610ILC-10 Altera CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 10 Speed Grade, 28LDCC Original PDF
EP610ILI-12 Altera CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 12 Speed Grade, 28LDCC Original PDF
EP610ILI-12N Altera IC CPLD 16MACROCELL 300GATE 12NS LE 5V 28PLCC Scan PDF
EP610IPC-10 Altera CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 10 Speed Grade, 24DIP Original PDF
EP610IPC-10N Altera IC CPLD 16MACROCELL 300GATE 10NS LE 5V 24 pin PDIP Scan PDF
EP610IPC-15 Altera CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP Original PDF
EP610IPC-15N Altera IC CPLD MACROCELL GATE NS LE V 24 pin PDIP Scan PDF

EP610I Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1995 - application of ic 7483

Abstract:
Text: Devices The architecture of the EP610, EP610I , EP910, EP910I, and EP1810 devices provides registered and , , EP610I , EP910, EP910I & EP1810 Device Timing Model If the register is bypassed, the delay between the , ) Combinatorial Delay Combinatorial Logic t PD1 MAX 5000 (multi-LAB) EP610, EP610I , EP910, EP910I , t IN + t LAC + ( t XZ or t ZX ) EP610, EP610I , EP910, EP910I, EP1810 t PXZ , t PZX = t , t PRE , t CLR = t IN + t LAC + ( t PRE or t CLR ) + t OD EP610, EP610I , EP910, EP910I


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PDF 7000E 7000S application of ic 7483 ic 7483 full adder ic 7483 7483 IC 4 bit full adder EPM5128 EPM5064 EPM5032 EP610I EP610 7483 IC APPLICATIONS
EP610

Abstract:
Text: Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins EP610 and EP610I devices that , Voltage (V) V0 O utput Voltage (V) EP610I EPLDs V0 O utput Voltage (V) Altera Corporation , , and capacitance for EP610 and EP610I devices. Notes (1), (2) EP610 EP610I EP610 & EP610I Device , , under bias Plastic packages, under bias Tj EP610 & EP610I Device Recommended Operating Conditions Note (2) EP610 EP610I Sym bol v cc V| Param eter Supply voltage Input voltage Output voltage


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PDF EP610 16-macrocell EP610I 24-pin 28-pin EP610 16-bit EP610-15 EP610-20 EP610-25 EP610-30 EP610-35 EP6101-10
EP61Q-15

Abstract:
Text: -12 EP610I-15 Min Max Min Max Min Max W l tpD2 tpzx pxz tcLR *MAX *SU EP6101-10 Min f/N EP610I-12 Min Max 4.0 0.0 6.0 2.0 5.0 5.0 5.0 4.0 EP610I-15 Min Max 4.0 0.0 9.0 2.0 6.0 6.0 5.0 7.0 Unit Max 1.5 0.0 5.5 , MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins EP610 and EP610I , . C 5 z U o 24-Pin SOIC EP610 24-Pin DIP EP610 EP610I 28-Pin PLCC EP610 EP610I Altera


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PDF EP610 16-macrocell EP610I 24-pin 28-pin 16-bit EP61Q-15 EP61B EP6101-10 EP610-35 EP610-30 EP610-25 EP610-20 EP610-15
fxz 556

Abstract:
Text: Parameters Notes (1), (2) Symbol Parameter Conditions EP6101-10 EP610I-12 EP6101 , Internal Timing Parameters Symbol Parameter Conditions EP6101-10 Min Max 1.5 0.0 5.5 EP610I-12 Min Max 4.0 0.0 6.0 2.0 5.0 5.0 5.0 4.0 EP610I-15 Min Max 4.0 0.0 9.0 2.0 6.0 6.0 5.0 7.0 Unit , Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins EP610 and EP610I devices are , d? C 24-Pin SOIC EP610 24-Pin DIP EP610 EP610I < O o IN P U T I/O I/O I/O I/O I/O


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PDF 16-macrocell EP610 EP610I 24-pin 28-pin 16-bit fxz 556 EP6101-10 EP610-Z5 EP610-35 EP610-30 EP610-25 EP610-20 EP610-15
Not Available

Abstract:
Text: Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins EP610, EP610I , and EP600I , . 5 o o -I o o o > > 24-Pin SOIC 24-Pin DIP 28-Pin PLCC EP610 EP610 EP610I EP610 EP610I Altera Corporation 359 05^5372 000S017 OTS Classic EPLD Family Data Sheet , -35 EPLDs V 0 Output Voltage (V) V 0 Output Voltage (V) EP610I EPLDs V0 Output Voltage (V , EP610 & EP610I Device Absolute Maximum Ratings Notes (1), (2) EP610 Parameter Conditions


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PDF EP610 16-macrocell EP610, EP610I, EP600I 24-pin 16-bit
ep610

Abstract:
Text: Notes (1), (2) EP610I-10 Non-Turbo Adder N ote (3) Symbol *PD1 tpD2 Parameter Input to , Data Sheet Internal Timing Parameters EP610I-10 Symbol hN ho (LAD Parameter Input pad , Program m able I / O arch itectu re w ith up to 20 inputs o r 16 ou tp uts and 2 clock pins E P610, EP610I , in D IP EP610 EP610I 2 8 -P in P L C C EP610 EP610I Altera Corporation 359 Classic EPLD , . 3 o V 0 O u tp u t V o ltag e (V ) V 0 O u tp u t V o lta g e (V ) EP610I EPLDs V 0 O


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PDF EP610EPLD EP610I, EP600I 24-pin 24-pine 16-bit ep610 EP610-15 EP610-20 EP610-25 EP610-30 EP610-35 EP610I P6101
EP610

Abstract:
Text: AC Operating Conditions: EP610I Notes (1), (2) EP610I-10 EP610I-15 EP610I-25 Non-Turbo Adder , -, function-, and programming file-compatible: EP610, EP610I , EP610T, EP610 MIL-STD-883-compliant, EP600I, and , /o □ i/o i/o i/o i/o input □ clk2 24-Pin DIP EP610 EP610T EP610 MIL-STD-883-Compliant EP610I / i , EP610I Altera Corporation 345 □ 5=13372 D004S71 T2b EP610 EPLD Table 2 summarizes EP610 device features. Table 2. EP610 Device Features Feature EP610 EP610T EP610 MIL-STD-883-Compliant EP610I tpD 15 ns 15


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PDF EP610 16-macrocell EP610, EP610I, EP610T, MIL-STD-883-compliant, EP600I, PALCE610 24-pin MIL-STD-883-compliant EP610-15 TI EP610 altera ep610 ALTERA MAX 5000 programming EP610-20 EP610I
EP610

Abstract:
Text: Conditions: EP610I Notes ( 1), (2) EP610I-10 EP610I-15 EP610I-25 Non-Turbo Adder Symbol ·PD1 tpD 2 *PZX , are pin-, function-, and program m ing filecompatible: EP610, EP610I , EP610T, EP610 M IL-STD , 24-Pin SOIC EP610 EP610T 24-Pin DIP EP610 EP610T EP610 MIL-STD-883-Compliant EP610I 28-Pin J-Lead EP610 EP610T EP610I Altera Corporation 345 EP610 EPLD Table 2 sum m arizes EP610 device , -pin CerDIP EP610I 10 ns 100 MHz 100 MHz 24-pin CerDIP 24-pin PDIP 28-pin PLCC General _ . . U e S C r


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PDF EP610 16-macrocell EP610, EP610I, EP610T, IL-STD-883-com EP600I, PALCE610 24-pin ep600i EP610-15 EP610-20 EP610-25 EP610-30 EP610-35 EP610I
altera ep910i

Abstract:
Text: Classic, MAX 5000 & MAX 7000Timing Table 2. EP610I Internal Timing Parameters (ns) Parameter {IN ho {LAD f OD EP610I-10 1.5 0.0 5.5 3.0 8.0 6.0 3.5 3.5 7.5 2.0 1.0 8.5 EP610I-15 2.0 0.0 9.0 4.0 , , EP610I , EP910, EP910I, and EP1810 Classic devices provides registered and com binatorial capabilities , : Understanding Classic, MAX 5000 & MAX 7000 Timing Figure 1. EP610, EP610I , EP910, EP910I & EP1810 Device Timing , u ffe r is zero. Tables 1 through 5 show the internal delay param eters for EP610, EP610I , EP910


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PDF
1995 - EP910PC-30

Abstract:
Text: Notes (1), (2) Non-Turbo Unit Adder Conditions EP610I-10 EP610I-12 EP610I-15 Min Max Min Max Min Max , Table 13. EP610 Internal Timing Parameters Symbol Parameter Conditions EP610I-10 Min tIN tIO tLAD tOD , = 35 pF C1 = 35 pF C1 = 5 pF 3.5 3.5 7.5 2.0 1.0 8.5 EP610I-12 Min Max 4.0 0.0 6.0 2.0 5.0 5.0 5.0 4.0 8.0 2.0 1.0 9.0 EP610I-15 Min Max 4.0 0.0 9.0 2.0 6.0 6.0 5.0 7.0 10.0 2.0 1.0 12.0 , Feature Usable gates Macrocells Maximum user I/O pins t PD (ns) f CNT (MHz) EP610 EP610I 300 16 22 10


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PDF EP610LC-15 EP610LC-25 EP610ILI-12 EP610PC-15 EP610PI-30 EP910PC-30 EP910dm EP910DC-40 EP1810LC-35 EP1810LC-20 EP610DI-30 EP610PC-15 Programming EP610SC-15 EP910JI-35 EP910LC-30
1995 - Altera EP1810

Abstract:
Text: Parameters Symbol Parameter EP610I-10 Conditions Min Max Non-Turbo Adder Note (3 , 0 MHz 369 Classic EPLD Family Data Sheet Internal Timing Parameters Symbol EP610I-10 , EP610I EP910 & EP910I EP1810 Usable gates 300 450 900 Macrocells 16 24 48 , Configurations Global Feedback Multiplexer Q Global I/O EP610 EP610I EP910 EP910I Altera , , EP610I , EP910, and EP910I devices have a global feedback configuration; either the macrocell output (Q


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PDF
1995 - 7483 IC APPLICATIONS

Abstract:
Text: tSU tH Classic Devices The architecture of the EP610, EP610I , EP910, EP910I, and EP1810 devices , Classic devices. Figure 4. EP610, EP610I , EP910, EP910I & EP1810 Device Timing Model If the register , Delay Combinatorial Logic MAX 7000 MAX 5000 (single-LAB) MAX 5000 (multi-LAB) EP610, EP610I , EP910 , , EP610I , EP910, EP910I, EP1810 Global Control t PXZ , t PZX t PXZ , t PZX = = t IN + t LAC + ( t , Logic MAX 7000 MAX 5000 EP610, EP610I , EP910, EP910I, EP1810 t PRE , t CLR t PRE , t CLR t CLR


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PDF 7000E 7000S 7483 IC APPLICATIONS 7483 full adder 7483 IC 4 bit full adder EP610I
altera ep610

Abstract:
Text: -10 Sym bol tpD1 tp D 2 EP610I-15 M in M ax 15 15 18 18 18 83.3 12 0 6 6 EP610I-25 M in M ax 25 , -, function-, and programming filecompatible: EP610, EP610I , EP610T, EP610 MIL-STD-883-compliant, EP600I, and , -883-Compliant EP610I 28-Pin J-Lead EP610 EP610T EP610I Altera Corporation 345 I 05=15372 0 D04E71 T2b , Voltage (V) EP610-15T & EP610-20T EPLDs EP610I EPLDs V0 Output Voltage (V) V0 Output Voltage , temperature Junction temperature No bias Under bias, Note (3) Under bias, Note (3) -6 5 -6 5 EP610I


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PDF 16-macrocell EP610, EP610I, EP610T, EP610 MIL-STD-883-compliant, EP600I, PALCE610 24-pin 16-bit altera ep610 537e AX2022 EP610-15 EP6101-10 EP610I
1995 - ep910 programmer

Abstract:
Text: Parameters Symbol Parameter Notes (1), (2) Conditions EP610I-10 EP610I-12 EP610I-15 Min Max Min , Data Sheet Table 13. EP610 Internal Timing Parameters Symbol Parameter Conditions EP610I-10 EP610I-12 EP610I-15 Min Min Min Max Max Unit Max tIN Input pad and buffer , -05 EP910 EP910I Usable gates Altera Corporation EP610 EP610I 100 76.9 50 745 , Feedback Multiplexer Q Global I/O EP610 EP610I EP910 EP910I Altera Corporation Quadrant


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PDF
ic 7483 block diagram

Abstract:
Text: term. Figure 4 shows the timing model for these Classic devices. Figure 4. EP610, EP610I , EP910 , ) tp D 1 tp D 2 MAX 5000 (multi-LAB) EP610, EP610I , EP910, EP910I, EP1810 T ri-S ta te En a ble/D isa ble D elay tp D 1 tp D 2 *PD1 *PD2 - Combinatorial Logic MAX 5000 EP610, EP610I , Timing Parameters (Part 2 of 4) Re g is te r C lear & Preset Tim e MAX 7000 MAX 5000 EP610, EP610I , MAX 7000 MAX 5000 EP610, EP610I , EP910, EP910I, EP1810 Ho ld Tim e Combinatorial Logic 'S U =


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PDF 7000E 7000S 500nd ic 7483 block diagram pin diagram for IC 7483 xor INTERNAL DIAGRAM OF IC 7483 pin diagram for IC 7483 7483 parallel adder pin diagram application of ic 7483 ic 7483 pin diagram pin diagram of ic 7483
EP610

Abstract:
Text: EP610 Device AC Operating Conditions Notes (1), (2) External Timing Parameters EP610I-10 Non-Turbo , Features Feature EP610 EP910 EP1810 EP610I EP910I Usable gates 300 450 900 Macrocells 16 24 48 , Feedback Multiplexer EP610 EP610I EP910 EP910I Quadrant Feedback Multiplexer EP1810 EP1810T Dual , , EP610I , EP910, and EP910I devices have a global feedback configuration; either the macrocell output (Q , architecture with up to 20 inputs or 16 outputs and 2 clock pins EP610 and EP610I devices that are pin


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PDF EP1810 68-pin EP610 ep910 programmer TI EP610 ALTERA MAX 5000 programming EP610-25 EP6101-10 EP910
1999 - ep910 programmer

Abstract:
Text: Parameters Symbol Parameter Notes (1), (2) Conditions EP610I-10 EP610I-12 EP610I-15 Min Max Min , Data Sheet Table 13. EP610 Internal Timing Parameters Symbol Parameter Conditions EP610I-10 EP610I-12 EP610I-15 Min Min Min Max Max Unit Max tIN Input pad and buffer , -05 EP910 EP910I Usable gates Altera Corporation EP610 EP610I 100 76.9 50 745 , Feedback Multiplexer Q Global I/O EP610 EP610I EP910 EP910I Altera Corporation Quadrant


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PDF
1995 - Not Available

Abstract:
Text: ) EP610I-10 Non-Turbo Adder Parameter Input to non-registered output I/O input to non-registered output , tCLR EP610I-10 Parameter Input pad and buffer delay I/O input pad and buffer delay Logic array , ) EP610 EP610I 300 16 22 10 100 EP910 EP910I 450 24 38 12 76.9 EP1810 900 48 64 20 50 Altera , EP610 EP610I EP910 EP910I Q I/O Quadrant Feedback Multiplexer Quadrant EP1810 EP1810T Q I/O Dual , Family Data Sheet EP610, EP610I , EP910, and EP910I devices have a global feedback configuration


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EP1810

Abstract:
Text: EP610 Device AC Operating Conditions Notes (1), (2) External Timing Parameters EP610I-10 Non-Turbo , Multiplexer Configurations Global Feedback Multiplexer EP610 EP610I EP910 EP910I Quadrant Feedback , Family Data Sheet EP610, EP610I , EP910, and EP910I devices have a global feedback configuration; either , Programmable 1/O architecture with up to 20 inputs or 16 outputs and 2 clock pins EP610 and EP610I devices , -Pin DIP EP610 EP610I pr ^ O O pr ? 1 d ^ 1 ? n_□_□_□_□_□_□_ 4 3 2 1 28 27 26 25 24


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PDF of300 EP1810 68-pin EP610 EP610-25 EP6101-10 EP910 ep910 programmer programmer EPLD QLCC 24
1995 - ep600i

Abstract:
Text: tACH tACL tODH tACO1 tACNT fACNT Notes (1), (2) EP610I-10 Non-Turbo Adder Parameter Input to , Internal Timing Parameters Symbol tIN tIO tLAD tOD tZX tXZ tSU tH tIC tICS tFD tCLR EP610I-10 , (ns) f CNT (MHz) EP610 & EP610I 300 16 22 10 100 EP910 & EP910I 450 24 38 12 76.9 EP1810 , . Feedback Multiplexer Configurations Global Feedback Multiplexer Global EP610 EP610I EP910 EP910I Q I/O , EP1810 EP1810T Q I/O Altera Corporation 353 Classic EPLD Family Data Sheet EP610, EP610I


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PDF
1995 - ic 7483 full adder

Abstract:
Text: otherwise indicated. Classic devices include the EP610, EP610I , EP910, EP910I , and EP1810 devices only. t , Classic devices. Classic devices include the EP610, EP610I , EP910, EP910I , and EP1810 devices only. t PD1 , device family, which includes the EP610, EP610I , EP910, EP910I , and EP1810 devices, provides registered , Classic device families. Classic devices include the EP610, EP610I , EP910, EP910I , and EP1810 devices


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EP6101-10

Abstract:
Text: Parameters Symbol l!N ho fLAD tOO *ZX txz >su EP610I-10 Parameter Input pad and buffer delay I/O , , Synopsys, Synplicity, and VeriBest Table 1. Classic Device Features Feature EP610 EP610I 300 16 22 10 100 , Quadrant Feedback Multiplexer Dual Feedback Multiplexer EP610 EP610I EP910 EP910I EP1810 EP1810T EP1810 EP1810T Altera Corporation 423 Classic EPLD Family Data Sheet EP610, EP610I , EP910, a , and EP610I devices that are pin-, function-, and program m ing file-compatible Programm able clock


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PDF
1995 - ic 7483 full adder

Abstract:
Text: applies to both device families unless otherwise indicated. Classic devices include the EP610, EP610I , , EP610I , EP910, EP910I , and EP1810 devices only. t PD1 t PD2 I/O pin input to non-registered , Classic device family, which includes the EP610, EP610I , EP910, EP910I , and EP1810 devices, provides , , EP610I , EP910, EP910I , and EP1810 devices only. To calculate the delay for a signal that follows a


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altera ep910i

Abstract:
Text: gates Macrocells Maximum user I/O pins tpo (ns) f CNT (MHz) EP610 EP610I 300 16 22 10 100 EP910 EP910I , Feedback Multiplexer Quadrant ^ Global < Q I/O EP 1810 I/O EP610 EP610I EP910 EP910I Altera Corporation 749 Classic EPLD Family Data Sheet EP610, EP610I , EP910, and EP910I devices have a


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7483 adder/subtractor

Abstract:
Text: otherwise indicated. Classic devices include the EP610, EP610I , EP910, EP910I, and EP1810 devices only. fflv , Classic devices. Classic devices include the EP610, EP610I , EP910, EP910I, and EP1810 devices only. tpDi , includes the EP610, EP610I , EP910, EP910I, and EP1810 devices, provides registered and combinatorial , Classic device families. Classic devices include the EP610, EP610I , EP910, EP910I, and EP1810 devices only


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