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LT1017MJ8/883 Linear Technology LT1017 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LM108AJ8 Linear Technology LM108A - Operational Amplifiers; Package: CERDIP; Pins: 8; Temperature: Military
LT1175CDWF#MILDWF Linear Technology LT1175 - 500mA Negative Low Dropout Micropower Regulator; Pins: 5
LT1018MJ8/883 Linear Technology LT1018 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LTC1041MJ8/883 Linear Technology LTC1041 - BANG-BANG Controller; Package: CERDIP; Pins: 8; Temperature: Military
LTC2905HDDB#TRMPBF Linear Technology LTC2905 - Precision Dual Supply Monitor with Pin-Selectable Thresholds; Package: DFN; Pins: 8; Temperature Range: -40°C to 125°C

EP3C25 pin diagram Datasheets Context Search

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2013 - EP3C25 pin diagram

Abstract: EP3C25 pin guideline
Text: Pin Information for the Cyclone® III EP3C25 Device Version 1.5 Notes (2), (3) Bank Number , 11 Pin Information for the Cyclone® III EP3C25 Device Version 1.5 Notes (2), (3) Bank Number , ® III EP3C25 Device Version 1.5 Notes (2), (3) Bank Number VREFB Group Pin Name / Function , /CQ1R#, DPCLK6 DQ1R DQ1R Page 4 of 11 Pin Information for the Cyclone® III EP3C25 Device , Cyclone® III EP3C25 Device Version 1.5 Notes (2), (3) Bank Number VREFB Group Pin Name


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PDF EP3C25 EP3C25 pin diagram EP3C25 pin guideline
2007 - EP3C25

Abstract: EP3C25 pin diagram F324 altera cyclone III EP3c25 234A2 PADD15 U256 F256 E144 233b4
Text: Diagram Page 14 of 15 Pin Information for the Cyclone® III EP3C25 Device Version 1.1 Version , Pin Information for the Cyclone® III EP3C25 Device Version 1.1 Notes (2),(3) Bank VREFB Number , L6 L2 L1 DQ1L DQ1L L4 DQ1L EP3C25 Pin List Adj. Adj. Page 1 of 15 Pin , DQ3B DM5B/BWS#5B DQ5B DQ5B EP3C25 Pin List DQ5B DQ3B DQS3B/CQ3B#, DPCLK2 DQS3B/CQ3B , Res. Res. Res. Res. DQ5B Page 2 of 15 Pin Information for the Cyclone® III EP3C25 Device


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PDF EP3C25 PT-EP3C25-1 EP3C25 pin diagram F324 altera cyclone III EP3c25 234A2 PADD15 U256 F256 E144 233b4
2007 - EP3C120

Abstract: altera cyclone 3 pins EP3C25
Text: . EP3C25 ES Revision B and C MSEL Pin Connection Fixed in EP3C25 Revision D and EP3C120 Revision , configuration starts. For a solution, refer to "MSEL Pin Connection". Momentary current surge from the VCCINT supply after configuration. EP3C25 ES Revision B and C EP3C120 ES Revision A Fixed in EP3C25 Revision D, EP3C120 ES Revision B and EP3C120 Revision C Issue with static current in I/O , Family Configuration Transition Current Issue Cyclone III EP3C25 ES Revision B and C and EP3C120


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PDF ES-01020-2 EP3C120 altera cyclone 3 pins EP3C25
2009 - EP3C25

Abstract: F324 E144 F256 U256 EP3C25 pin guideline
Text: Pin Information for the Cyclone® III EP3C25 Device Version 1.4 Notes (2), (3) Bank Number , 14 Pin Information for the Cyclone® III EP3C25 Device Version 1.4 Notes (2), (3) Bank Number , of 14 Pin Information for the Cyclone® III EP3C25 Device Version 1.4 Notes (2), (3) Bank , Pin Information for the Cyclone® III EP3C25 Device Version 1.4 Notes (2), (3) Bank Number VREFB , DQ1R Pin List Page 4 of 14 Pin Information for the Cyclone® III EP3C25 Device Version 1.4


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PDF EP3C25 PT-EP3C25-1 F324 E144 F256 U256 EP3C25 pin guideline
ttl to mini-lvds

Abstract: mini-lvds connector point-to-point mini-lvds mini-lvds EQFP-144 cyclone iii EP3C10 EP3C25 EP3C40 EP3C120F780
Text: left and right I/O banks, some of the differential pin pairs (p and n pins) of the dedicated output drivers are not located on adjacent pins. In these cases, a power pin is located between the p and n pins. Refer to the pin tables on the Altera web site at www.altera.com for more details about the location of , differential output drivers that require an external resistor network. Refer to the pin tables on the Altera , Differential Channels Device Package Pin Count User I/O Clock Pin Total 4 20 EP3C5


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PDF CIII51008-1 ttl to mini-lvds mini-lvds connector point-to-point mini-lvds mini-lvds EQFP-144 cyclone iii EP3C10 EP3C25 EP3C40 EP3C120F780
2010 - altera Date Code Formats Cyclone 2

Abstract: altera marking Code Formats Cyclone 2 EP3CLS200 EP3CLS150 ALTERA die identifier EP3C55 EP3C25 EP3C120 cyclone temperature Altera Cyclone V
Text: devices For a solution, refer to MSEL Pin Connection. Momentary current surge from the VCCINT supply after configuration. EP3C25 ES Revision B and C Fixed in: EP3C120 ES Revision A EP3C25 Revision D EP3C120 Revision B EP3C120 Revision C M9K Memory Block Read Issue The Cyclone III , . Cyclone III Device Family Errata Sheet © June 2010 Altera Corporation MSEL Pin Connection 1 , standard. (2) You must use a 200-MHz memory component speed grade. MSEL Pin Connection Altera has


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PDF 65-nm 60-nm 60-nm: EP3C55, EP3C80, EP3C120 EP3CLS150 EP3CLS200 altera Date Code Formats Cyclone 2 altera marking Code Formats Cyclone 2 ALTERA die identifier EP3C55 EP3C25 cyclone temperature Altera Cyclone V
2007 - EP3C40F484

Abstract: pin information ep3c10 PIN INFORMATION FOR EP3C55 EP3C16F484 U256 EP3C40 EP3C16 EP3C40Q240 100 PIN PQFP ALTERA DIMENSION EP3c55
Text: Changes Made July 2007 2.2 Updated values for EP3C25 (E144) device in Table 2. May 2007 2.1 , 19.4 17.7 16.2 6.9 EP3C25 E144 20 17.5 15.4 14 8.4 EP3C25 Q240 27 24.5 21.8 17.6 4.2 EP3C25 F256 27.5 24.1 22.2 20.7 8.5 EP3C25 U256 27.9 24.5 22.6 21.1 9.1 EP3C25 F324 26.6 23.1 21.3 19.8 8 , F484 22.5 18.5 16.4 14.8 9.8 EP3C25 F256 27.5 23.2 20.9 19.1 12.6


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PDF EP3C25 EP3C10 EP3C40F484 pin information ep3c10 PIN INFORMATION FOR EP3C55 EP3C16F484 U256 EP3C40 EP3C16 EP3C40Q240 100 PIN PQFP ALTERA DIMENSION EP3c55
DDR2 sdram pcb layout guidelines

Abstract: Memory Interfaces BGA and eQFP Package sdram bga pcb layout guide SSTL-18 EP3C55 EP3C40 EP3C25 EP3C16 eQFP
Text: , a DM pin and DQ pins. DQ groups on the left and right sides of EP3C16, EP3C25 , and EP3C40 (of the , EP3C25 (of the 144- pin EQFP package) do not support DM pin . Data and Data Clock/Strobe Pins Cyclone , Package EP3C25 144- pin EQFP (2) Side Number Number Number Number Number Number of ×8 of ×9 , to Figure 9­4: (1) The DQS/CQ/CQ# pin locations in this diagram applies to all packages in the Cyclone III family except EP3C5, EP3C10, EP3C16 and EP3C25 devices in 144- pin EQFP package. 9­8


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PDF CIII51009-1 DDR2 sdram pcb layout guidelines Memory Interfaces BGA and eQFP Package sdram bga pcb layout guide SSTL-18 EP3C55 EP3C40 EP3C25 EP3C16 eQFP
2009 - point-to-point mini-lvds

Abstract: ttl to mini-lvds EP3CLS200 EP3CLS150 EP3CLS100 mini-lvds connector EP3C40 mini lvds mini-lvds mini-lvds source driver
Text: . On the left and right I/O banks, some of the differential pin pairs (p and n pins) of the true output drivers are not located on adjacent pins. In these cases, a power pin is located between the p , 49 8 4 61 FBGA 115 8 4 127 FBGA EP3C40 31 FBGA FBGA EP3C25 , Devices 5 4 9 EP3C5 and EP3C25 6 4 10 EP3C10 and EP3C16 5 4 9 6 4 , 4 14 EP3C16 and EP3C25 23 8 31 EP3C16 and EP3C40 11 8 19 EP3C25 and


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PDF CIII51008-3 point-to-point mini-lvds ttl to mini-lvds EP3CLS200 EP3CLS150 EP3CLS100 mini-lvds connector EP3C40 mini lvds mini-lvds mini-lvds source driver
2010 - PCN0904

Abstract: EP3C10E144C8N EP3C16Q240C8N EP3C16F484C6 EP3C40F780I7N ep3C40F484C8N ep3c16 EP3C25E144I7N EP3C25F324C8N EP3C120F484I7N
Text: Line Pin Count Package Type Sample Availability Earliest Shipment EP3C120 EP3C120 , Cyclone III Device Transition Dates Product Line Pin Count Package Type Estimated Sample Availability EP3C40 EP3C40 EP3C40 EP3C40 EP3C40 EP3C25 EP3C25 EP3C25 EP3C25 EP3C25 EP3C16 EP3C16


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PDF PCN0904 65-nm 60-nm PCN0904, EU-REP3C16U484I7N EP3C10E144C7 EP3C10E144C7N EP3C10E144C8 PCN0904 EP3C10E144C8N EP3C16Q240C8N EP3C16F484C6 EP3C40F780I7N ep3C40F484C8N ep3c16 EP3C25E144I7N EP3C25F324C8N EP3C120F484I7N
2007 - EP3SL70F780

Abstract: EP3SE50F780 EP3SE110F1152 EP3SL110F1152 EP3SL70F484 EP3C25U256 EP3SL70 EP3SE50F484 EP3C120F780 EP3C120F484
Text: Fixed for altpll_reconfig Megafunction . 8 Fixed EP3C25 M9K Memory Block Read Issue , Corporation RN-01028-1.0 Device EP1AGX20 EP1AGX50 EP1AGX90 HC210 HC220 HC240 EP3C10 EP3C25 EP3C55 , transceiver I/O banks (Bank 13, 14, 15, 16 and 17), connect each pin marked GND* either individually through , GND. For non-transceiver I/O banks, connect each pin marked GND* directly to GND or leave it unconnected. Connect each pin marked GXB_VCC* either individually through a 10 KOhm resistor to VCCT/VCCR


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PDF RN-01028-1 EP3SL70F780 EP3SE50F780 EP3SE110F1152 EP3SL110F1152 EP3SL70F484 EP3C25U256 EP3SL70 EP3SE50F484 EP3C120F780 EP3C120F484
PCN0714

Abstract: EQFP-144 XZ074 EQFP 144 PACKAGE altera TQFP 32 PACKAGE EPM7128S EPF8636A EPF8452A ep1k30 pin E144
Text: (Part 1 of 2) Package Pin 160 PQFP 208 Altera Corporation Product Line EPF8452A , Affected by PCN0714 (Part 2 of 2) Package Pin TQFP 32 TQFP 144 Altera Corporation , Pin PQFP 240 EQFP 144 Altera Corporation Product Line EP20K100 EP20K60E EP20K100E , EPF6024A EPF81188A EPF81500A EP1C12 EP1C6 EP2C20 EP3C16 EP3C25 EP3C40 EP3C5 EP3C10 EP3C16 EP3C25 Earliest Shipment Date October 2010 October 2010 October 2010 October 2010 October 2010


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PDF PCN0714 PCN0714; EP20K100 EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EPF10K100E EPF10K130E EQFP-144 XZ074 EQFP 144 PACKAGE altera TQFP 32 PACKAGE EPM7128S EPF8636A EPF8452A ep1k30 pin E144
EQFP-144

Abstract: mini-lvds source driver EP3C55 EP3C40 EP3C25 EP3C16 EP3C120 EP3C10 SSTL-18 EP3C25 pin diagram
Text: interfaces. The Altera® Quartus® II software completes the solution with powerful pin planning features that , chapter contains the following sections: Overview Each Cyclone III device I/O pin is fed , Devices (EP3C5, EP3C10, EP3C25 , EP3C55, EP3C80, and EP3C120) Column I/O Block Contains up to Four IOEs , io_datain (combinational or registered) inputs. The pin 's datain signals can drive the logic array. The , Resistor aclr/prn Chip-Wide Reset Output Pin Delay Output Register D sclr/ preset Current


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2010 - 74 series family

Abstract: EP3C10 EP3CLS200 mini-lvds driver receiver altLVDS mini-lvds source driver EQFP-144 EP3CLS70 BGA and eQFP Package EP3C16M164
Text: completes the solution with powerful pin planning features that allow you to plan and optimize I/O system , Resistor aclr/prn Chip-Wide Reset Output Pin Delay Output Register D sclr/ preset Current , clkin oe_in Q Bus Hold Input Pin to Input Register Delay or Input Pin to Logic Array , offers a range of programmable features for an I/O pin . These features increase the flexibility of I/O , Cyclone III device family I/O pin has a programmable current strength control for certain I/O standards


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2008 - pin information ep3c10

Abstract: u256 EP2C35-F484 E144 EP3C10 EP3C16 EP3C25 F256 M164
Text: EP3C25 (E144) device in Table 2. May 2007 2.1 Updated values for EP3C10 (E144) device in Table 2 , F484 EP3C40 25.1 28.8 U484 EP3C25 28.5 U256 19.8 16.3 14.6 13.2 4.8 , 18.5 27.5 F324 EP3C40 22.5 F256 U256 EP3C25 16.8 13.1 11.3 9.9 5.9 , 16.4 324 6 100 256 EP1C12 JC (°C/W) 256 EP1C6 Package 240 EP1C3 Pin , ./min. Pin Count Package JC (°C/W) 324 FBGA 5.0 21.0 17.7 15.6 14.1 400


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PDF EP3C25 EP3C10 pin information ep3c10 u256 EP2C35-F484 E144 EP3C10 EP3C16 EP3C25 F256 M164
2007 - TSMC embedded Flash

Abstract: EQFP 144 PACKAGE pin information ep3c10 cyclone III 484-pin BGA FPGA package point-to-point mini-lvds SSTL-18 EP3C55 EP3C40 EP3C25 pin guideline EP3C16
Text: ) 256- pin FBGA 182 84 148 168 182 215 346 780- pin FBGA 256- pin UFBGA 182 182 168 484- pin UFBGA 377 429 531 327 295 EP3C40 283 156 324- pin FBGA 484- pin FBGA 295 82 160 327 331 EP3C25 EP3C16 94 331 535 94 240- pin PQFP1 EP3C120 144- pin EQFP EP3C80 Enhanced thin quad flat pack (E) EP3C10 Unless noted , industrial temperatures Cyclone III FPGA features EP3C10 EP3C16 EP3C25 EP3C40 EP3C55


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PDF 65-nm SG-01003-2 TSMC embedded Flash EQFP 144 PACKAGE pin information ep3c10 cyclone III 484-pin BGA FPGA package point-to-point mini-lvds SSTL-18 EP3C55 EP3C40 EP3C25 pin guideline EP3C16
565 PLL

Abstract: pll 566 pll 565 ma 8601 pll 565 application Mini Toggle Switch Series 727 CIII52001-1 PCI 6602 EP3C120 EP3C16
Text: current, per pin ­25 40 mA VE S D H B M Electrostatic discharge voltage using the human , Figure 1­1, overshoot voltage is shown in red and is present on the Cyclone III input pin at over 4.1 V , , pin capacitance, on chip termination tolerance, and bus hold specifications for Cyclone III devices , design. Table 1­4 lists I/O pin leakage current for Cyclone III devices. Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 1 of 2) Symbol Parameter Conditions Min Typ


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PDF CIII52001-1 565 PLL pll 566 pll 565 ma 8601 pll 565 application Mini Toggle Switch Series 727 PCI 6602 EP3C120 EP3C16
PCN0802

Abstract: ALTERA PART MARKING tsmc EP3C5 EP3C55 EP3C40 EP3C25 EP3C16 EP3C120 EP3C10
Text: FAB 14 Product Family EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 Altera , at FAB 14 Table 2. Transition Timeframe Product Family EP3C5 EP3C10 EP3C16 EP3C25 EP3C40


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PDF PCN0802 JESD46-C, PCN0802 ALTERA PART MARKING tsmc EP3C5 EP3C55 EP3C40 EP3C25 EP3C16 EP3C120 EP3C10
2007 - EP3SE50

Abstract: ep2s30 pinout HC210 EP3C10 EP3C120 EP3C25 EP3C55 ep3sl340 pinout
Text: EP3SE110 EP3SL200 EP3SL340 EP3C10 EP3C25 EP3C55 EP3C120 HC210WF484 EP3SL70 EP3SL150 EP3SE260 , HC210 HC220 HC240 EP3C10 EP3C25 EP3C55 EP3C120 EP3SE50 EP3SE110 EP3SL200 EP3SL340 HC210W , II software earlier than 7.0, the Pin-Out file (. pin ) incorrectly specifies that VCCA pins be


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PDF RN-01024-1 EP3SE50 ep2s30 pinout HC210 EP3C10 EP3C120 EP3C25 EP3C55 ep3sl340 pinout
2006 - cyclone III datasheet

Abstract: 8 x8 array multiplier verilog code EP3C40 pin definition 16 bit array multiplier VERILOG EP3C55 EP3C40 EP3C25 EP3C16 EP3C120 E144
Text: Features Feature EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 Logic , package options and user I/O pin counts. The highest I/O count in the family is delivered by the EP3C40. Table 1­2. Cyclone III FPGA Package Options and I/O Pin Counts Notes (1), (2), (3) 144- pin Plastic Enhanced Quad Flat Pack (EQFP) (5) 240- pin Plastic Quad Flat Pack (PQFP) 256- pin FineLine Ball-Grid Array (FBGA) 256- pin Ultra FineLine Ball-Grid Array (UBGA)(6) EP3C5 94 -


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PDF CIII51001-1 65-nm cyclone III datasheet 8 x8 array multiplier verilog code EP3C40 pin definition 16 bit array multiplier VERILOG EP3C55 EP3C40 EP3C25 EP3C16 EP3C120 E144
2007 - 8609 396 81 15 765

Abstract: EP3C16 A 3120 0532 8 pin PCI 6602 CV 7599 diode EP3C25 pin diagram
Text: voltage DC output current, per pin Electrostatic discharge voltage using the human body model , Cyclone III input pin at over 4.1 V but below 4.2 V. From Table 1­1, for an overshoot of 4.1 V the , . DC Characteristics This section lists the I/O leakage currents, pin capacitance, on chip termination , Power Estimator to get the supply current estimates for your design. Table 1­4 lists I/O pin leakage current for Cyclone III devices. Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 1


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PDF CIII52001-1 8609 396 81 15 765 EP3C16 A 3120 0532 8 pin PCI 6602 CV 7599 diode EP3C25 pin diagram
2008 - 5252 F 1105 transistor

Abstract: max 8770 TMS 3617 AS 12308 c 5296 Horizontal Output transistor, EP3C25 pin guideline fa 5571 tms 3878 transistor c 5936 circuit diagram
Text: . 9­3 Cyclone III Memory Interfaces Pin Support , . 10­7 Configuration and JTAG Pin I/O Requirements


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EP4CE15

Abstract: EP4CE40 EP4CE30 EP4CGX30CF23 EP4CE22 EP4CE10 EP4CE75 EP2AGX190 Altera EP4CE6 EP4CE6
Text: , EP2C20) Cyclone III (EP3C5, EP3C10, EP3C16, EP3C25 , EP3C40) Cyclone IV E (EP4CE6, EP4CE10, EP4CE15 , SP1 EP3C25 Final ­ 7.2 SP1 EP3C40 Final ­ 8.0 EP3C55 Final ­ 8.0 EP3C80 Final , VCCIO pin count incorrect with device migration turned ON When you migrate from a Stratix IV to a HardCopy IV or HardCopy IV GX device, if a pin is NC in the Stratix IV device and VCCIO in either HardCopy


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PDF RN-01053 EP4CE15 EP4CE40 EP4CE30 EP4CGX30CF23 EP4CE22 EP4CE10 EP4CE75 EP2AGX190 Altera EP4CE6 EP4CE6
2010 - EP4CE22f17

Abstract: EP4CE115F29 EP4CE40F23 EP4CE6E22 EP4CE15f17 EP4CE10E22 EP4CE6F17 EP4CE30F EP4CE10F17 EP4CE15F23
Text: ) Cyclone II (EP2C5, EP2C8, EP2C20) Cyclone III (EP3C5, EP3C10, EP3C16, EP3C25 , EP3C40) Cyclone IV E , EP3C5 Final ­ 8.0 SP1 Final ­ 8.1 Final ­ 8.0 SP1 EP3C16 Final ­ 8.0 SP1 EP3C25 , Page 8 Changes in Device Support Applies to: Cyclone IV GX Devices VCCIO pin count incorrect , device, if a pin is NC in the Stratix IV device and VCCIO in either HardCopy device, the migration


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PDF RN-01051-1 EP4CE22f17 EP4CE115F29 EP4CE40F23 EP4CE6E22 EP4CE15f17 EP4CE10E22 EP4CE6F17 EP4CE30F EP4CE10F17 EP4CE15F23
2008 - 3841 9904

Abstract: 5053 resistor NCE 7190 DR 6236 078
Text: EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 Parameter Input Pin Leakage Current , 5 Unit pF pF pF Notes to Table 1­9: CV R E F T B for EP3C25 is 30 pF. When VREF pin is used , PLL DC input voltage DC output current, per pin Electrostatic discharge voltage using the human body , input pin at over 4.1 V but below 4.2 V. From Table 1­1, for an overshoot of 4.1 V, the percentage of , currents, pin capacitance, on-chip termination tolerance, and bus hold specifications for Cyclone III


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PDF CIII52001-2 3841 9904 5053 resistor NCE 7190 DR 6236 078
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