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EL B17 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
EL B17

Abstract: 74LVT16500A 74LVT16500ADGG 74LVT16500ADL LVT16500A fnd display
Text: ] B14 vcc [22 35] Vcc A15 [23 E B1S A16 E 33] B16 GND E 32] GND Al 7 [26 El B17 OEBA E 30


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PDF ABT18-bit 74LVT16500A 18-bit 64mA/-32mA 500mA 74LVT16 510MHz 500ns EL B17 74LVT16500A 74LVT16500ADGG 74LVT16500ADL LVT16500A fnd display
1999 - p22v10

Abstract: ba 5412 5412 DATASHEET Motorola phone schematic diagram mpc860 atm MPC860 memory controller HD15 MC68360 MPC860 TMS320C6000
Text: B8 B23 B7 B7 B7 B11 B17 B19 150ns B22b td(HSTBL-HRDY H ) th(HST BH-HDV ) td( HST BH-HD HZ ) tPLD B8 B8 B8 B23 B7 B7 B7 B17 B19 250ns , td (H ST B L -H R D Y H ) tw ( H ST B L) tsu(H D -H STB H ) ts u (S EL - H ST B L) B12 5 , tPL D tw ( H ST B L) tsu(H D -H STB H ) ts u (S EL - H ST B L) B23 th( H ST B H -H D ) B7 B8 B8 B8 B11 B17 10 0n s B9 B7 B30 B7 B30 B2 9b tPL D th( H ST B H


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PDF SPRA546 TMS320C6000 MPC860 MPC860 p22v10 ba 5412 5412 DATASHEET Motorola phone schematic diagram mpc860 atm MPC860 memory controller HD15 MC68360
EL B17

Abstract: No abstract text available
Text: JACKET B11 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 GND TxTx+ GND - 14 10 -P X X-O O -X.XX Vendor ID:!' 'Lo t# : YYWW B12 B13 B14 B15 B16 * B17 B18 B19 - GND Tx+ TxGND GND Rx+ RxGND 3. JA C K E T T Y P E S : H A LO G EN F R E E / G> LA B EL DETAIL 4 . C A B LE FLAMM ABILITY


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PDF EC0-0035953 EL B17
1998 - AA23

Abstract: AC13 AF14 EL B17
Text: Global OE Pins and One Product Term OE per Macrocell Input Bus IM EL · 100% IEEE 1149.1 , 5384v_01 1 October 1998 Specifications ispLSI 5384V Functional Block Diagram IN IM EL , Members EL The ispLSI 5000V family ranges from 256 macrocells to 512 macrocells and operates from a , PT 160 PT 160 160 D D 160 5 PT 160 32 32 Q D EL 32 IM 24 , EL PT 76 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 . 5


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PDF 272-BGA 388-BGA 384V-125LB272 272-Pin 384V-125LB388 388-Pin 384V-100LB272 384V-100LB388 AA23 AC13 AF14 EL B17
2012 - Not Available

Abstract: No abstract text available
Text: length ‘EL’ : EL =500 mm Overall length “OL” : 650 mm Tag plate : SS tag plate Example , SWG (0.50 mm) 29 29 SWG (0.35 mm) XX OL T EL Single KER-710 Support Protecting Tube , OL T EL F Screwed type, flameproof, IP-67, Gr. IIA IIB in Die-cast Aluminum E Screwed type , EL - Specify in mm. OL - Specify in mm. X Support Tube Material 1 Example XXX 21 22 , 1” 150 # B16 3/4” 300 # B22 1” 300 # B17 3/4” 600 # B23 1” 600 # B33 1 ½” 150 # B34


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PDF
SD-87715-901

Abstract: PCI x1 express PCB dimensions SD-87715-207 5B00 PK-87715-207 87715-9306 molex pci express axis sd card EL B17
Text: 'C'A X1 36 6 8.15 B17 X4 6 A 20 22.15 B17 , B31 X8 98 37 39.15 B17 , B31 B48 X16 164 70 72.15 B17 , B31 , . TIN PLATING. 2-3.UNDER PLATING: NO EL PLATING OVERALL. 3.DATE CODE: YY MM DD. -i.PRODUCT SPECIFICATION , WIDTH s POS REF N DIM 'B' 'U a X1 36 6 8.15 B17 X16 164 70 72.15 B17 , B31 B48,B81 I/O PANEL DIRECTION -


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PDF UL94V-0, PS-87715-200. PK-87715-207. TS-87715-207. 2007/05/H 2007/05/K 2007/05/U sd-87715-901 PCI x1 express PCB dimensions SD-87715-207 5B00 PK-87715-207 87715-9306 molex pci express axis sd card EL B17
JE 100 ETZ

Abstract: ENS150-11A EL B17 125/160 NSL 200a liu JISC0806 09Z-OZZ SI-021SN3 SI-080SN3
Text: –¡ ■y h 1.6±0.3 tz u EL Sfi «« m 01 <5r-a 02 îKSâiîA^&iI) TT 1.6±0.3 2± 0.1 I—1 C , \ I, -50 0 50 1 m m %i a T8 ro Breakover Voltage oo -50 0 50 J3 El ift J* Ta CC) Dynamic , 0. 1 I 10 £P to IE Vb (V) Junction Capacitance 100 B-17 WJf«— ciuffi— oooooo-ooo-ooo , Ss«m\/wm\ (i?) *06 OST 09Z-OZZ oot £12 EL -0Ï2SN3 S6 091~ SSI OST 031 VLL-0SLSN3 OOT 56 Ol , 89 El-0¿0SN3 *0ZZ OSI 0Z —SS 001 OS £ 1-090SN3 (VLU)H| ¿¿MSyfr (A]oaA sa*'-* un (a)s,si


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PDF ENS150-11A 10/looojus, l95t/R89 JE 100 ETZ ENS150-11A EL B17 125/160 NSL 200a liu JISC0806 09Z-OZZ SI-021SN3 SI-080SN3
B21G

Abstract: No abstract text available
Text: (SEE MA TH M O D EL FOR P R E C I S E D IM EN S I O NS ) . FOR ALL O T H ER D I M E N S I O N S NOT S H O W N BUT R E Q U I R E D FOR TOOL B U I LD s SEE MATH M O D EL FOR P R E C I S E TOOL PAT H , 12191811 C A V I T I E S Big B 2 S B 7 s B8 9 B 9 9 B 1 0 9 B 1 5 9 B16g B17 , B 18, B2 3, B24, B 2 5 , SEPARATELY, REGARDLESS OF DATUM REFERENCE. PROCESS SENSITIVE DIMENSION DIMENSIONAL RANGE (MM) CHART El


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PDF 15N000 27MR01 25JN01 30JA02 B21G
2008 - A3PE600L

Abstract: 896-Pin FBGA 896 A3PE3000L IO283PDB7V1 A3P1000 IO10PDB0V1 ProASIC3 EL B17 AF29
Text: Military ProASIC3/ EL Packaging 3 ­ Package Pin Assignments 208-Pin PQFP 1 208 208 , TDO 3 -2 v1.0 Military ProASIC3/ EL Packaging 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP , ProASIC3/ EL Packaging 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA Pin Number A3P1000 Function , VPUMP M12 GNDQ 3 -6 v1.0 Military ProASIC3/ EL Packaging 484-Pin FBGA A1 Ball Pad , B17 IO30PDB1V1 D8 IO05PDB0V0 A5 IO06PDB0V1 B18 IO32PDB1V1 D9 IO10PDB0V1


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PDF 208-Pin A3P1000 IO199PDB3 IO162RSB2 A3PE600L 896-Pin FBGA 896 A3PE3000L IO283PDB7V1 IO10PDB0V1 ProASIC3 EL B17 AF29
BUS-6552211

Abstract: 69053 EL B17
Text: Counter · On-board Memory Management LED INDICATORS (BRIGHT GREEN) (GREEN) (YELLOW) (RED) El , B6 B7 B8 B9 B10 B11 B12 B13 B14 B1S B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31


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PDF BUS-6552211, MIL-STD-1553B MILSTD-1553B BUS-65522ITs MIL-STD-1553 BUS-6552211 BUS-85522H BU8-65S23H BUS-6552X 69053 EL B17
EL B17

Abstract: No abstract text available
Text: B16 GND B17 ÜPBA GND 24 16 13 6D m m 40] 39] 38] El 49 44 E [2 2 [2 3 El 36] 35 ] A15 A16 GND A17 O tB A LEBA E E |2 6 El 33] 32] E [2 8 El 30] 29 ] SW000 , A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B9 B10 B11 B12 B13 B14 B15 B16 B17 , A10 A11 GND A12 A13 A14 < O O E E E E E E E E E E E E E E E E E E E [2 0 E 53] El ID 5o


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PDF 74ABT16500C 74ABTH16500C 18-bit /-32m 500mA EL B17
1999 - EL B17

Abstract: No abstract text available
Text: Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell EL ispLSI 5000V Description , 165 I/O 164 Generic Logic Block Input Bus EL I/O 68 I/O 69 I/O 70 I/O 71 I/O 147 I/O , line from each I/O pin. EL GLBs 8 12 16 Table 1. ispLSI 5000V Family PR The input buffer , 24 32 32 672 D Q 32 24 24 I/O EL 160 5 PT 160 PT 5 160 68 160 160 PT 160 68 5 PT 5 PR 24 , PT (P)reset 1 To I/O Pad EL To GRP PR 6 Global PTOE 0 . 5 PT 159 PT 158 PT 157


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PDF 208-Pin 208-Ball 272-Ball 388-Ball EL B17
1999 - 5384V-125LB208

Abstract: AC13 AF14 202 ball bga EL B17
Text: IN A Input Bus IM PR EL · ARCHITECTURE FEATURES - Enhanced Pin-Locking Architecture , I/O 217 I/O 216 I/O 239 I/O 238 I/O 237 I/O 236 IN M EL I PR Generic Logic , each macrocell output and one line from each I/O pin. EL The interconnect structure (GRP) is , PT Q 24 EL I 32 IN Q 32 M 32 24 I/O 32 32 24 24 5 A , PR PT 158 EL PT 75 From PTSA PTSA bypass Shared PT Clock 0 Shared PT (P)reset 0


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PDF 384V-125LB208 208-Ball 384V-125LB272 272-Ball 384V-125LB388 388-Ball 384V-100LQ208 384V-100LB208 208-Pin 5384V-125LB208 AC13 AF14 202 ball bga EL B17
EL B17

Abstract: No abstract text available
Text: E E E E E E [20 El 53 ] Ü ID 50 ] 49 ] 48] vcc B3 B4 B5 GND B6 B7 B8 B9 B10 B11 GND B12 B13 B14 VC C B15 B16 GND B17 CPBA GND El 46] 1V 4V A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 24 16 17 BIO B11 B12 B13 B14 B15 B16 B17 13 14 10 6D B1 B2 B3 B4 B5 B6 B7 1 1 44] « 1 1 1 ID 4Ô*| 39] 38] El 36] E [22 [23 35 ] E E [26 El 33 ] 32 ] E


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PDF 74LVT16501A 18-bit 74LVT16501A /-32m EL B17
1999 - 5384VA

Abstract: AF14 EL B17
Text: IN A Input Bus IM PR EL · ARCHITECTURE FEATURES - Enhanced Pin-Locking Architecture , Specifications ispLSI 5384V Functional Block Diagram Generic Logic Block IN IM EL 1. CLK2, CLK3 , each macrocell output and one line from each I/O pin. EL The interconnect structure (GRP) is , 24 A 24 32 32 D D IN Q 160 PT 5 160 IM 24 32 32 Q D EL , PR PT 158 EL PT 75 From PTSA PTSA bypass Shared PT Clock 0 Shared PT (P)reset 0


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PDF 384V-125LB208 208-Ball 384V-125LB272 272-Ball 384V-125LB388 388-Ball 384V-100LQ208 384V-100LB208 208-Pin 5384VA AF14 EL B17
1999 - AC13

Abstract: AF14 EL B17
Text: Generic Logic Block Input Bus IM EL · ARCHITECTURE FEATURES - Enhanced Pin-Locking , ispLSI 5384V Functional Block Diagram IN IM EL PR 1. CLK2, CLK3 and TOE signals are , . ispLSI 5000V Family Members EL IM The ispLSI 5000V family ranges from 256 macrocells to 512 , 32 32 Q D EL 32 IM 24 24 24 32 D 672 32 PR 24 D 160 5 , bypass PT 7 PT 6 IN PT 78 PT 77 EL PT 76 Shared PT Clock 1 Shared PT (P)reset 1 6


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PDF Bus08* 208-Ball 384V-125LB272 272-Ball 384V-125LB388 388-Ball 384V-100LQ208* 208-Pin 384V-100LB208* AC13 AF14 EL B17
B20 N03

Abstract: b20 p03 aa09 B07 P03 Y14W AA19 119N03 b09 n03 GS214 EL B17
Text: B17 B18 B19 B20 B21 C01 C02 C03 C04 C05 C06 C07 C08 C09 CIO S ig n a l N am a VMM PSCID02 NSCID03 , NOI N02 P in N u m b a r E05 E06 E07 E08 E09 E10 El 2 El 3 El 4 El 5 E16 El 7 El 8 El 9 E20 E21 , U21 V05 V18 V19 V20 V21 W05 Y01 Y02 Y06 Y16 E04 El 8 U04 U18 D19 B21 Signal Nama NSCIDIO NSCIDI1 , B16 C17 B17 A18 A06 B18 C19 B06 C07 A07 B08 C08 C09 A19 A20 D20 C20 T02 TOI JOl D03 Signal Nam , B07 B15 B19 COI C04 C06 CIO C12 C16 C18 C21 D09 DU D13 E02 E05 E08 E09 ElO El2 El 3 E14 El5 Signal


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PDF VSC7203 27mm/side) B20 N03 b20 p03 aa09 B07 P03 Y14W AA19 119N03 b09 n03 GS214 EL B17
2000 - 64MX16

Abstract: EL B17
Text: GND LDQB0 GND LDQB2 GND LDQB4 GND LDQB6 GND LSCK GND SOUT Vdd NC GND NC VCMOS NC FEATURES Pr el , A38 A39 A40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 , Pr el im in ar y Gnd VCMOS U3 Direct RDRAM U4 Direct RDRAM C O N FI D EN TI AL SVDD


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PDF UGD64R16 04U6J 128/144MB 18bits 800MHz 600MHz 160-Pin 160pin 32banks, 64MX16 EL B17
1999 - AC13

Abstract: AF14 388-BGA max 232 G4 EL B17
Text: per Macrocell Generic Logic Block Input Bus IM EL · 100% IEEE 1149.1 BOUNDARY SCAN , Bus R Y Generic Logic Block IN A Generic Logic Block Input Bus Input Bus EL , Members EL IM The ispLSI 5000V family ranges from 256 macrocells to 512 macrocells and operates , 32 32 Q D 160 5 PT A 32 32 Q D 160 PT 5 160 68 EL 18 18 I/O , 77 EL PT 76 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 . 5


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PDF 388-BGA 512V-110LB388 388-Ball 512V-100LB388 512V-70LB388 AC13 AF14 388-BGA max 232 G4 EL B17
1999 - Not Available

Abstract: No abstract text available
Text: Term OE per Macrocell Generic Logic Block Input Bus IM EL • 100% IEEE 1149.1 BOUNDARY , Logic Block Input Bus Input Bus EL IM Generic Logic Block PR Generic Logic Block , , a D-type latch or a T-type flip flop. ispLSI 5000V Family Members EL IM The ispLSI 5000V , 32 Q D 160 PT 5 160 68 EL 18 18 I/O IM 160 5 PT 32 D Q PR , Macrocell 1 PT 9 PT 8 From PTSA PTSA bypass PT 7 PT 6 IN PT 78 PT 77 EL PT 76


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PDF 388-BGA 512V-110LB388 388-Ball 512V-100LB388 512V-70LB388
1999 - AC13

Abstract: AF14 EL B17
Text: per Macrocell Generic Logic Block Input Bus IM EL · 100% IEEE 1149.1 BOUNDARY SCAN , Bus R Y Generic Logic Block IN A Generic Logic Block Input Bus Input Bus EL , Members EL IM The ispLSI 5000V family ranges from 256 macrocells to 512 macrocells and operates , 160 PT 160 A 32 32 Q D 160 PT 5 160 68 EL 18 18 I/O IM 160 5 , 77 EL PT 76 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 . 5


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PDF 388-BGA 512V-110LB388 388-Ball 512V-100LB388 512V-70LB388 AC13 AF14 EL B17
2000 - EL B17

Abstract: No abstract text available
Text: higher efficiency PCB : Height (1230 mil), double sided component Pr el im in ar y PIN SYMBOL GND , B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 , LDQB8 Pr el im in ar y SIO0 SIO1 SCK CMD Vref SIO0 SIO1 SCK CMD Vref U3 Direct RDRAM C O


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PDF UGD128R16 08U6J 256/288MB 18bits 800MHz 600MHz 160-Pin UGD128R1608U6J-L6/G6/T6 256MB 128Mx16) EL B17
electric diagram acs 150

Abstract: B29B F98S MPC823 PA13 EL B17
Text: EL IM IN Output Low Voltage IOL = 2.0 mA CLKOUT IOL = 3.2 mAA[6:31], TSIZ0/REG, TSIZ1, D(0 , /HSYNC/PD4, SHIFT/CLK/PD3 2.4 µA EL Freescale Semiconductor, Inc. Signal Low Input , EL Layout Practices THERMAL CHARACTERISTICS CHARACTERISTIC + 273C) + qJA Each VCC pin on , inner layers as VCC a PR EL IM CAUTION: The JTAG and GPIO input voltages cannot be more than , : www.freescale.com ns ns EL INPUTS 3 8 - - ns 4 - 0.8V ns 28 2.0V


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PDF MPC823 electric diagram acs 150 B29B F98S PA13 EL B17
1996 - G30 922

Abstract: MB86907 AD29 AG20 AG21 AG25 ag20 ta EL B17
Text: Voltage Recommended Operating Conditions IN Table 7. Parameter 3.5V EL PLL Ground , Dissipation IM IN IOZ VCC=Max, Vin =VCC or GND, outputs static 2.3 - EL VDD1, VDD2 , Max tSI tHI EL IRL[3:0] STANDBY RY Table 9. PR Notes: 1. CPU_MODE[2:0], PLL_BYP , AFX_AEN AFX_SREPLY[1:0] AFX_CLK SB_PA[27:0] SB_CLK[2:0] PR AFX_ADDR[2:0] EL MF_CLK[1:0 , ns ns A IN IM EL PR 16 PRELIMINARY RY MEM_DATA[63:0] Highly Integrated 32


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PDF 32-bit PP-DS-20339-11/96 G30 922 MB86907 AD29 AG20 AG21 AG25 ag20 ta EL B17
TTL 7400

Abstract: ITT 7400 55199 IC 7400 nand gate N7421N ttl ttl7400 7400 signetics TTL 7400 signetics ITT301 Signetics SE 540
Text: Schmitt Trigger 55199F 1 B15 N7416N Hex Inverter Buffer/D'iver with-o/c 55200H 1 B17 N7417N Hex Buffer , Signetics Connection Diagram B17 Vçç 6A 6Y &A 5V 4A 4¥ ^TÌrerEmnìnir 2A 2Y 3A VCC 2D 2C NC ?B 2A , °7 [7 °8 [7 Dg [» DIO E GND [ü S El vcc E CUK2 U Q1 3 Q2 3 Q4 33 oB 33 33 °7 33 as 3 , 3 B3 CIN [j[ El f3 cOUT[I 3 <2 E E 3 b2 S E 3 A2 GND E 3 So B149 B148 B150 Q7(T- qse- Q9 , - IM 0 0 INPUTS OUTPUT OUTPUT B217 Vcc 30 3C NC M 3A 3V SlsljBHQQSl iè-l El


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PDF BS9400 N7400N 55181D N7401N 55182B N7402N 55184R N7403N TTL 7400 ITT 7400 55199 IC 7400 nand gate N7421N ttl ttl7400 7400 signetics TTL 7400 signetics ITT301 Signetics SE 540
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