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E2 hdb3 Datasheets Context Search

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1996 - pin diagram 14 demultiplexer

Abstract:
Text: data streams from the E2 intermediary stream. · If the LIU provides HDB3 decoding, NRZ data and , DHDNI DHHDB3C HDB3 Decoder Within the E2 and E3 standards, there are four extra bits used for , The SXT6234 E-Rate Multiplexer offers a simple and economic approach to building E1/ E2 , E2 /E3 and E1 , , E2 , and E3 specifications. The ITU-T was formerly known as the Consultive Committee for , Level Number System 1 E1 30 2.048 2 E2 120 8.448 3 E3 480 34.368


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PDF an9501 SXT6234 16-E1/E3 16E1/E3 SDB6234 pin diagram 14 demultiplexer E1 HDB3 multiplexing e1 frame to e3 frame HDB3 to nrz 16 line to 4 line coder multiplexer HDB3 E2 HDB3 1 into 12 demultiplexer circuit diagram how to interface microcontroller with encoder multiplexer 30 pin
2001 - LDB6234

Abstract:
Text: LXT6234, E1/ E2 Stage · If the tributary LIU does not perform HDB3 decoding, then the signals are routed , and clock to the LXT6234 1.7.4.2 LXT6234, E3/ E2 Stage · If the LIU does not do HDB3 decoding , . 5 E2 Standard , . 9 1.7.2.2 LXT6234, E1/ E2 Stage , .12 1.7.4.2 LXT6234, E3/ E2 Stage


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PDF LXT6234 AN9501. LDB6234 HDB3 HDB3 decoder multiplexing e1 frame to e3 frame E1 HDB3 E2 liu multiplexing e2 frame e3 nrz to hdb3 Multiplexing of four E2 streams into E3 stream multiplexing demultiplexing e2 e3
1997 - multiplexing e1 frame to e3 frame

Abstract:
Text: Multiplexer/Demultiplexer SXT6234, E3/ E2 STAGE · If the LIU does not do HDB3 decoding then the signals are , Tributary #1 Tributary #2 Tributary #3 Tributary #4 DHDNI DHHDB3C HDB3 Decoder Within the E2 , approach to building E1/ E2 , E2 /E3 and E1/E3 multiplexers and demultiplexers. This application note , ) standardized the E1, E2 , and E3 specifications. The ITU-T was formerly known as the Consultive Committee for , E2 120 8.448 3 E3 480 34.368 4 E4 1920 139.264 Speech 16


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PDF SXT6234 16-E1/E3 16E1/E3 SDB6234 multiplexing e1 frame to e3 frame HDB3 E2 1 into 12 demultiplexer circuit diagram HDB3 to nrz multiplexing e2 frame e3 design 16 bit demultiplexer introduction HDB3 decoder 1 into 16 demultiplexer circuit diagram using 1 i crystal oscillator 8.448
2001 - HDB3 AMI ENCODER DECODER

Abstract:
Text: Multiplexer can also serve as a five channel HDB3 coder and decoder. Applications n E1/ E2 Multiplexer (2/8 , negative RZ data.) 5.1.2 LXT6234, E1/ E2 Stage · The LXT6234 may interface with either HDB3 or , Multiplexer, stage E2 /E3. 1. Datasheet If the HDB3 decoder is on the line interface unit (LIU). 17 , four E1 channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line


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PDF LXT6234 LXT6234 HDB3 AMI ENCODER DECODER multiplexing e1 frame to e3 frame Frame structure for Multiplexing of four E2 streams into E3 stream LXT6234QE HDB3 to nrz multiplexer 30 pin intel 4e2 circuit diagram of 64-1 multiplexer HDB3 E2 hdb3
1999 - 16 line to 4 line coder multiplexer

Abstract:
Text: LXT6234 can also function as a stand alone five-channel HDB3 transcoder. E1/ E2 Multiplexer (2/8 Mbit , HDB3 E1 E2 E3 4 4 DLNRZO[1:4] DLCO[1:4] DHNRZI Demultiplexer DHDMXC DNAT And , Stage LXT6234, E1/ E2 Stage · The LXT6234 may interface with either HDB3 or non-HDB3 coded signals , into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E1


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PDF LXT6234 LXT6234 recommenda-1130 PDS-6234-7/99-2 16 line to 4 line coder multiplexer Frame structure for Multiplexing of four E1 streams into E2 stream LEVEL ONE COMMUNICATIONS LXT6234QE HDB3 Frame structure for Multiplexing of four E2 streams into E3 stream HDB3 DECODER mais E2 hdb3 E1 AMI HDB3 decoder
1997 - circuit diagram of 64-1 multiplexer

Abstract:
Text: ; formerly known as CCITT): G.742 recommendation for multiplexing four E1 channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The SXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E1, E2 , and E3 signals. The coder and decoder input/output pins are externally accessible, allowing either HDB3 or NRZ , HDB3 transcoder. E1/ E2 Multiplexer (2/8 Mbit/s) E2 /E3 Multiplexer (8/34 Mbit/s) E1/E3 Multiplexer


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PDF SXT6234 SXT6234 circuit diagram of 64-1 multiplexer E1 AMI HDB3 decoder Frame structure for Multiplexing of four E2 streams into E3 stream HDB3 Frame structure for Multiplexing of four E1 streams into E2 stream 16 line to 4 line coder multiplexer E1 HDB3 multiplexer/14052B multiplexing demultiplexing e2
1996 - E1 HDB3

Abstract:
Text: .742 recommendation for multi plexi ng four E1 channel s into an E2 frame; and the G.751 recommendation for mul tiplexing four E2 channels into an E3 frame. The SXT6234 E-Rate Multi plexer al so encodes and decodes HDB3 zero suppression line coding used on E1, E2 , and E3 signals. The coder and decoder input/output pins are external ly accessible, allowing either HDB3 or NRZ (non-return-to-zero) I/O to the mul tiplexer. The SXT6234 E-Rate Mul tiplexer can also serve as a five channel HDB3 coder and decoder. ·


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PDF SXT6234 SXT6234 E1 HDB3 16 line to 4 line coder multiplexer HDB3 AMI ENCODER DECODER HDB3 to nrz circuit diagram of 64-1 multiplexer Frame structure for Multiplexing of four E2 streams into E3 stream E1 AMI HDB3 decoder Frame structure for Multiplexing of four E1 streams into E2 stream HDB3 decoder
aux-04

Abstract:
Text: LXT6234 can also function as a stand alone five-channel HDB3 transcoder. E1/ E2 Multiplexer (2/8 Mbit , Glossary AIS AMI CCITT CODEC HDB3 El E2 E3 FIFO ITU NRZ PCB RZ 12 Alarm Indication , LXT6234, E1/ E2 Stage • The LXT6234 may interface with either HDB3 or non-HDB3 coded signals. Data from , into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E l


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PDF LXT6234 LXT6234 aux-04
1998 - 16 line to 4 line coder multiplexer

Abstract:
Text: SXT6234 can also function as a stand alone five-channel HDB3 transcoder. E1/ E2 Multiplexer (2/8 Mbit , Side Block Diagram AIS AMI CCITT CODEC HDB3 E1 E2 E3 4 4 DLNRZO[1:4] DLCO[1:4 , four E1 channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The SXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E1, E2 , and E3 signals. The coder and decoder input/output pins are externally


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PDF SXT6234 SXT6234 16 line to 4 line coder multiplexer LEVEL ONE COMMUNICATIONS circuit diagram of 64-1 multiplexer Frame structure for Multiplexing of four E2 streams into E3 stream Frame structure for Multiplexing of four E1 streams into E2 stream E1 HDB3 HDB3 AMI ENCODER DECODER 500E multiplexing demultiplexing e2
2001 - LDB6208

Abstract:
Text: E2AIS and , E2NAT bits setting MU X RX CH1 RX CH1 IN HDB3 ENC E2 Tx Ch1 AUX in Ch2 AUX in Ch3 AUX in Ch4 AUX in ME2AIS in ME2NAT in JP6 E2 Input & Output LXT332 HDB3 , Cable HDB3 DEC E2 Rx JP5 AUX Channel, E2AIS and E2NAT bits out monitors 1.2 E12 , circuit and includes all supporting circuitry for E1 and E2 multiplexer/ demultiplexer applications. The , input and output signals. JP1 is for E1 I/O and JP6 is for E2 I/O. JP4 is for Local Loop Back and


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PDF LDB6208 LXT6234 LXT6234 CON14 HEADER14P PE-65861 LXT332QE LDB6208 HDB3 E2 E1 HDB3 HDB3 nrz to hdb3 XR5683 HDB3 to nrz Header14 HEADER14P
HD b3c

Abstract:
Text: ): G .742 recom m endation for m ultiplexing four E l channels into an E2 fram e; and the G.751 recom m endation for m ultiplexing four E2 chan nels into an E3 frame. The SX T6234 E-Rate M ultiplexer also encodes and decodes HDB3 zero suppression line coding used on E l, E2 , and E3 signals. The coder and decoder input/output pins are externally accessible, allow ing either HDB3 or N RZ (non-return-to-zero) I , SX T 6234 can also function as a stand alone five-channel HDB3 transcoder. E1/ E2 M ultiplexer (2/8


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PDF SXT6234 T6234 S-T6234-0496-5K HD b3c 11DB3 DLC12 mc 3375 SXT6234QC XT6234
C55D

Abstract:
Text: he N R Z data is sent to a tributary o f th e E -R ate M ultiplexer, stage E2 /E3. 1. If the HDB3 , ITU or for proprietary use. Five independent HDB3 C O D E C s allow M ultiplexer I/O in either H D B3 or N R Z form ats. T he SX T6234 can also function as a stand alone five-channel HDB3 transcoder , ultiplexing four E l channels into an E2 fram e; and the G.751 recom m endation for m ultiplexing four E2 , suppression line coding used on E l, E2 , and E3 signals. T he coder and decoder input/ output pins are


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PDF SXT6234 T6234 DS-SXT6234-0296-1K C55D DLDP02 I2864 PV 1153 z04 e3
HD b3c

Abstract:
Text: ): G.742 recommendation for multiplexing four E l channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 chan­ nels into an E3 frame. The SXT6234 E-Rate Multiplexer also encodes and decodes H D B3 zero suppression line coding used on E l, E2 , and E3 signals. The coder and , D B3 or N R Z formats. The SXT6234 can also function as a stand alone five-channel HDB3 transcoder. Applications NOTE • E1/ E2 Multiplexer (2/8 Mbit/s) • E2 /E3 Multiplexer (8/34 Mbit/s) The SXT6234 w


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PDF SXT6234 SXT6234 HD b3c
EFB7446

Abstract:
Text: - input E2 16 Receive HDB3 + input IN 5 Inhibition input BE 6 Transmission Binary input BB 8 Binary loop input HE 7 Transmission clock input HRG 14 Regenerated clock input SI 3 Transmission HDB3 , voltage ±5 V. • Low power CMOS. BLOCK DIAGRAM BINARY DATA- INHIBITION . TRANSMISSION CODER HDB3 + - HDB3 - _ SAMPLING CLOCK BINARY LOOPING - RECEPTION |,2|-DECODER REGENERATED CLOCK BINARY DATA , SUFFIX PLASTIC PACKAGE PIN ASSIGNMENT VDD C 3 E2 HD C 2 15 3 El S1 C 3 14 3 HRG S2 C 4 13 D ER


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PDF EFB7446 CB-79 EFB7446 E2 hdb3 HDB3 HDB3 E2 binary coder E1 HDB3 HDB3 coding Thomson ceramic capacitor
1993 - G753

Abstract:
Text: .753 (34368 kbit/s) · Line side interface: - Rail or NRZ · HDB3 codec for rail I/O The E2 /E3F can be , is clocked into the E2 /E3F on negative transitions of the clock signal RCK/RCKL. The HDB3 codec for , Leased Circuits. An optional HDB3 codec is provided for the two CCITT line rates. TXC-21037, E2 /E3F-MRT , E2 /E3F Device 8-, 34 Mbit/s Framer TXC-03701 DATA SHEET FEATURES DESCRIPTION The E2 /E3 Framer ( E2 /E3F) is a CMOS VLSI device that provides the functions needed to frame a wideband payload to


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PDF TXC-03701 G753 g745 E2 hdb3 txc-21037
2001 - Not Available

Abstract:
Text: ® MT90732 CMOS E2 /E3 Framer ( E2 /E3F) Advance Information Features · Framer for CCITT , side interface - Dual rail or NRZ HDB3 codec for dual rail I/O Terminal side interface - , +85°C Description The MT90732 E2 /E3 Framer ( E2 /E3F) is a CMOS VLSI device that provides the , .753. The E2 /E3 Framer interfaces to line circuitry with either dual rail or NRZ signals. On the terminal , without a microprocessor. When interfaced with a microprocessor, the E2 /E3 Framer provides an 8byte memory


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PDF MT90732 MT90732AP
2001 - HDB3 E2

Abstract:
Text: MT90732 CMOS E2 /E3 Framer ( E2 /E3F) ® Advance Information Features · · · · · · , .751 (34368 kbit/s) - G.753 (34368 kbit/s) Line side interface - Dual rail or NRZ HDB3 codec for dual rail , 68 Pin PLCC -40°C to +85°C Description The MT90732 E2 /E3 Framer ( E2 /E3F) is a CMOS VLSI device , . G.742, G.745, G.751, or G.753. The E2 /E3 Framer interfaces to line circuitry with either dual rail , E2 /E3 Framer provides an 8byte memory map for control, performance counters and alarm status. The


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PDF MT90732 MT90732AP MT90732 753all HDB3 E2 nrz to hdb3 E2 hdb3 g745 HDB3 to nrz e2 MT90732AP
1996 - e2 framer g742

Abstract:
Text: http://products.zarlink.com/obsolete_products/ ® MT90732 CMOS E2 /E3 Framer ( E2 /E3F) Advance , .751 (34368 kbit/s) - G.753 (34368 kbit/s) Line side interface - Dual rail or NRZ HDB3 codec for dual rail I/O , MT90732AP 68 Pin PLCC -40°C to +85°C Description The MT90732 E2 /E3 Framer ( E2 /E3F) is a CMOS VLSI device , .742, G.745, G.751, or G.753. The E2 /E3 Framer interfaces to line circuitry with either dual rail or NRZ , be operated with or without a microprocessor. When interfaced with a microprocessor, the E2 /E3 Framer


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PDF MT90732 MT90732AP e2 framer g742
XT305

Abstract:
Text: IT T); G .742 recom m endation for m ultiplexing four E l channels into an E2 fram e; and the G.751 recom m endation for m ultiplexing four E2 channels into an E3 fram e. T he SX T6234 E -R ate M ultiplexer also encodes and d ecodes H DB3 zero suppression line coding used on E l, E2 , and E3 signals. T he , or for p ro p ri etary use. Five independent HDB3 C O D E C s allow M ultiplexer I/O in either H D B , Clocks Loss Of Signal (LOS) Service Channels / AIS HDB3 Data input Clock 4 Tributary NRZ Data Inputs 4


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PDF SXT6234 T6234 XT305
G753

Abstract:
Text: 0 Features · M ITEL CMOS MT90732 E2 /E3 Framer ( E2 /E3F) Advance Information , or NRZ HDB3 codec for dual rail I/O Terminal side interface - Nibble-parallel - Bit-serial Transmit , rdering Info rm a tio n MT90732AP 68 Pin PLCC -40°C to +85°C D escrip tion The MT90732 E2 /E3 Framer ( E2 /E3F) is a CMOS VLSI device that provides the functions needed to frame a wideband payload to one of four CCITT Recommendations. G.742, G.745, G.751, or G.753. The E2 /E3 Framer interfaces to line


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PDF MT90732 MT90732AP G753
1995 - e2 framer g742

Abstract:
Text: MT90732 CMOS E2 /E3 Framer ( E2 /E3F) ® Advance Information Features ISSUE 1 · , kbit/s) - G.753 (34368 kbit/s) Line side interface · - Dual rail or NRZ HDB3 codec for dual , +85°C Description · · Microprocessor or control leads · The MT90732 E2 /E3 Framer ( E2 /E3F , CCITT Recommendations. G.742, G.745, G.751, or G.753. The E2 /E3 Framer interfaces to line circuitry , interfaced with a microprocessor, the E2 /E3 Framer provides an 8byte memory map for control, performance


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PDF MT90732 MT90732AP MT90732 e2 framer g742 HDB3 E2 E2 liu multiplexing e2 frame e3 E2 hdb3 G753 HDB3 to nrz MT90732AP
1996 - 8448 clock

Abstract:
Text: MT90732 CMOS E2 /E3 Framer ( E2 /E3F) ® Advance Information Features · · · · · · , .751 (34368 kbit/s) - G.753 (34368 kbit/s) Line side interface - Dual rail or NRZ HDB3 codec for dual rail , 68 Pin PLCC -40°C to +85°C Description The MT90732 E2 /E3 Framer ( E2 /E3F) is a CMOS VLSI device , . G.742, G.745, G.751, or G.753. The E2 /E3 Framer interfaces to line circuitry with either dual rail , E2 /E3 Framer provides an 8byte memory map for control, performance counters and alarm status. The


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PDF MT90732 MT90732AP MT90732 753Overhead 8448 clock MT90732AP multiplexing e2 frame e3
2002 - 8448 clock

Abstract:
Text: Circuits. For 8448 and 34368 kbit/s operation, the MRT provides a selectable HDB3 codec. · AGC and , clock alarms · Selectable HDB3 encoder/decoder · Two loopbacks: - Receive to transmit - Transmit to , NRZ interface, HDB3 error rate monitor, alarm detection, and AIS generators. Testing capability is , MRT Transmit Line Signal 6-, 8-, 34- Mbit/s Multiplexer and/or Baseband I/O TXC-03701 E2 , Device ( E2 /E3F) · TXC-03702 6 Mbit/s Framer VLSI Device (JT2F) · TXC-06125 Bit Error Rate


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PDF TXC-02050C TXC-06125 TXC-02050 TXC-02050C-MC 8448 clock HDB3 E2 TXC-03701 HDB3 TXC-06125 HDB3 to nrz NTT encoder chip TranSwitch TXC-02050 TXC-02050C
Not Available

Abstract:
Text: reference generator is provided. Line side interface: - Rail or NRZ HDB3 codec for rail I/O The E2 , clocked out of the E2 /E3F on positive tran­ sitions of the clock signal TCK/TCKL. The HDB3 codec for , . An optional HDB3 codec is provided for the two CCITT line rates. TXC-21037, E2 /E3F-MRT Evaluation , E2 /E3F Device 8-, 34 Mbit/s Framer TXC-03701 v DATA SHEET W FEATURES DESCRIPTION , ) - G.753 (34368 kbit/s) = The E2 /E3 Framer ( E2 /E3F) is a CMOS VLSI device that provides the


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PDF TXC-03701
IESS-308/309

Abstract:
Text: .703 E1 G.703 T2 (DSX2) G.703 E2 ITU V.35 RS-422/449 Plesiochronous Buffer Size Centering , Mbps or 2.048 Mbps, G.732/733 AMI or B8ZS for T1 and HDB3 for E1 D4, ESF, or SLC-96 for T1 and PCM30 , ), E1 (G.703), and E2 (G.703) 1.544 Mbps, 100 Ohm balanced, AMI and B8ZS 2.048 Mbps, 75 Ohm unbalanced & 120 Ohm balanced , HDB3 6.312 Mbps, 75 Ohm unbalanced & 110 Ohm balanced, HDB3 and B6ZS 8.448 Mbps, 75 Ohm BNC, unbalanced, HDB3 Differential, Clock and Data only All Rates, Differential, Clock


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PDF DMD15 DMD15 BPSK/QPSK/8PSK/16 IESS-308/309 IESS-308 standard iess 308 viterbi IESS-308/309 IESS-308 sCRAMBLER IESS-308 code scrambler satellite v.35 IESS-308 G703
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