The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC2452CDDB#TRPBF Linear Technology LTC2452 - Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
LTC2452CDDB#PBF Linear Technology LTC2452 - Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
LTC2452CDDB#TRMPBF Linear Technology LTC2452 - Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C
LTC2452IDDB#TRPBF Linear Technology LTC2452 - Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
LTC1960CG#TR Linear Technology LTC1960 - Dual Battery Charger/ Selector with SPI Interface; Package: SSOP; Pins: 36; Temperature Range: 0°C to 70°C
LTC2452IDDB#TRMPBF Linear Technology LTC2452 - Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C

DesignWare SPI Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - vhdl coding for pipeline

Abstract: verilog code of 2 bit comparator verilog code for 4 bit ripple COUNTER RAM32X32 structural vhdl code for ripple counter
Text: . . . . . DesignWare Module Coding . . . . . . . . . . . . Operating Conditions . . . . . . . . , Actel-Synopsys Design Considerations . . . . . Compiling Designs with DesignWare Components . . Translating , . . . . . . . . . . . . . . . . 87 87 91 92 92 93 94 B DesignWare Library Information . . . . . . . . . . . . 97 DesignWare DesignWare DesignWare DesignWare Library Library Library Library , DesignWare Library Counters . . DesignWare Library Incrementer . DesignWare Library Decrementer. Improving


Original
PDF
2001 - verilog code for Modified Booth algorithm

Abstract: 8 bit booth multiplier vhdl code Booth algorithm using verilog booth multiplier code in vhdl structural vhdl code for ripple counter vhdl code for Booth multiplier 8 bit carry select adder verilog code verilog code for 16 bit carry select adder
Text: . . . . . DesignWare Module Coding . . . . . . . . . . . . Operating Conditions . . . . . . . . , Actel-Synopsys Design Considerations . . . . . Compiling Designs with DesignWare Components . . Translating , . . . . . . . . . . . . . . . . 89 89 93 94 94 95 96 B DesignWare Library Information . . . . . . . . . . . . 99 DesignWare DesignWare DesignWare DesignWare Library Library Library Library , DesignWare Library Counters . . . . DesignWare Library Incrementer . . . DesignWare Library Decrementer. . .


Original
PDF
1998 - DW01 pinout

Abstract: vhdl code for full subtractor full subtractor implementation using 4*1 multiplexer 16 bit carry select adder verilog code
Text: Machine Design . . . . . . . . . . . . . . . . . 24 DesignWare Module Coding . . . . . . . . . . . . . . . , Considerations . . . Compiling Designs with DesignWare Components Translating Designs from Other Technologies . . , . . . . . . . . 87 87 91 92 92 93 94 B DesignWare Library Information . . . . . . . . . . . . 97 DesignWare DesignWare DesignWare DesignWare Library Library Library Library Description . Adders . . . , . . . . . . . . . . . . 97 . 98 . 99 . 100 iv Table of Contents DesignWare Library


Original
PDF
1997 - DesignWare

Abstract: actel act1 family 3265DX RH1020 RH1280
Text: instantiated in VHDL and Verilog. Note: FIFO and RAM components are not available in the DesignWare libraries for this release. · Higher performance DesignWare library adder and subtractor macros are included , analysis has been improved. · Behavioral simulation models of the DesignWare library counters are , change any settings. You do not have to modify the actsetup.scr file. Regenerating DesignWare , , update_all_dw.fpga.shell, is needed to regenerate the DesignWare libraries. The script is available in the /pub directory


Original
PDF 1200XL LBR-29) DesignWare actel act1 family 3265DX RH1020 RH1280
2002 - FD1S3DX

Abstract: BTZ12 msc sdf A-18 VHDL program 4-bit adder FD1S3IX
Text: Analyzer, Design Compiler, DesignWare , DesignWare Developer, FPGA Compiler, FPGA Express, HDL Compiler , INSTALLATION OF ORCA/SYNOPSYS DESIGNWARE LIBRARIES . 6 ORCA MACRO LIBRARY , Series 3/4 LUT Libraries 50 Designing with ORCA2A (Series 3/4) DesignWare Library .52 Index , DesignWareTM Libraries Directory. Also see the section INSTALLATION OF ORCA/SYNOPSYS DESIGNWARE LIBRARIES , /Synopsys Version 1998.08 DesignWare Libraries Directory. Also see the section INSTALLATION OF ORCA


Original
PDF 1-800-LATTICE FD1S3DX BTZ12 msc sdf A-18 VHDL program 4-bit adder FD1S3IX
1995 - HP700

Abstract: verilog code for 8 bit carry look ahead adder carry save adder verilog program catalogue book
Text: . . . How to Verify the Library Version . . . . . . . . How to Reanalyze DesignWare Libraries . . , . . 67 Synthesis Libraries . . . . . . . . . . . . . . . . . . . 67 DesignWare Libraries . . . . . . . . . . . . . . . . . 75 6 How To Access DesignWare Modules . . . . . . 93 Adders . . . , . . . . . . . . . . . . . . . . Targeting the DesignWare Library Using VHDL . . Instantiating Soft , design an Actel FPGA using the Synopsys synthesis tools, Actel DesignWare libraries, preferred HDL


Original
PDF
1996 - OSC52

Abstract: xilinx xc3000 vq100 XC5200 XC4025 XC4000E XC4000A XC3100A XC3000 xact reference guide
Text: DesignWare and Simulation Libraries . Chapter 3 1-1 1-2 1-2 1-2 1-2 1-3 2-1 2-1 , DesignWare Library Must Be Analyzed. Path Reference To DesignWare Libraries Has Changed . , .synopsys_vss.setup file: XC5200 : $DS401/synopsys/libraries/sim/lib/xc5200 Analyzing the DesignWare and Simulation Libraries DS-401 provides DesignWare libraries that support X-BLOX functions in XC4000 and , libraries supporting VSS. You need to analyze the DS-401 DesignWare VHDL files after you install DS


Original
PDF
1997 - DesignWare

Abstract: synopsys QUICKLOGIC
Text: Interface Kit HIGHLIGHTS Supports both VHDL and Verilog HDL standards - enabling a complete high-level design methodology. Supports DesignWare for optimal area and speed implementations of adders and , performance. DesignWare , a term Synopsys uses to describe a set of technology-specific libraries (synthetic , DesignWare libraries are based on QuickLogic-optimized macrofunctions, allowing the synthesis tool to take , VHDL Synthesis Library Simulation Library Synopsys VHDL System Simulator DesignWare


Original
PDF
1995 - structural vhdl code for ripple counter

Abstract: vhdl projects abstract and coding voicemail controller vhdl code for Booth multiplier vhdl program for simple booth multiplier 8 bit carry select adder verilog codes vhdl code for 4 bit updown counter verilog code for fixed point adder VHDL code for 8 bit ripple carry adder vhdl codes for Return to Zero encoder in fpga
Text: .44 DesignWare , is generally technology-independent, and uses the DesignWare behavioral operators and standard VHDL , Techniques discusses VHDL coding style and shows how to use the DesignWare and instantiation capabilities of , .synopsys_dc.setup configuration file specifies the Altera technology you will use, whether you are using DesignWare , ) If DesignWare was used when Synopsys processed the design, ensure that the global project logic


Original
PDF
2002 - Not Available

Abstract: No abstract text available
Text: Xilinx vendor Translator options tab. Synopsys full-chip retiming optimizes performance of DesignWare , , Virtex-II, and Virtex-II Pro families of devices. DesignWare Foundation IP Library ASIC designers save design time by reusing components from the Synopsys DesignWare Foundation IP library. Although some , to prototype an ASIC or SOC. For a prototype, FCII's ability to implement the DesignWare components


Original
PDF
1999 - quicklogic

Abstract: DesignWare
Text: Interface Kit HIGHLIGHTS Supports both VHDL and Verilog HDL standards - enabling a complete high-level design methodology. Supports DesignWare for optimal area and speed implementations of adders and , predictions. DesignWareTM support ensures optimal results for area and performance. DesignWare , a term , , adders, and subtractors into area and speed efficient implementations. The DesignWare libraries are , VHDL Synthesis Library Simulation Library Synopsys VHDL System Simulator DesignWare


Original
PDF
1995 - HP700

Abstract: 1N201 SIGNAL PATH designer
Text: Simulation of DesignWare Counters Using Library Cell DLE . . . . . . . . . . . . Netlist Syntax . . . . . . , VHDL System Simulator Core Programs manual describes how to run the VSS library. The DesignWare Databook descrives the Synopsys DesignWare library modules. The DesignWare User's Guide explains how to use DesignWare components. v Introduction System Requirements The following lists the , , optimize the design targeting the synthesis and DesignWare libraries. After optimizing your design, the


Original
PDF HP700TM HP700 1N201 SIGNAL PATH designer
1999 - DesignWare

Abstract: asic design flow FPGA
Text: Design Compiler shell scripts. l Outputs Synopsys .db database files. l Support for DesignWare , million-gate designs. Third, you can now make use of the DesignWare Foundation library. DesignWare , scripting, DesignWare IP libraries, and a proven synthesis product that leverages your existing Figure 4


Original
PDF
1995 - CY3146

Abstract: features of verilog 1995 Warp Cypress Hewlett Packard
Text: Cypress CPLD. Utilize Cypress DesignWare and Technology libraries. Simulation Post-Synthesis , Solaris are trademarks of Sun Microsystems Corporation. Design Compiler, DesignWare , FPGA Compiler, and , Cypress DesignWare and Technology libraries. Simulation Post-Synthesis Simulation Simulate your , trademarks of Sun Microsystems Corporation. Design Compiler, DesignWare , FPGA Compiler, and VSS are


Original
PDF CY3146 FLASH370iTM CY3146 FLASH370i, features of verilog 1995 Warp Cypress Hewlett Packard
2002 - Not Available

Abstract: No abstract text available
Text: Translator options tab. Synopsys full-chip retiming optimizes performance of DesignWare Foundation all , Virtex-II PRO families of devices. DesignWare Foundation IP Library ASIC designers save design time by reusing components from the Synopsys DesignWare Foundation IP library. Although some components in the , SOC. For a prototype, FCII's ability to implement the DesignWare components in the FPGA provides


Original
PDF
1996 - full adder 7483

Abstract: 8count macrofunction 81MUX DW03D Altera 8count FLEX10K vhdl code for 8-bit serial adder Altera flex10k "serial adder" 7483 applications 7483 logic gates
Text: -5_fpga.db max5000.db max5000_fpga.db DesignWare Setup To use the DesignWare interface, you must add lines to , Synopsys & MAX+PLUS II Software Interface Guide Table 2. DesignWare Interface Lines to Be Added to the , Synthetic Library FLEX 10K Technology Library The DesignWare interface synthesizes FLEX 8000 and FLEX , interface guide are written in VHDL. However, you can also use the DesignWare interface for FLEX 8000 and , Interface Guide Updating DesignWare Libraries Altera provides DesignWare libraries that are pre-compiled


Original
PDF System/6000 full adder 7483 8count macrofunction 81MUX DW03D Altera 8count FLEX10K vhdl code for 8-bit serial adder Altera flex10k "serial adder" 7483 applications 7483 logic gates
1995 - and or

Abstract: CY3146
Text: FPGA Comiler for any Cypress CPLD. Utilize Cypress DesignWare and Technology libraries. Simulation , Corporation. SunOS and Solaris are trademarks of Sun Microsystems Corporation. Design Compiler, DesignWare


Original
PDF CY3146 FLASH370iTM CY3146 FLASH370i, and or
1995 - XC2018 PC84

Abstract: DS401 XC3042 pc84 CORE i3 ARCHITECTURE CORE i3 INTERNAL ARCHITECTURE XC3020 "Tape drive" xc4005 pg156 XC7000 HP700
Text: . 28 Analyzing the DesignWare and Simulation Libraries , . 33 X-BLOX DesignWare Library Must Be Analyzed , DesignWare library is included in the synthetic library string. If you do not want to use this default, delete the X-BLOX DesignWare information from the synthetic library string. June 1995 5 , DesignWare and Simulation Libraries DS-401 provides DesignWare libraries that support X-BLOX functions in


Original
PDF
1997 - bdr 551

Abstract: 32X8 sram DesignWare verification plan e language
Text: DesignWare Counter (Figure 12) Section 2: Efficient Implementation · Resource Sharing (Area versus Timing , clock reset DesignWare Counter ENTITY counter IS PORT ( data : IN std_logic_vector(9 downto 0 , > reset, clock => clk ); END impl; Figure 12 · DesignWare Counter a b + sum c d + , functions for logic modules. · Adapting Synopsys DesignWare standards to implement data-path and , generator (ACTgen) into the Synopsys DesignWare library. Actel has fully supported the existing


Original
PDF
2000 - 8x4 multiplexor

Abstract: m3189 A500K VHDL vhdl code of ripple carry adder verilog code pipeline ripple carry adder verilog code for carry look ahead adder signal path designer
Text: . . . . . . . . . . 67 iv List of Figures Synopsys Design Compiler Design Flow Designware Basic Adders - Area . . . . Designware Basic Adders - Timing . . . Designware Foundation Adders - Area . Designware Foundation Adders - Timing Actel Designware Adders - Area . . . . Actel Designware , Actel ProASIC DesignWare libraries. Note: In rare instances, you might see DesignWare cells create , recommends that you use either the Synopsys foundation or Actel supplied DesignWare in all designs. 16


Original
PDF
1996 - DW03D

Abstract: full adder 7483 8count 8count macrofunction VHDL program 4-bit adder vhdl code for carry select adder FLEX10K equivalent a_8fadd 8fadd FLEX10K
Text: max7000_fpga.db MAX 5000 & Classic devices max5000.db max5000_fpga.db DesignWare Setup To use the DesignWare interface, you must add the following lines to your .synopsys_dc.setup configuration file , flex10k_fpga.sldb FLEX 10K Technology Library flex10k.db flex10k_fpga.db Library The DesignWare , DesignWare interface for FLEX 8000 and FLEX 10K devices with Verilog HDL. Updating DesignWare Libraries Altera provides DesignWare libraries that are pre-compiled for the current version of Synopsys. See


Original
PDF System/6000 industr29 DW03D full adder 7483 8count 8count macrofunction VHDL program 4-bit adder vhdl code for carry select adder FLEX10K equivalent a_8fadd 8fadd FLEX10K
2003 - DesignWare SPI

Abstract: canon 7d designware i2c AN2415 SPS 13002
Text: Standard System I/O GPIO Connectivity MMC/SD CPU Complex Memory Stick® Host Controller ARM9TDMITM SPI 1 and SPI 2 UART 1 UART 2 SSI/I2S I2C USB Device AIPI 2 DMAC (11 Chnl) EIM & SDRAMC Bus Control Human , for common electrode driving signal preparation (Sharp panel dedicated signal). SPI 1 and 2 SPI1_MOSI , alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the , in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MXL


Original
PDF MC9328MXL/D MC9328MXL KMC9328MXLVF15 KMC9328MXLVF20 KMC9328MXLVH15 KMC9328MXLVH20 MC9328MXLVF15 MC9328MXLVF20 MC9328MXLVH15 MC9328MXLVH20 DesignWare SPI canon 7d designware i2c AN2415 SPS 13002
1996 - DesignWare

Abstract: BAD02 DS401 XC4000 XC4000E
Text: reference to the XBLOX DesignWare Library. An example .synopsys_dc.setup file is shown below. The target , _4000e.sldb standard.sldb} The reference to the XC4000E XBLOX DesignWare library is differentiated from the XC4000


Original
PDF
1995 - TRANSISTOR REPLACEMENT GUIDE

Abstract: 3195A verilog hdl code for parity generator xc3000 xact 3000a7 vhdl code for 8-bit parity checker CMOS 4002 X4897 XC4000A vhdl code for 8 bit ODD parity generator
Text: . Modifying the DesignWare Library Search Path. Using Synlibs with the FPGA Compiler , . Modifying the DesignWare Library Search Path. Using Synlibs with the Design , . Increasing Performance with the GSR Net. Using the X-BLOX DesignWare , . Using the X-BLOX DesignWare Library. HDL Operators Using , source X-BLOX DesignWare files were placed in this directory during installation. This directory should


Original
PDF
1998 - vhdl

Abstract: verilog
Text: Synthesis DesignWare Library Timing Simulation Flow COREGen VHDL Verilog 3rd Party SDF


Original
PDF X8441 vhdl verilog
Supplyframe Tracking Pixel