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Part Manufacturer Description Datasheet Download Buy Part
LTC2461IMS#TRPBF Linear Technology LTC2461 - Ultra-Tiny, 16-Bit I2C Delta Sigma ADCs with 10ppm/C Max Precision Reference; Package: MSOP; Pins: 12; Temperature Range: -40°C to 85°C
LTC2656BCFE-H16#TRPBF Linear Technology LTC2656 - Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference; Package: TSSOP; Pins: 20; Temperature Range: 0°C to 70°C
LTC2656BIFE-L16#TRPBF Linear Technology LTC2656 - Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
LTC2656CUFD-H12#TRPBF Linear Technology LTC2656 - Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference; Package: QFN; Pins: 20; Temperature Range: 0°C to 70°C
LTC2656IUFD-L12#TRPBF Linear Technology LTC2656 - Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C
LTC2754BIUKG-16#TRPBF Linear Technology LTC2754-12 - Quad 12-/16-Bit SoftSpan IOUT DACs; Package: QFN; Pins: 52; Temperature Range: -40°C to 85°C

Decoder 5 to 32 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2011 - quadrature decoder 4X

Abstract: rotary encoder mouse return to zero decoder psoc example projects 5 to 32 decoder
Text: the cyfitter.h file. Document Number: 001-69402 Rev. *A Page 5 of 32 Quadrature Decoder , General Description The Quadrature Decoder (QuadDec) Component gives you the ability to count transitions , per rotation. When to Use a Quadrature Decoder A quadrature decoder is used to decode the output , ISR is used. To work properly with the 32 -bit counter, interrupts must be enabled. You can add ISR , Number: 001-69402 Rev. *A Page 3 of 32 Quadrature Decoder (QuadDec) PSoC® CreatorTM Component


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2004 - 27mhz remote control transmitter circuit

Abstract: PAL to ITU-R BT.601/656 Decoder Hsync Vsync analog to digital convert ST20 TOOLSET cvbs to lcd decoder digital cvbs encoder 640 480 ac3 downmix decoder 33io H720 ae5 sony
Text: Plane 5th still picture plane available in MPEG video decoder OSD, used for MHP or MHEG- 5 , Letterbox and 4:3 to 16:9 format conversion with programmable 5 -segment Panoramic mode Picture Structure , product now in development or undergoing evaluation. Details are subject to change without notice. 1/ 32 , Diagnostic Controller Interrupt Controller MPEG 2 Video Decoder Slave Controller ST20 32 -bit CPU , . 5 1.2.1 MPEG Video Decoder


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PDF STD0550 10bit 50/60-Hz 32-bit 32-bit, 27mhz remote control transmitter circuit PAL to ITU-R BT.601/656 Decoder Hsync Vsync analog to digital convert ST20 TOOLSET cvbs to lcd decoder digital cvbs encoder 640 480 ac3 downmix decoder 33io H720 ae5 sony
2003 - 5 to 32 decoder

Abstract: 1024-pulse 5 to 32 decoder circuit quadrature decoder Quadrature Decoder Interface ICs MPC500 AN2511 decoder and encoder
Text: 6 5 0 1 2 3 4 5 6 PC_VS_ADDR 7 32 -bit Linear Quadrature Decoder TPU Function Set (32LQD , Freescale Semiconductor, Inc. Application Note AN2511/D Rev. 0, 5 /2003 32 -bit Linear Quadrature , . Functional Overview 32 -bit Linear Quadrature Decoder (32LQD) TPU Function Set is useful for decoding , functions: · 32 -bit Linear Quadrature Decoder (32LQD) · Home Channel for 32 -bit Linear Quadrature Decoder (32LQD_Home) · Velocity Support for 32 -bit Linear Quadrature Decoder (32LQD_VS) The 32


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PDF AN2511/D 32-bit 32LQD) 5 to 32 decoder 1024-pulse 5 to 32 decoder circuit quadrature decoder Quadrature Decoder Interface ICs MPC500 AN2511 decoder and encoder
32LQD

Abstract: 5 to 32 decoder Quadrature Decoder Interface ICs 1024-pulse quadrature decoder MPC500
Text: Freescale Semiconductor, Inc. AN2511/D Rev. 0, 5 /2003 32 -bit Linear Quadrature Decoder TPU , initialization, the PC is set to a 32 -bit PC_init value entered by the CPU. 32 -bit Linear Quadrature Decoder , 32 -bit Linear Quadrature Decoder (32LQD) TPU Function Set is useful for decoding position, direction , : · 32 -bit Linear Quadrature Decoder (32LQD) · Home Channel for 32 -bit Linear Quadrature Decoder (32LQD_Home) · Velocity Support for 32 -bit Linear Quadrature Decoder (32LQD_VS) The 32


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PDF AN2511/D 32-bit 32LQD) 32LQD 5 to 32 decoder Quadrature Decoder Interface ICs 1024-pulse quadrature decoder MPC500
2010 - psoc full projects

Abstract: control of motor using psoc quadrature encoder 4X psoc projects
Text: ) General Description The Quadrature Decoder (QuadDec) component provides the ability to count transitions , rotation. When to Use a Quadrature Decoder A Quadrature Decoder is used to decode the output of a , Setup Drag a Quadrature Decoder component onto your design and double-click it to open the Configure , resource usage. For this target, an additional ISR is used. To work properly with the 32 -bit counter , Quadrature Decoder (QuadDec) Enable Glitch Filtering Tab This tab contains a field to enable/disable


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1997 - r02101

Abstract: 433MHz saw Based Transmitter Schematic and PCB HCS301 receivers 433MHz saw Based Transmitter Schematic and PCB La HCS301 pcb hcs200 220r 1 schematic diagram 110v ac motor speed controller SAW 433MHZ PCB BFR92A application note circuit diagram of Garage Door Openers
Text: comprising the system. The software can be used to implement a stand alone decoder or integrate with full , the transmission, principally containing the encoder's serial number identifying it to a decoder , to identify the encoder to the decoder . Hopping Code The hopping code contains function , , this information can be used to check integrity of decryption operation by a decoder . If known , the decoder to check whether the information has been decrypted correctly. 12 bits (including


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PDF AN662 PIC16C56 HCS200, HCS300, HCS301, HCS360, HCS361 DS00662A-page r02101 433MHz saw Based Transmitter Schematic and PCB HCS301 receivers 433MHz saw Based Transmitter Schematic and PCB La HCS301 pcb hcs200 220r 1 schematic diagram 110v ac motor speed controller SAW 433MHZ PCB BFR92A application note circuit diagram of Garage Door Openers
1997 - timing diagram for 8 to 3 decoder

Abstract: timing DIAGRAM OF ROM 4 Signal s ZiVA Decoder 5 to 32
Text: : 32 ] MCE ROM (64K x 16) MA[8:0] MA[21:9] MD[15:0] CE OE Figure 9-1 ZiVA Decoder to Memory , all of the information necessary to connect the ZiVA decoder to an extended data out (EDO) DRAM array , control signals required to access external EDO DRAMs and ROMs. 9.1.1 DRAM The ZiVA decoder 's DRAM , , with one additional 256K x 16 DRAM, the ZiVA decoder can interface to 20 Mbits. The decoder 's DRAM controller can support up to 32 Mbits of local DRAM; however, only 16 Mbits of DRAM are needed to read


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2012 - quadrature decoder 4X

Abstract: quadrature decoder
Text: General Description The Quadrature Decoder (QuadDec) Component gives you the ability to count transitions , per rotation. When to Use a Quadrature Decoder A quadrature decoder is used to decode the output , ISR is used. To work properly with the 32 -bit counter, interrupts must be enabled. You can add ISR , violations when the target device is a PSoC 5 . It is recommended to limit the BUS_CLK frequency to 36 MHz for PSoC 5 projects. Document Number: 001-79365 Rev. * Page 5 of 17 Quadrature Decoder (QuadDec


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2002 - 5 to 32 line decoder

Abstract: HCS500 HCS301 transmitter code hopping transmitter 24LC02 automotive transponder C316 D216 E116 F016
Text: controller device. The HCS500 operates over a wide voltage range of 3.0 volts to 5.5 volts. The decoder , data rate. The decoder contains sophisticated error checking algorithms to ensure only valid codes , input to the encryption algorithm and the output is 32 bits of encrypted information. This data will , referred to as the hopping portion of the code word. The 32 -bit hopping code is combined with the button , that allows the decoder to operate in conjunction with an HCS500 based transmitter. Section 3.0


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PDF HCS500 HCS500 D-81739 DS40153C-page 5 to 32 line decoder HCS301 transmitter code hopping transmitter 24LC02 automotive transponder C316 D216 E116 F016
HCTL-2022

Abstract: Decoder 5 to 32 single ic Quadrature Decoder Interface ICs HCTL-2032-SC quadrature encoder 4X quadrature decoder HCTL-2032-SCT HCTL-20XX-XX HCTL-2032 quadrature decoder ic
Text: intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2032 consists of 4x , to 100oC 32 -Pin PDIP, 32 -Pin SOIC Applications Interface Quadrature Incremental Encoders to , functions to a cost effective hardware solution. The HCTL-20XX-XX consists of a quadrature decoder logic, a , . The HCTL-2022 doesn't provide decoder output and cascade signals. Interfaces Encoder to , : -40°C to 100°C 32 -Pin PDIP, 32 -Pin SOIC, 20-Pin PDIP Applications · Interface Quadrature


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PDF HCTL-2032 HCTL-2032 HCTL2032 HCTL-2022 Decoder 5 to 32 single ic Quadrature Decoder Interface ICs HCTL-2032-SC quadrature encoder 4X quadrature decoder HCTL-2032-SCT HCTL-20XX-XX quadrature decoder ic
1997 - downmix 5.1 to 2 channel

Abstract: dolby digital decoder wola WOLA adaptive reference downmix WOLA reference block diagram of video cd player ac3 downmix decoder intel pentium MMX simd 1997
Text: 0 through AB 5 in Figure 2) contains various pieces of information that tell the decoder how to , compares favorably with floating-point based implementations. Typically Intel's decoder has about 5 to 10 , Laboratories has developed a stringent test suite to ensure that a certified decoder indeed provides high , uniformly through a Dolby Digital decoder is insufficient to pass the test suite. The challenge was to , implementer to increase the audio quality of the decoder while still providing a significant speedup over


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PDF AD-706862, S96/11283. 16-Bit 31-Bit downmix 5.1 to 2 channel dolby digital decoder wola WOLA adaptive reference downmix WOLA reference block diagram of video cd player ac3 downmix decoder intel pentium MMX simd 1997
1997 - avia

Abstract: Decoder 5 to 32
Text: decoder 's DRAM controller can support up to 32 Mbits of local DRAM; however, only 16 Mbits of DRAM are , [8:0] MDATA[60:48] MDATA[47: 32 ] MCE Figure 9-1 AViA Decoder to Memory Connection (16- and 20 , decoder outputs the column address of the first word to be read on MADDR. 5 . The decoder latches the , all of the information necessary to connect the AViA decoder to an extended data out (EDO) DRAM array , the control signals required to access external EDO DRAMs and SRAMs. 9.1.1 DRAM The AViA decoder


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1996 - E1 HDB3

Abstract: 16 line to 4 line coder multiplexer HDB3 AMI ENCODER DECODER HDB3 to nrz circuit diagram of 64-1 multiplexer Frame structure for Multiplexing of four E2 streams into E3 stream E1 AMI HDB3 decoder SXT6234 Frame structure for Multiplexing of four E1 streams into E2 stream HDB3 decoder
Text: = ± 5 %, GND = 0V. Figure 5 : HDB3 Encoder and Decoder Timing (Refer to Table 5 ) t cyc t pwh , input clocked on the rising edge of MHHDB3C. 45 MHHDB3C 48 DHDPI HDB3 Decoder # 5 Positive Data Input. HDB3 Decoder # 5 (High Speed) positive rail input clocked on the ri sing edge of DHHDB3C. 49 DHDNI HDB3 Decoder # 5 Negative Data Input. HDB3 Decoder # 5 (High Speed) positi ve rail input clocked on the ri sing edge of DHHDB3C. 50 DHHDB3C HDB3 Decoder # 5 Clock Input


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PDF SXT6234 SXT6234 E1 HDB3 16 line to 4 line coder multiplexer HDB3 AMI ENCODER DECODER HDB3 to nrz circuit diagram of 64-1 multiplexer Frame structure for Multiplexing of four E2 streams into E3 stream E1 AMI HDB3 decoder Frame structure for Multiplexing of four E1 streams into E2 stream HDB3 decoder
2005 - AHA4524A-031

Abstract: AHA4524A-031PTI Comtech Aha Corporation PB4524 R793 AHA4524 Turbo Decoder block diagram of 2 to 4 decoder interleaver AHA ecc
Text: deinterleaved before decoding. The decoder output is descrambled, and the CRC is computed to verify data , option to accept 4 bit parallel soft metric data symbols. The parallel decoder input is used to support , Programmable decoder input quantization for up to 4 bit wide soft metrics · Programmable iterations up to 255 , ASIC/DSP to block and prepare the Figure 2: data for the AHA4524 decoder . Data blocks are then , ENCODER/ DECODER The AHA4524 device is a single-chip Turbo Product Code (TPC) Forward Error Correction


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PDF AHA4524 AHA4524 AHA4524A-031 PB4524 AHA4524A-031PTI Comtech Aha Corporation R793 Turbo Decoder block diagram of 2 to 4 decoder interleaver AHA ecc
ls7474

Abstract: SN74HC390 pin DIAGRAM OF IC 74ls74 74ls74 timing setup hold IC 74LS74 74ls74 ic chip architecture of TMS320C10 74LS299 APPLICATIONS ci 74LS74 TMS320C10
Text: □ nc VccC 5 36 □ nc clkoutq 6 35 □ nc x1 □ 7 34 □ nc x2/clkinq 8 33 □ nc lion; 9 32 , 64 kbit/s PCM to 32 kbit/s ADPCM, or for the decoding from 32 kbit/s ADPCM to 64 kbit/s PCM. The same , advantage of using a single device to perform both the encoder and decoder functions. The TMS320SA32 thus , encoder and decoder . encoder The function of the encoder or transmitter, shown in Figure 1 (a), is to receive a 64 kbit/s PCM signal and transcode it to a 32 kbit/s ADPCM signal. This is accomplished by


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PDF TMS320SA32 165-mW 40-pin ls7474 SN74HC390 pin DIAGRAM OF IC 74ls74 74ls74 timing setup hold IC 74LS74 74ls74 ic chip architecture of TMS320C10 74LS299 APPLICATIONS ci 74LS74 TMS320C10
1999 - 24LC02

Abstract: HCS200 HCS300 HCS301 HCS360 HCS410 HCS500 circuit diagram of Garage Door Openers HCS301
Text: detection 7 RFIN 6 S_CLK 5 RFIN Stand-alone decoder chipset External EEPROM for , . Compatible Encoders The HCS500 operates over a wide voltage range of 3.0 volts to 5.5 volts. The decoder , data rate. The decoder contains sophisticated error checking algorithms to ensure only valid codes , serial number to form the code word transmitted to the receiver. FIGURE 1-2: HCS Decoder Overview , Microchip Technology Inc. HCS500 3.0 DECODER OPERATION 3.1 Learning a Transmitter to a


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PDF HCS500 67-bit 24LC02 HCS200 HCS300 HCS301 HCS360 HCS410 HCS500 circuit diagram of Garage Door Openers HCS301
2007 - 90S8535

Abstract: quadrature decoder 4X AV02-0096EN HCTL-2022 incremental optical encoder 5V ttl quadrature HCTL-2032 dy23 optical quadrature encoder 32bit Quadrature Decoder Interface ICs HCTL-2032-SC
Text: edges as explained in the Quadrature Decoder Section. All 32 bits of data are passed to the position , decoder , counter, and bus interface function. The HCTL-20XX-XX is designed to improve system performance , shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL , 8, 16, 24, or 32 -Bit Operating Modes Quadrature Decoder Output Signals, Up/Down and Count Cascade , /CMOS Compatible I/O Operating Temperature: -40°C to 100°C 32 -Pin PDIP, 32 -Pin SOIC, 20-Pin PDIP


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PDF HCTL-2032, HCTL-2032-SC, HCTL-2032-SCT, HCTL-2022 HCTL-20XX-XX HCTL-20XX-XX 32bit 32-PDIP 90S8535 quadrature decoder 4X AV02-0096EN HCTL-2022 incremental optical encoder 5V ttl quadrature HCTL-2032 dy23 optical quadrature encoder 32bit Quadrature Decoder Interface ICs HCTL-2032-SC
2010 - AHA4524A-031

Abstract: code of encoder and decoder in rs(255,239) serial parallel decoder AHA4524 8 TO 64 DECODER block diagram of 2 to 4 decoder
Text: deinterleaved before decoding. The decoder output is descrambled, and the CRC is computed to verify data , option to accept 4 bit parallel soft metric data symbols. The parallel decoder input is used to support , Figure 2: data for the AHA4524 decoder . Data blocks are then transferred to the AHA4524 for TPC , iter 1.E-08 TPC(64,57)^2, 32 iter 1.E-09 1.E-10 0 1 2 3 4 5 6 Eb/No (dB , / DECODER The AHA4524 device is a single-chip Turbo Product Code (TPC) Forward Error Correction (FEC


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PDF AHA4524 AHA4524 AHA4524A-031 PB4524 code of encoder and decoder in rs(255,239) serial parallel decoder 8 TO 64 DECODER block diagram of 2 to 4 decoder
2006 - HCTL-2022

Abstract: avago encoder quadrature decoder 4X avr processor SCHEMATIC circuit diagram optical quadrature decoder 32bit HCTL-2032-SC HCTL-2032-to-Atmel 5989-0060EN quadrature decoder
Text: edges as explained in the Quadrature Decoder Section. All 32 bits of data are passed to the position , functions to a cost effective hardware solution. The HCTL-20XX-XX consists of a quadrature decoder logic, a , 32 -Bit Operating Modes Quadrature Decoder Output Signals, Up/Down and Count Cascade Output Signals , I/O Operating Temperature: -40°C to 100°C 32 -Pin PDIP, 32 -Pin SOIC, 20-Pin PDIP Applications · , -2032 HCTL-2032-SC HCTL-2022 Description 32 -bit counter, dual axis, decoder and cascade outputs, index


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PDF HCTL-2032, HCTL-2032-SC, HCTL-2022 HCTL-20XX-XX HCTL20XX-XX 32-bit 32-PDIP HCTL-2022 avago encoder quadrature decoder 4X avr processor SCHEMATIC circuit diagram optical quadrature decoder 32bit HCTL-2032-SC HCTL-2032-to-Atmel 5989-0060EN quadrature decoder
1994 - Zilog Z80 instruction set

Abstract: the return of the native zilog z80 processor Z380 Z80 Programming manual Z80 CPU
Text: to 4 Gbytes (232) of memory addressing space, and 4G locations of I/O. It offers 16/ 32 , Appendix D and E. DC-8297-03 3-1 Z380TM USER'S MANUAL ZILOG 3.2 DECODER DIRECTIVES The Decoder Directive is not an instruction, but rather a directive to the instruction decoder . The instruction decoder may be directed to fetch an additional byte or word of immediate data or address with the , decoder to fetch additional byte(s) of address information or immediate data to extend the instruction


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PDF Z380TM Z380TM 16/32-bit DC-8297-03 Zilog Z80 instruction set the return of the native zilog z80 processor Z380 Z80 Programming manual Z80 CPU
2001 - hcs500

Abstract: No abstract text available
Text: controller device. The HCS500 operates over a wide voltage range of 3.0 volts to 5.5 volts. The decoder , data rate. The decoder contains sophisticated error checking algorithms to ensure only valid codes are , with every button press, hence, it is referred to as the code hopping portion of the code word. The 32 , word transmitted to the receiver. 1.3 HCS Decoder Overview Before a transmitter and receiver , Microchip Technology Inc. HCS500 3.0 3.1 DECODER OPERATION Learning a Transmitter to a Receiver


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PDF HCS500 67-bit DS40153B-page hcs500
2009 - CX24155

Abstract: QPSK Demodulator low cost qpsk modulator trident video processor decoder tv ir QPSK bpsk modulator mpeg demodulator nxp set-top box CX2415
Text: CX24152/ 5 MPEG-2 SD Decoder with Integrated QPSK Demodulator Highly Integrated, Cost Efficient , all the major subsystems required to implement the core system and decoder electronics of a DBS , High-performance 16 or 32 -bit unified memory controller architecture This includes an MPEG-2 A/V decoder (Dolby , CPU in the CX24152/ 5 offers up to 224 Dhrystone 2.1 MIPS at a 200MHz clock speed. This CPU platform , secure transactions between the STB smart card and the broadcaster service decoder . The CX24152/ 5 also


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PDF CX24152/5 32-bit ARM920 16KBh 256-level 4/8/16-bit 10044B CX24155 QPSK Demodulator low cost qpsk modulator trident video processor decoder tv ir QPSK bpsk modulator mpeg demodulator nxp set-top box CX2415
1984 - 32 QAM modulator demodulator matlab

Abstract: 16 QAM modulation matlab code scramble matlab TMS320 viterbi matlab dsp algorithms using tms320c50 for decrementing the number signal constellation diagram lookup Signal Path designer
Text: transformations from one delay state to another, along with their corresponding path states. 5 Figure 4. V. 32 , bps, either a 16-point or a 32 -point constellation can be used (see Figure 1). Obviously, 5 -bit-long symbols are required to map each point of a 32 -point constellation. 1 I and Q components are also referred to as X and Y in literature. Both notations are used interchangeably in this paper. 1 The V. 32 , the 32 -point constellation is used extensively to help decode the signals, the actual modulation


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PDF TMS320C5x 32 QAM modulator demodulator matlab 16 QAM modulation matlab code scramble matlab TMS320 viterbi matlab dsp algorithms using tms320c50 for decrementing the number signal constellation diagram lookup Signal Path designer
2003 - quadrature decoder 4X

Abstract: HCTL-2022 avr processor SCHEMATIC circuit diagram 2032-SC HCTL-2022 circuit HCTL-2032-SC incremental optical encoder 5V ttl 5989-0060EN hctl 2032 encoder counter quadrature shaft decoder
Text: the Quadrature Decoder Section. All 32 bits of data are passed to the position data latch. The , digital data input systems. It does this by shifting time intensive quadrature decoder functions to a , , 16, 24, or 32 -Bit Operating Modes · Quadrature Decoder Output Signals, Up/Down and Count · Cascade , ) · TTL/CMOS Compatible I/O · Operating Temperature: -40°C to 100°C · 32 -Pin PDIP, 32 -Pin SOIC, 20 , -2032 32 -bit counter, dual axis, decoder and cascade outputs, index channel support, A programmable count


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PDF HCTL-2032, HCTL-2032-SC, HCTL-2022 32-PDIP 32-SOIC 20-PDIP 5989-0060EN quadrature decoder 4X HCTL-2022 avr processor SCHEMATIC circuit diagram 2032-SC HCTL-2022 circuit HCTL-2032-SC incremental optical encoder 5V ttl 5989-0060EN hctl 2032 encoder counter quadrature shaft decoder
1997 - datasheet tca 786

Abstract: rf encoder and decoder HCS500 HCS200 transmitter HCS301 HCS300 HCS200 F016 24LC02 HCS410
Text: . Compatible Encoders The HCS500 operates over a wide voltage range of 3.0 volts to 5.5 volts. The decoder , data rate. The decoder contains sophisticated error checking algorithms to ensure only valid codes , serial number to form the code word transmitted to the receiver. FIGURE 1-2: HCS Decoder Overview , Microchip Technology Inc. HCS500 3.0 DECODER OPERATION 3.1 Learning a Transmitter to a , , consequently, can store up to seven transmitters. During the learn procedure, the decoder searches for an


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PDF HCS500 67-bit DS40153B-page datasheet tca 786 rf encoder and decoder HCS500 HCS200 transmitter HCS301 HCS300 HCS200 F016 24LC02 HCS410
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