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Part Manufacturer Description Datasheet Download Buy Part
LT2079I Linear Technology IC QUAD OP-AMP, 700 uV OFFSET-MAX, 0.2 MHz BAND WIDTH, PDSO14, 0.150 INCH, PLASTIC, SO-14, Operational Amplifier
UPS25510 GE Critical Power VH 700 TOWER/RACKMT LINE INTERAC
TPA721D Texas Instruments 700-mW Mono, Class-AB Audio Amplifier with Active High Shutdown 8-SOIC
INA128PAG4 Texas Instruments Precision, 130-dB CMRR, 700-µA, Low-Power, Instrumentation Amplifier 8-PDIP
TPA701DGN Texas Instruments 700-mW Mono, Class-AB Audio Amplifier 8-MSOP-PowerPAD -40 to 85
INA128U/2K5G4 Texas Instruments Precision, 130-dB CMRR, 700-µA, Low-Power, Instrumentation Amplifier 8-SOIC

DXR 700 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Diplexer

Abstract: No abstract text available
Text: SHIELDED DIPLEXER DXR 216 / DXR 334 DESCRIPTION · DXR 216: Diplexer with 2 inputs / 1 output, suitable for splitting or combining RF / 1st IFSAT. · DXR 334: Diplexer with 3 inputs / 1 output, suitable for incorporating QAM digital channels in analogue channels installations. TECHNICAL SPECIFICATIONS MODEL DXR 216 DXR 334 86245 86334 Number of inputs 2 3 Number of outputs 1 1 500 mA, max - Reference DC pass SAT IN-OUT SAT IN Input MHz 950 ÷ 2300


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2004 - diplexer

Abstract: saddle clamp DIPLEXER LGP21906 86245
Text: SHIELDED DIPLEXER DXR Series Shielded diplexer with saddle clamp connection. APPLICATION Suitable for digital or analogue TV installations. CHARACTERISTICS DXR 216: diplexer with 2 inputs/1 output, suitable for splitting or combining RF/1st IF SAT. DXR 334: diplexer with 3 inputs/1 output , MHz MHz MHz dB dB dB dB dB dB dB mm. kg. DXR 216 86245 1: RF (15 ÷ 862 MHz) 1: 1ª FI SAT (950 ÷ , ) 30 (1200 ÷ 2300 MHz) 115 x 110 x 47 0,95 DXR 334 86334 1: RF (15 ÷ 230 ; 470 ÷ 862 MHz) 1: HYP


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2005 - C2548

Abstract: TMS320C50 TLV2548 TLV2544 TLV1572 TLV1570 TLV1548 TLV1544 TLC2558 TLC2554
Text: operation of the serial port is supported by the following five 16-bit registers: DXR Data transmit register. Transmit data are written by the CPU into this register and then copied into the XSR. The DXR , are copied from the DXR into the XSR and sent to the data converter. RSR Receive shift register , , which are set by the CPU to configure the operation of the serial port. Data Bus DXR XINT XSR , writing transmit data to the DXR . Then the data are copied from the DXR into the XSR and clocked out to


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PDF TMS320C50) SLYT175 C2548 TMS320C50 TLV2548 TLV2544 TLV1572 TLV1570 TLV1548 TLV1544 TLC2558 TLC2554
TIMING DIAGRAM OF MCBSP and E1 interface

Abstract: P2E4 001C AC97 N-16 MCBSP EXAMPLE
Text: Compress Clock and frame sync generation and control Multichannel selection DRR DXR SPCR RCR XCR , receive register (DRR) and writes the data to be transmitted to the data transmit register ( DXR ). Data written to the DXR is shifted out to DX via the transmit shift register (XSR). Similarly, receive data on , register^ 8.2 018C 0004 0190 0004 DXR Data transmit tegister 8.2 018C 0008 0190 0008 SPCR Serial port , ready for data to: be written: to DXR . 8.3.2 RRST Receiver reset. This resets or enables the receiver


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1996 - TLC32046

Abstract: TMS320
Text: Register ( DXR ) before the secondary frame sync pulse goes low. If the TRANSMIT interrupt is used to control writes to the DSP DXR during AIC configuration, the XINT signal occurs approximately 15 (C26) or , occurs after the contents of the data register ( DXR ) are loaded into the SXR at the beginning of the , . There is a latency of approximately 10/17 instruction cycles (C26/C51) from XINT to writing to the DXR , idle lalk idle 0 020h IMR ;Enable transmit interrupt DXR AIC_SETUP ;Enable global


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PDF TMS320 TMS320C2x/C5x TMS320C2x TMS320C5x C26/C51 TLC32046
2001 - SAT Line Amplifier

Abstract: "SAT Line Amplifier" Diplexer "line AMPLIFIER" sat F connector
Text: 3 Packing dimensions mm 80 x 20 x 25 Kg 0,1 Weight Shielded Diplexer DXR 216 / DXR 334 DESCRIPTION · DXR 216: Diplexer with 2 inputs / 1 output, suitable for splitting or combining RF / 1st IF SAT. · DXR 334: Diplexer with 3 inputs / 1 output, suitable for incorporating QAM digital channels in analogue channels installations. TECHNICAL SPECIFICATIONS MODEL DXR 216 Reference DXR 334 86245 86334 Number of inputs 2 3 Number of outputs 1 1 500


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2007 - AC97

Abstract: ARM926EJ-S C6000 TMS320C6000 SPRUE25
Text: ). 44 3.2 Data Transmit Register ( DXR , . 34 Transmit Data Companding Format in DXR , ) . 44 Data Transmit Register ( DXR , . Data Transmit Register ( DXR ) Field Descriptions , DR DX CLKX CLKR FSX FSR RSR XSR RBR Expand DRR Compress DXR SPCR RCR


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PDF TMS320DM644x SPRUE29B AC97 ARM926EJ-S C6000 TMS320C6000 SPRUE25
1996 - xmtd

Abstract: TMS320
Text: registers (SPC, DXR , and DRR) are memory mapped, setting up the C5x serial port and reading and writing to , has been declared; data is read from the C5x serial-port receive register, DXR , as follows: #define DXR (volatile unsigned int *) 0x0021) aicPrimary._bitval.command = 0; /* Initialize lower 2 bits to 0 */ aicPrimary._intval = * DXR ; /* Read all 16 bits */ dataReceived = , ; /* Write data to upper 14 bits */ * DXR = aicPrimary._intval; /* Transmit all 16 bits */ In the previous


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PDF TMS320 TMS320C5x 0x0022, 0x0020) 0x0021) xmtd
1996 - D11OUT

Abstract: TMS320
Text: registers (SPC, DXR , and DRR) are memory mapped, setting up the C5x serial port and reading and writing to , has been declared; data is read from the C5x serial-port receive register, DXR , as follows: #define DXR (volatile unsigned int *) 0x0021) aicPrimary._bitval.command = 0; /* Initialize lower 2 bits to 0 */ aicPrimary._intval = * DXR ; /* Read all 16 bits */ dataReceived = , ; /* Write data to upper 14 bits */ * DXR = aicPrimary._intval; /* Transmit all 16 bits */ In the previous


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PDF TMS320 TMS320C5x 0x0022, 0x0020) 0x0021) D11OUT
1995 - LPC-10 52E

Abstract: FED-STD-1015 LPC-10-52E erskine dc motor drives TMS320 SPRU131 SPRU103 SPRU099 SPRU052 C209
Text: . . . . . . . . . . . . . . . 1-29 DXR Filling Process . . . . . . . . . . . . . . . . . . . . . . , control register (SPC), the data transmit register ( DXR ), and the data receive register (DRR). , Registers Description SPC Serial port control register DXR Data transmit register DRR , DR DXR (16) FSX Byte/Word Counter DX CLKR CLKX The SPC controls serial port operation; the functions of SPC bit fields are described in Figure 1­2. Transmit data is written to the DXR


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PDF TMS320C54x D425005 SPRU156 TMS320C54x LPC-10 52E FED-STD-1015 LPC-10-52E erskine dc motor drives TMS320 SPRU131 SPRU103 SPRU099 SPRU052 C209
1995 - LPC-10 52E

Abstract: FED-STD-1015 FED-STD-101 REAL TIME CONTROL OF DC MOTOR DRIVE USING SPEECH SPRU099 SPRU103 SPRU052 FSM04 C209 C203
Text: . . . . . . . . . . . . . . . 1-29 DXR Filling Process . . . . . . . . . . . . . . . . . . . . . . , control register (SPC), the data transmit register ( DXR ), and the data receive register (DRR). , Registers Description SPC Serial port control register DXR Data transmit register DRR , DR DXR (16) FSX Byte/Word Counter DX CLKR CLKX The SPC controls serial port operation; the functions of SPC bit fields are described in Figure 1­2. Transmit data is written to the DXR


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PDF TMS320C54x D425005 SPRU156 TMS320C54x 6000h, 0x6000 0009h, LPC-10 52E FED-STD-1015 FED-STD-101 REAL TIME CONTROL OF DC MOTOR DRIVE USING SPEECH SPRU099 SPRU103 SPRU052 FSM04 C209 C203
1995 - C203

Abstract: FED-STD-101 TMS320 SPRU131 SPRU103 SPRU099 SPRU052 SPRU011 C209 erskine dc motor drives
Text: . . . . . . . . . . . . . . . 1-29 DXR Filling Process . . . . . . . . . . . . . . . . . . . . . . , control register (SPC), the data transmit register ( DXR ), and the data receive register (DRR). , Description SPC Serial port control register DXR Data transmit register DRR Data receive , DXR (16) FSX Byte/Word Counter DX CLKR CLKX The SPC controls serial port operation; the functions of SPC bit fields are described in Figure 1­2. Transmit data is written to the DXR


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PDF TMS320C54x D425005 SPRU156 TMS320C54x C203 FED-STD-101 TMS320 SPRU131 SPRU103 SPRU099 SPRU052 SPRU011 C209 erskine dc motor drives
1995 - FED-STD-1015

Abstract: stl motor control 64 lead LPC-10 52E TMS320 SPRU131 SPRU103 SPRU099 SPRU052 SPRU011 C209
Text: . . . . . . . . . . . . . . . 1-29 DXR Filling Process . . . . . . . . . . . . . . . . . . . . . . , control register (SPC), the data transmit register ( DXR ), and the data receive register (DRR). , Registers Description SPC Serial port control register DXR Data transmit register DRR , DR DXR (16) FSX Byte/Word Counter DX CLKR CLKX The SPC controls serial port operation; the functions of SPC bit fields are described in Figure 1­2. Transmit data is written to the DXR


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PDF TMS320C54x D425005 SPRU156 TMS320C54x FED-STD-1015 stl motor control 64 lead LPC-10 52E TMS320 SPRU131 SPRU103 SPRU099 SPRU052 SPRU011 C209
1997 - instruction set of TMS320C50 DSP PROCESSOR

Abstract: instruction set tms320c50 TMS320C26 tms320c2x TMS320C50 tms320c50 application TMS320C50 specifications TLC32046 TMS320
Text: written to the DSP's Serial Port Transmit Register ( DXR ) before the secondary frame sync pulse goes low. If the TRANSMIT interrupt is used to control writes to the DSP DXR during AIC configuration, the , in the TMS320C50, XINT occurs after the contents of the data register ( DXR ) are loaded into the SXR , ) from XINT to writing to the DXR . 10 SPRA221 Example 1. TMS320C26 Program , to synchronize the sacl lalk idle lalk idle dint DXR AIC_SETUP ; TMS320C26 and AIC


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PDF TMS320 TMS320C2x/C5x SPRA221 instruction set of TMS320C50 DSP PROCESSOR instruction set tms320c50 TMS320C26 tms320c2x TMS320C50 tms320c50 application TMS320C50 specifications TLC32046
2004 - SPRU401

Abstract: mcbsp TMS320C6000 C6000 programming tms320c6000
Text: from DRR and writes to DXR , either the polled or interrupt method can be used. Contents 1 Design , transmission of data that is written in DXR . The contents of DXR are copied to the transmit shift register XSR , transmitted or shifted out of XSR on every transmit clock CLKX. New data can be written to DXR using either , Generation: The McBSP generates sync events to the EDMA to indicate that data is ready in DRR, or that DXR , programmed via the CPU, but the data registers DXR and DRR can be accessed either by the CPU or the EDMA


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PDF SPRA488C TMS320C6000 SPRU401 mcbsp C6000 programming tms320c6000
1999 - TIMING DIAGRAM OF INT R

Abstract: C6000 SPRU190 TMS320C6000 programming tms320c6000
Text: register ( DXR ), respectively, to handle the 48 bits of receive data and the 48 bits of transmit data , Element 3 Element 4 Element 5 Element 6 DXR to XSR Copy DXR to XSR Copy DXR to XSR Copy DXR to XSR Copy CLKR/X FSR/X DR/DX DXR to XSR Copy DXR to XSR Copy In this configuration , the DRR and six 8-bit writes to the DXR . When the McBSP is operating at maximum frequency, as shown , mentioned above would now require only two 24-bit reads of the DRR and two 24-bit writes to the DXR


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PDF SPRA551 TMS320C6000 16/24/32-bit 16-bit 32-bit TIMING DIAGRAM OF INT R C6000 SPRU190 programming tms320c6000
1997 - TMS320C5x

Abstract: xmtd TMS320
Text: , DXR , and DRR) are memory mapped, setting up the 'C5x serial port and reading and writing to the , 'C5x serial-port receive register, DXR , as follows: #define DXR (volatile unsigned int *) 0x0021) aicPrimary._bitval.command = 0 ; /* Initialize lower 2 bits to 0 */ aicPrimary._intval = * DXR ; /* Read all 16 bits , ) aicPrimary._bitval.data = xmitData ; /* Write data to upper 14 bits */ * DXR = aicPrimary._intval; /* Transmit all 16 bits */ In the previous two code segments, notice the alternative method used to access DXR and DRR


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PDF TMS320 TMS320C5x SPRA251 0x0020) 0x0021) xmtd
2004 - generator synchronization

Abstract: pulse code interval encoding using MCBSP SPRU580D P2E4 C6000 SPRU189 SPRU190 TMS320C6000 MCBSP EXAMPLE
Text: ( DXR ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , DXR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Companding of , . . . . . . . . . 88 Data Transmit Register ( DXR ) . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . 88 Data Transmit Register ( DXR ) Field Descriptions . . . , Expand DRR Compress DXR SPCR Clock and frame sync generation and control RCR XCR


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PDF TMS320C6000 SPRU580D generator synchronization pulse code interval encoding using MCBSP SPRU580D P2E4 C6000 SPRU189 SPRU190 MCBSP EXAMPLE
1997 - programming tms320c6000

Abstract: C6000 TMS320 TMS320C6000
Text: sync events. Alternatively, in cases where the CPU reads from DRR and writes to DXR , either the polled , transmitter section is responsible for the serial transmission of data that is written in DXR . The contents of DXR are copied to the transmit shift register XSR. The transfer starts as soon as the transmit , clock CLKX. New data can be written to DXR using either the CPU or the DMA. · Receiver: The data , DMA to indicate that data is ready in DRR or that DXR is ready for new data. They are read sync event


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PDF SPRA488 TMS320C6000 programming tms320c6000 C6000 TMS320
1997 - control register mean

Abstract: TMS320 TMS320C25
Text: ; RB,2 02h AIC_2ND AIC_CTR,2 ADDK CALL RET 0 DXR initialize TA' initialize TB , transmit data ; register ; wait for int 6,16 DXR ; ACC_hi requests 2nd XMIT DXR ; ACC_lo sets up registers DXR ; make sure word was sent Texas Instruments


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PDF TMS320 SPRA206 100nS) control register mean TMS320C25
2001 - mcbsp1 signals

Abstract: programming tms320c6000 mcbsp SPRU401 C6000 SPRU190 TMS320C6000
Text: , requires six reads of the data receive register (DRR) and six writes to the data transmit register ( DXR , /DX DXR to XSR Copy DXR to XSR Copy DXR to XSR Copy DXR to XSR Copy DXR to XSR Copy DXR to XSR Copy , -bit reads from the DRR and six 8-bit writes to the DXR . When the McBSP is operating at maximum frequency , and transmit data now requires only two 24-bit reads of the DRR and two 24-bit writes to the DXR , SPRA551A Element 1 (24 bits) Element 2 (24 bits) CLKR/X FSR/X DR/DX DXR to XSR Copy DXR to XSR


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PDF SPRA551A TMS320C6000 16/24/32-bit 16-bit 32-bit C6000 mcbsp1 signals programming tms320c6000 mcbsp SPRU401 SPRU190
1996 - TMS320

Abstract: TMS320C25
Text: RET 0 DXR IMR ; XINT interrupt TA,9 ; initialize TA register RA,2 AIC_2ND TAp,9 , DXR ; ACC_hi requests 2nd XMIT DXR ; ACC_lo sets up registers DXR Figure 1. TMS320C25 code


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PDF TMS320 100nS) TMS320C25
1997 - TMS320

Abstract: TMS320C25
Text: ; RB,2 02h AIC_2ND AIC_CTR,2 ADDK CALL RET 0 DXR initialize TA' initialize TB , transmit data ; register ; wait for int 6,16 DXR ; ACC_hi requests 2nd XMIT DXR ; ACC_lo sets up registers DXR ; make sure word was sent Texas Instruments


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PDF TMS320 SPRA206 100nS) TMS320C25
2001 - mcbsp dsk

Abstract: SPRU401 0X21000002 TMS320C6711TM slla053 C6711 DSP kit TMS320C6711 TMS320C6211 TMS320C6000 SN65LVDM1676
Text: Transmitter XSR DX DXR CLKR CLKX Sample Rate Generator FSR FSX CLKS RINT , either a write to the data transmit register ( DXR ) or a read from the data receive register (DRR). - , Transmission If the transmitter is ready to transfer data, DXR is copied to the transmit shift register (XSR , start an EDMA transfer. Once data is copied from DXR to XSR, the transmitter ready bit (XRDY) is set , when DXR is copied to XSR. Again, the status of this bit can be polled to recognize when there is the


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PDF SLLA105 mcbsp dsk SPRU401 0X21000002 TMS320C6711TM slla053 C6711 DSP kit TMS320C6711 TMS320C6211 TMS320C6000 SN65LVDM1676
1999 - BIOS example source code

Abstract: SPRA598 main distribution frame C5000 C6000 BIOS mailbox example source code
Text: Port Receive ISR DRR DXR Serial Port IN OUT Codec Audio Source Speaker Figure 5 , -bit serial port Data Transmit Register ( DXR ) each time the interrupt is handled. When the whole frame has , pip.h62 (1) .include dss.h62 (2) DRR DXR .set 0x018c0000 .set 0x018c0004 .bss rtxDone,4 , DSS_rxCnt if (DSS_txCnt) { ldw *+b14(_DSS_txCnt),b1 nop 4 b txErr ; * DXR = *DSS_txPtr+; ldw , DXR ,a1 mvkh DXR ,a1 ; DSS_txCnt­­; sub b2,1,b2 stw a0,*a1 stw b2,*+b14(_DSS_txCnt) ; if


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PDF SPRA598 BIOS example source code main distribution frame C5000 C6000 BIOS mailbox example source code
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