The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
TCXO-EVAL-T BOARD Connor-Winfield EVAL BOARD FOR CW 5X7 SMT TCXO'S
EK64101-11 Peregrine Semiconductor Corp BOARD EVAL DTC PE64101
EK64102-11 Peregrine Semiconductor Corp BOARD EVAL DTC PE64102
PE64906B-Z Peregrine Semiconductor Corp IC RF DTC 100-3000MHZ 10QFN
DS4026S+KCC Maxim Integrated Products 10MHz to 51.84MHz TCXO
NT3225SA-26.000000MHZ Nihon Dempa Kogyo Co Ltd OSC TCXO 26.000000 MHZ SMD

DTC TCXO Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
ECCOBOND 45

Abstract: ovenaire eccobond ovenaire osc ovenaire oak frequency control OSC-35 ovenaire 10 mhz oscillator OSC 35 ovenaire 10 mhz oscillator tt 2232 ECCOBOND 55 application note DTC TCXO
Text: charlottesville, virginia I TCXO CATALOG TOLERANCES 2231 E-14 UNLESS , , virginia •ht 2 OF 3 ose 35-Z-X nam! X i ¡M I IT) ro m fco w «M O K X M TCXO CATALOG t0liwanc6s oTNcmnac inoirwd { MILLIMSTCM 1 AIMLM INCH DtC ± REV. TO SHT. 1. TNT 2/85 LET_ 2232 , ASSIGNED AS NEEDED. CHARLOTTESVILLE, VIRGINIA mams TCXO CATALOG tolerances 2233 F—02 OTHKMrWC


OCR Scan
PDF 2flS10 35-2-X ECCOBOND 45 ovenaire eccobond ovenaire osc ovenaire oak frequency control OSC-35 ovenaire 10 mhz oscillator OSC 35 ovenaire 10 mhz oscillator tt 2232 ECCOBOND 55 application note DTC TCXO
2011 - p36AG

Abstract: No abstract text available
Text: IDT6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCXO or LVCMOS input , , it will not be re-selected until 1024 cycles have passed. Packaged in 24-pin QFN LVCMOS or TCXO , TCXO_INA Input Connect to 13 MHz TCXO input. 24 VDD Power Connect to +1.8 V. IDT , ±10%, Ambient Temperature -40 to +85° C Parameter Symbol Input Frequency Conditions Min. TCXO , accelerate your future networks. Contact: w w w.I DT.c om For Sales For Tech Support 800-345-7015


Original
PDF IDT6P30006A 24-pin p36AG
2012 - Not Available

Abstract: No abstract text available
Text: IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 , 1024 cycles have passed. Packaged in 24-pin QFN TCXO sine wave input +2.5 V operating voltage , Connect to TCXO input. 24 VDDO1 Power Connect to +3.0 V. IDT® CLOCK DISTRIBUTION CIRCUIT , , Note 3 TCXO Input Swing Max. LVCMOS_INB, TCXO_INA, Note 2 Time Switch Clock Inputs Typ , Innovate with IDT and accelerate your future networks. Contact: w w w.I DT.c om For Sales For Tech


Original
PDF IDT6T39007A 24-pin
2008 - R5F70865

Abstract: No abstract text available
Text: APPLICATION NOTE SH7080 Group Data Transfer Controller ( DTC ) in Normal Transfer Mode Introduction This application note describes the normal transfer mode of the data transfer controller ( DTC ). , Controller ( DTC ) in Normal Transfer Mode 1. Specification In this sample application, ADI interrupt requests from the A/D converter of the SH7086 activate the DTC for data transfer in normal transfer mode. A/D conversion on analog input channels 0 to 3 (AN0 to AN3) proceeds three times. The DTC transfers


Original
PDF SH7080 SH7086 REJ06B0700-0100/Rev R5F70865
2008 - DSP DTS

Abstract: R5F70865
Text: APPLICATION NOTE SH7080 Group Data Transfer Controller ( DTC ) in Block Transfer Mode Introduction This application note describes the block transfer mode of the data transfer controller ( DTC ). It , Controller ( DTC ) in Block Transfer Mode 1. Specification In this sample application, ADI interrupt requests from the A/D converter of the SH7086 activate the DTC for data transfer in block transfer mode , each round of A/D conversion, the DTC regards the converted data from all four channels as a block and


Original
PDF SH7080 SH7086 REJ06B0702-0100/Rev DSP DTS R5F70865
Not Available

Abstract: No abstract text available
Text: Section 8 Data Transfer Controller ( DTC ) 8.1 Overview The SH7040 Series has an on-chip data transfer controller ( DTC ), which is activated either by interrupts or software and can perform data , , external ROM, external RAM - On-chip peripheral modules (excluding DMAC/ DTC ) - Memory-mapped external , byte/word/longword · Interrupts activating the DTC can be requested of the CPU - Interrupt requests , HITACHI 8.1.2 Block Diagram Figure 8.1 shows the DTC block diagram. DTC transfer information is


OCR Scan
PDF SH7040 32-bit
2004 - 2215S

Abstract: 0x600000
Text: APPLICATION NOTE H8S/2200 Series DTC Transfer (Software Activation) Introduction Transfers data on an SRAM chip to other addresses on the chip by DTC that is activated by software. Target , . 19 REJ06B0348-0100Z/Rev.1.00 March 2004 Page 1 of 30 H8S/2200 Series DTC Transfer , the chip using DTC that is activated by software. 2. Configuration The configuration of the , 2 of 30 H8S/2200 Series DTC Transfer (Software Activation) 3. Description of Functions


Original
PDF H8S/2200 H8S/2215 REJ06B0348-0100Z/Rev 2215S 0x600000
2001 - ST7265

Abstract: ST72651 ST72652 ST72F651 ST72F652 TQFP64
Text: Mass Storage Interface ­ DTC (Data Transfer Coprocessor): Universal Serial/Parallel communications , 16K FLASH 1K (256) 2 USB, DTC , Timer, ADC, I C, PWM USB, DTC , Timer Dual 2.4V to 5.5V or , Coprocessor ( DTC ), able to handle fast data transfer with external devices. This DTC also computes the CRC , over the USB and DTC when accessing the Data Buffer. In USB mode, the USB interface is serviced before the DTC . ­ A FLASH Supply Block able to provide programmable supply voltage and I/O electrical levels


Original
PDF ST7265 ST7265 ST72651 ST72652 ST72F651 ST72F652 TQFP64
2008 - R5F70865

Abstract: No abstract text available
Text: APPLICATION NOTE SH7080 Group Data Transfer Controller ( DTC ) in Chain Transfer Mode Introduction This application note describes the chain transfer mode of the data transfer controller ( DTC ). It , Controller ( DTC ) in Chain Transfer Mode 1. Specification In this sample application, ADI interrupt requests from the A/D converter of the SH7086 activate the DTC for data transfer in normal transfer mode , mode. The DTC transfers the converted data in ADDR0 to the on-chip RAM. After the data in ADDR0 have


Original
PDF SH7080 SH7086 REJ06B0703-0100/Rev R5F70865
2000 - ST72651

Abstract: ST72652 ST72F651 ST72F652 TQFP64 ST7265 usb to parallel port
Text: packets and 512-byte blocks PLL for generating 48 MHz USB clock using a 12 MHz crystal DTC (Data , ) USB, DTC , Timer, ADC, ST72F652 16K FLASH 1K (256) I2C, PWM USB, DTC , Timer Dual 2.4V , corresponds to a sector both on computers and FLASH media cards). ­ A Data Transfer Coprocessor ( DTC ), able to handle fast data transfer with external devices. This DTC also computes the CRC or ECC required , DTC when accessing the Data Buffer. In USB mode, the USB interface is serviced before the DTC . ­ A


Original
PDF ST7265 512-byte ST72651 ST72652 ST72F651 ST72F652 TQFP64 ST7265 usb to parallel port
FFB000

Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family DTC Transfer with Transfer Information Read Skipping Processing Introduction The data transfer controller ( DTC ) is activated by an IRQ0 interrupt and transfers 64 bytes of data twice. In the second data transfer, the DTC skips reading of the transfer information. Target , . 8 REJ06B0624-0100/Rev.1.00 September 2006 Page 1 of 17 H8SX Family DTC Transfer with , transfer by the DTC for this sample task. · The DTC is activated by an IRQ0 interrupt and transfers two 64


Original
PDF H8SX/1653 REJ06B0624-0100/Rev FFB000
2008 - Not Available

Abstract: No abstract text available
Text: APPLICATION NOTE SH7280 Group Using the DTC in the Clock Synchronous-Mode Transfer of Serial , ( DTC ). This application note is a summary for quick reference of information required in the design of , . 21 REJ06B0809-0100/Rev.1.00 December 2008 Page 1 of 23 SH7280 Group Using the DTC in , Specifications In this sample task, serial transfer is conducted with the data-transfer controller ( DTC ) used , and DTC are used. · The communications format has a fixed 8-bit data length. · The data-transfer


Original
PDF SH7280 SH7285 REJ06B0809-0100/Rev
2000 - Not Available

Abstract: No abstract text available
Text: packets and 512-byte blocks PLL for generating 48 MHz USB clock using a 12 MHz crystal DTC (Data , ) USB, DTC , Timer, ADC, ST72F652 16K FLASH 1K (256) I2C, PWM USB, DTC , Timer Dual 2.4V , corresponds to a sector both on computers and FLASH media cards). ­ A Data Transfer Coprocessor ( DTC ), able to handle fast data transfer with external devices. This DTC also computes the CRC or ECC required , DTC when accessing the Data Buffer. In USB mode, the USB interface is serviced before the DTC . ­ A


Original
PDF ST7265 512-byte
1999 - 10E6

Abstract: E62148R DTCC
Text: DTC , SCI & FRT: Data Transfer Controller, Serial Communications Interface & 16 Bit Free Running Timer Introduction This Application Note details how to use the H8S/2148 DTC , SCI and FRT peripherals. The Application Note is primarily concerned with the operation of the DTC . It shows how to use the DTC , only used to help demonstrate the DTC . DTC Basics DTC stands for `Data Transfer Controller'. It can , registers, are not loaded into the DTC until activation interrupt occurs. This is unlike a normal DMA


Original
PDF
2004 - Not Available

Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2200 Series DTC Transfer (Activation by 8-Bit Timer Channel 0A Interrupt , chip with the DTC that is activated by the 8-bit timer channel 0A interrupt. It also transfers data continuously to other addresses on the SRAM chip with the DTC chain transfer function. Target Device H8S , . 17 REJ06B0349-0100Z/Rev.1.00 March 2004 Page 1 of 28 H8S/2200 Series DTC Transfer , H8S/2215 transfers data on an SRAM to other addresses with the DTC that is activated by the 8


Original
PDF H8S/2200 H8S/2215 REJ06B0349-0100Z/Rev
2008 - CKE 8002

Abstract: No abstract text available
Text: APPLICATION NOTE SH7280 Group Using the DTC in the Asynchronous-Mode Transfer of Serial Data by , mode by the serial communications interface (SCI) with the aid of the data-transfer controller ( DTC ). , . 19 REJ06B0775-0100/Rev.1.00 September 2008 Page 1 of 21 SH7280 Group Using the DTC , In this sample task, serial transfer is conducted with the data-transfer controller ( DTC ) used to , example of connection for transmission and reception by the SCI in asynchronous mode. · SCI_0 and DTC are


Original
PDF SH7280 SH7285 REJ06B0775-0100/Rev CKE 8002
H0011

Abstract: FFB000 DTC Data Technology
Text: APPLICATION NOTE H8SX Family DTC Data Transfer Initiated by IRQ Interrupt Introduction The DTC is activated by an IRQ interrupt and it performs data transfer of 128 bytes. Target Device , . 8 REJ05B0789-0100/Rev.1.00 March 2006 Page 1 of 16 H8SX Family DTC Data Transfer , DTC . · The DTC is activated by an IRQ0 interrupt and transfers data blocks, each of which is 128 , ) by means of the DTC . H8SX/1582F On-chip ROM Trigger signal DTC vector table IRQ0 interrupt


Original
PDF H8SX/1582F REJ05B0789-0100/Rev H0011 FFB000 DTC Data Technology
FFB000

Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family DTC Transfer with Transfer Information Write-Back Skipping Processing Introduction The data transfer controller ( DTC ) is activated by an IRQ0 interrupt and transfers two bytes of data. In the second byte transfer, the DTC skips write-back of the transfer information , . 8 REJ06B0625-0100/Rev.1.00 September 2006 Page 1 of 17 H8SX Family DTC Transfer with , diagram of data transfer by the DTC for this sample task. · The DTC is activated by an IRQ0 interrupt and


Original
PDF H8SX/1653 REJ06B0625-0100/Rev FFB000
2001 - ST7265

Abstract: ST72651 ST72652 ST72F651 ST72F652 TQFP64
Text: Mass Storage Interface ­ DTC (Data Transfer Coprocessor): Universal Serial/Parallel communications , 16K FLASH 1K (256) 2 USB, DTC , Timer, ADC, I C, PWM USB, DTC , Timer Dual 2.4V to 5.5V or , Coprocessor ( DTC ), able to handle fast data transfer with external devices. This DTC also computes the CRC , over the USB and DTC when accessing the Data Buffer. In USB mode, the USB interface is serviced before the DTC . ­ A FLASH Supply Block able to provide programmable supply voltage and I/O electrical levels


Original
PDF ST7265 ST7265 ST72651 ST72652 ST72F651 ST72F652 TQFP64
2004 - DTC Data Technology

Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2200 Series Simultaneous Startup of DTC , DMAC, and CPU Introduction Starts up DTC , DMAC, and CPU each time a compare match occurs. DTC transfers data from the ROM to the I/O , the port and stops DTC and DMAC when the port output goes low. Target Device H8S/2239 Contents , Startup of DTC , DMAC, and CPU 1. Specifications 1. As shown in figure 1, this sample task starts up DTC , DMAC, and CPU each time a timer compare match occurs. DTC transfers data to I/O Port from the


Original
PDF H8S/2200 H8S/2239 REJ06B0323-0100Z/Rev DTC Data Technology
2004 - SH7145

Abstract: No abstract text available
Text: APPLICATION NOTE SH7145 Group I2C Bus Interface in Combined Use with DTC Introduction This , I2C bus (Inter IC Bus) interface through the use of DTC (Data Transfer Controller) of the SH7145F , Use with DTC . 2 Specifications , . 15 2. 2.1 2.2 2.3 2.4 2.5 2.6 I2C Bus Single-Master Reception in Combined Use with DTC , in Combined Use with DTC 1. 1.1 I2C Bus Single-Master Transmission in Combined Use with DTC


Original
PDF SH7145 SH7145F. SH7145F, SH7145F REJ06B0399-0100Z/Rev
2009 - h8sx

Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family DTC Block Transfer Introduction This application note describes using the data transfer controller ( DTC ) function to transfer five blocks of data, each comprising two bytes, and outputting the transferred data to I/O ports (P1 and P2). The DTC block transfer function , . 24 REJ06B0816-0100/Rev.1.00 January 2009 Page 1 of 26 H8SX Family DTC Block Transfer , controller ( DTC ) function to transfer five blocks of data, each comprising two bytes, and outputting the


Original
PDF H8SX/1663 H8SX/1622 H8SX/1638 H8SX/1648 H8SX/1648A H8SX/1648L H8SX/1648G REJ06B0816-0100/Rev h8sx
2008 - R5F70865

Abstract: No abstract text available
Text: APPLICATION NOTE SH7080 Group Data Transfer Controller ( DTC ) in Repeat Transfer Mode Introduction This application note describes the repeat transfer mode of the data transfer controller ( DTC ). , Controller ( DTC ) in Repeat Transfer Mode 1. Specification In this sample application, ADI interrupt requests from the A/D converter of the SH7086 activate the DTC for data transfer in repeat transfer mode , the DTC transfers converted data to the on-chip RAM one channel at a time. After the converted data


Original
PDF SH7080 SH7086 REJ06B0701-0100/Rev R5F70865
2008 - PE2D

Abstract: R5F70865
Text: APPLICATION NOTE SH7080 Series Using the DTC to Drive Clock Synchronous Data Transfer by the , FIFO) and the data-transfer function of the DTC (data transfer controller). This application note is a , . 31 REJ06B0708-0100/Rev.1.00 February 2008 Page 1 of 33 SH7080 Series Using the DTC , application, the DTC 's data-transfer functions and SCIF are used for clock-synchronous transmission and , received. · DTC transfer for transmission is activated by the transmit FIFO data empty interrupt, with the


Original
PDF SH7080 SH7086 REJ06B0708-0100/Rev PE2D R5F70865
FFF800

Abstract: No abstract text available
Text: of Functions 1. This sample task starts up DTC each time it detects a falling edge of IRQ1 and outputs 6-byte data to port G from port B. A. The block diagram of DTC used by this sample task is shown , starts up DTC on an external request ( DTC startup by IRQ) · Function that transfers data in the unit of block at DTC startup (block transfer mode) Internal RAM Register information Interrupt controller MRA MRB CRA CRB DAR SAR DTC startup request IRQ1 Control logic DTC Output pattern


Original
PDF H8S/2339 REJ06B0463-0100/Rev FFF800
Supplyframe Tracking Pixel