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DSP96002--32-B Datasheets Context Search

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1995 - PLD-6

Abstract: PLD-5 DSP96002 F100
Text: address lines. aD(0:31) These signals are the 32 Port A data lines. aR/W 2-6 Mode Select B , DSP96002 Port A Control Pins Free Port B Pins For Future Memory and I/O Expansion Port A , support of IEEE 754 Single Precision and Single Extended Precision Floating-Point with 32 -bit signed and , Floating Point Instructions per Second (MFLOPS) peak with a 40.0 MHz clock · Single-Cycle 32 x 32 , Do Loops · Fast Auto-Return Interrupts · 2 Independent On-Chip 512 x 32 -bit Data RAMs · 2


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PDF APR10section2 DSP96002 DSP96002 PLD-6 PLD-5 F100
1996 - BF740

Abstract: f3620 BF681 BF136 ad1794 BF239 BA 9511 F7314 DSP96002/D F48D
Text: GNDN GNDQ 32 / Address Bus B BA0­BA31 32 / DSP96002 Data Bus B BD0 ­ BD31 Port B , 32 -BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSOR The DSP96002 is designed to support , Processing Unit (CPU) consists of three 32 -bit execution units operating in parallel. The DSP96002 has two , ) Bus Control YAB * XAB * PAB * Port A Address External 32 Address Switch 4 32 -bit Host Interface Timer 32 Data Dual Channel DMA Controller Internal Switch And Bit


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PDF DSP96002/D, DSP96002 32-BIT DSP96002 BF740 f3620 BF681 BF136 ad1794 BF239 BA 9511 F7314 DSP96002/D F48D
1996 - DSP96002 APPLICATIONS

Abstract: DSP96002 address generation unit block diagram of 32 bit array multiplier
Text: Port B Control Port A Freescale Semiconductor, Inc. 32 -BIT IEEE FLOATING-POINT DUAL-PORT , circuitry. The Central Processing Unit (CPU) consists of three 32 -bit execution units operating in parallel , * XAB * PAB * Address External 32 Address Switch Dual Channel DMA Controller 4 32 -bit Host Interface Internal Switch And Bit Manipulation Unit Timer 32 Data Clock Generator Y Data * Memory 512 x 32 RAM 512 x 32 ROM Program Address Generator 4 32


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PDF DSP96002P/D DSP96002 DSP96002 32-bit DSP96002 APPLICATIONS address generation unit block diagram of 32 bit array multiplier
MOC BTA

Abstract: DSP96002UM 000004B0 Nippon capacitors moc 2030 BF740 Bf7314 BF299 AA1716 AA06
Text: Address 32 External Address Switch X A B * PAB* Program ' X Data * Memory Memory 1 0 2 4x3 2 512x32 , processing p er in stru ctio n cycle Single-cycle 32 x 32 b it parallel m u ltip lier H ighly parallel , (DDB) O ne 32 -bit bidirectional internal P ro g ram D ata Bus (PDB) T w o 32 -bit external d ata b u ses , e n t on-chip 512 x 32 -bit d a ta ROM s (1024 x 32 -bit v irtual m em ory) O n-chip 64 x 32 -bit b o o , Groupings Power1 V CCN DSP96002 32 M -+ 32 Address Bus B BA0-B A 31 Data Bus B BDO - BD31 Port


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PDF DSP96002/D, DSP96002 32-BIT DSP96002 ------------------------------1ATX24213-6 1CV96 DSP96002/D MOC BTA DSP96002UM 000004B0 Nippon capacitors moc 2030 BF740 Bf7314 BF299 AA1716 AA06
1988 - mvb bus schematics

Abstract: mc88000 real time application and product for fir DSP56001 users manual IC 7492 DSP96002 fft c b2n MC880 newton raphson power flow model pdf for barrel shifter design from computer archive
Text: ADDRESS BUS A aA0-aA31 Vcc Vss 32 (2) (4) ADDRESS BUS B (2) (4) DATA BUS A aD0-aD31 Vcc Vss 32 32 32 (2) (4) DATA BUS B (2) (4) PORT A BUS CONTROL aS1 aS0 - aR , . External memory spaces for each port, A and B , are addressed via a single 32 -bit unidirectional address , DSP96002 32 -BIT DIGITAL SIGNAL PROCESSOR USER'S MANUAL Motorola, Inc. Semiconductor Products , Single Extended Precision (11 bit Exponent and 32 bit Mantissa) Floating-Point and 32 bit signed and


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PDF DSP96002 32-BIT DSP96002 DSP96002. mvb bus schematics mc88000 real time application and product for fir DSP56001 users manual IC 7492 DSP96002 fft c b2n MC880 newton raphson power flow model pdf for barrel shifter design from computer archive
1988 - DSP96002

Abstract: MC68881 FFFF0000 bootstrap 0000-07FF
Text: Interface (Port A) B ) A) B ) A) B ) A) B ) Figure 9-1. DSP96002 Initial Chip Operating Mode , USER'S MANUAL 9-1 9.1.2 Mode 1 (Internal PRAM enabled, Reset at $FFFFFFFE, Port B ) In Mode 1 , of the hardware reset vector is $FFFFFFFE, located in the Port B external program memory space. The , Figure 9-2. 9.1.4 Mode 3 (Internal PRAM disabled, Reset at $00000000, Port B ) In Mode 3 the internal , . The address of the hardware reset vector is $00000000, located in the Port B external program memory


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PDF DSP96002 DSP96002. 0000003F, 000001FF 000007FF FFFFFF80- MC68881 FFFF0000 bootstrap 0000-07FF
1996 - f3620

Abstract: BF681 ba05 BF136 TRANSISTOR BC 187 motorola g18 BTS 129 BF740 BF308 Nippon capacitors
Text: Power1 VCCN VCCQ Ground2 GNDN GNDQ 32 / Address Bus B BA0­BA31 32 / DSP96002 Data , ) consists of three 32 -bit execution units operating in parallel. The DSP96002 has two identical memory , Control YAB * XAB * PAB * Address External 32 Address Switch 4 32 -bit Host Interface Timer 32 Data Dual Channel DMA Controller Internal Switch And Bit Manipulation Unit Clock Generator Y Data * Memory 512 × 32 RAM 512 × 32 ROM Program Address Generator


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PDF DSP96002/D, DSP96002 DSP96002 32-bit f3620 BF681 ba05 BF136 TRANSISTOR BC 187 motorola g18 BTS 129 BF740 BF308 Nippon capacitors
1988 - 7N121

Abstract: MC88000 7483 logic circuit adder and subtracter IEEE-745 IC 7483 Single 3-Bit binary full adder look area DSP96002 APPLICATIONS DSP96002 dlms circuit diagram of half adder using IC 7486 time delay circuit for ic 74123
Text: Vss 32 (2) (4) 32 32 bA0-bA31 Vcc Vss DATA BUS B (2) (4) (2) (4) PORT , aD0-aD31 Vcc Vss 32 bD0-bD31 Vcc Vss PORT B BUS CONTROL aS1 aS0 - aR/ W - ­ a B S , Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. DSP96002 32 -BIT DIGITAL , Single Extended Precision (11 bit Exponent and 32 bit Mantissa) Floating-Point and 32 bit signed and , clock · Single-Cycle 32 x 32 Bit Parallel Multiplier · Highly Parallel Instruction Set with


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PDF DSP96002 32-BIT DSP96002 7N121 MC88000 7483 logic circuit adder and subtracter IEEE-745 IC 7483 Single 3-Bit binary full adder look area DSP96002 APPLICATIONS dlms circuit diagram of half adder using IC 7486 time delay circuit for ic 74123
1995 - DSP96002

Abstract: MC68000 MC68040
Text: Vss 32 (2) (4) ADDRESS BUS B (2) (4) DATA BUS A aD0-aD31 Vcc Vss 32 32 32 , Ground Plane Power/Ground Plane Subtotal 2 5 1 1 9 Port A/ B Each Port Both Ports Pins , Subtotal Port A/ B Bus Control Signals Bus Control Spare Bus Control Power Bus Control Ground Control Subtotal 32 32 2 4 2 4 76 64 64 4 8 4 8 152 Each Port Both Ports Pins Pins 17 2 1 2 22 Pinout Summary CPU Pins Package Power/Ground Planes Port A/ B Pins Data and


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PDF DSP96002 DSP96002/D) DSP96002 MC68000 MC68040
1988 - FFFF0000

Abstract: DSP96002 LBL33 LBL22
Text: internal PRAM thru Host Interface in Port B . BOOT EQU The location in P: memory ; where the external , M_HCRB EQU $FFFFFFE4 ; Port B Host Control Register M_HSRB EQU $FFFFFFE5 ; Port B Host Status Register M_HRXB EQU $FFFFFFE7 ; Port B Host Rec. Data Register ORG PL:$0 ; bootstrap code starts at P , the required memory expansion port (Port A or B ). ; ; The first routine will load 4,096 bytes from , ,024 32 -bit words and stored in contiguous internal PRAM memory ; locations starting at P:$0. Note


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PDF DSP96002 DSP96002 DSP96002. FFFF0000) 32-bit FFFF0000 LBL33 LBL22
1995 - DSP56001

Abstract: DSP96002
Text: bits were shifted-in (so a new command is available) and the second indicating that 32 bits were shifted-in (the data associated with that command is available) or that 32 bits were shifted-out (the data , from OBC (one indicating that 8 bits have been received and the other that 32 bits have MOTOROLA , and Control Register (OSCR) The Status and Control Register is a 32 -bit register used to select the , hardware reset. 10.4.3 Program Memory Address Latch (OPAL) The Program Memory Address Latch is a 32


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PDF DSP56001) DSP96002 DSP96002 DSP56001
1995 - alu 7481

Abstract: 7486 Logic ICs MC88000 7481 memory ics DSP96002 shift register 7491 74181 introduced 96002 manual MCM511002
Text: own service routine. Three on-chip peripherals are provided in the DSP96002: · · a 32 -bit parallel Host MPU/DMA Interface connected to Port B . · 7.2 a 32 -bit parallel Host MPU/DMA , two external expansion ports (Port A and Port B ). Each port has a bus control register where memory , DRAM/VRAM memory support are located, and control bits for direct software control of B R and B L pins , for direct software control of the B R and B L pins. MOTOROLA DSP96002 USER'S MANUAL 7-1


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PDF DSP96002 alu 7481 7486 Logic ICs MC88000 7481 memory ics shift register 7491 74181 introduced 96002 manual MCM511002
1995 - C-15

Abstract: C-16 DSP96002 DSP96002 fft
Text: operands in the DSP96002 are either 32 bits long (Single Real), 64 bits long (Double Real) or 96 bits long , supported for memory storage of floating point numbers. SP numbers are represented by 32 bits in memory , , i.e.: 1.f = 1+(o.5) · b + (0.25) · b +.+ (­ 1 2 1 2 ) p-1 · b p-1 Therefore , a nonzero fractional field. The value of the sign bit is irrelevant in this en- coding. QNaNs ( b , fractional field of all ones ( all b = 1 in f). Other types of QNaNs i (DSP96002 "illegal" NaNs) may


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PDF 32-bit DSP96002 C-15 C-16 DSP96002 fft
1996 - PAL Decoder 16L8

Abstract: 2N3904 A31 ICT-286-S-TG 2N3904 A30 ICT-203-S-TG ICT-286-STG ICE-283-S-TG 20000000-3FFFFFFF P1C30 NSH-36SB-S2-TG30
Text: made to accomodate 16 256K X 4 bit devices (MCM6228) also. Port A and Port B both have 64K x 32 words , DSP96002 PORT A CTRL PORT B CTRL MEMORY DECODER MEMORY DECODER P/X/Y SRAM P/X/Y SRAM PMEM EPROM PMEM EPROM PORT A DATA PORT A ADDRESS PORT B DATA PORT B ADDRESS Figure , JG1-3 (1-2),(1-2),(1-2) Exit reset in Mode 0. JG4-6 (1-2),(1-2),(1-2) IRQA/ B /C pass , deassertion of the U20 output. 10.3.4 EXTERNAL IRQA/ B /C INPUT PATH The external input path for IRQA, IRQB


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PDF DSP96002 ADM96002 PAL Decoder 16L8 2N3904 A31 ICT-286-S-TG 2N3904 A30 ICT-203-S-TG ICT-286-STG ICE-283-S-TG 20000000-3FFFFFFF P1C30 NSH-36SB-S2-TG30
DSP56ADC16

Abstract: 56adc16 bba 3rd sem datasheet VMEbus interface handbook ADS96002 BBA 1st sem date sheet architecture of microprocessor 80386 DSP56ADC16S adc16s micro bts datasheet
Text: 56ADC16 Sigma-Delta A/D Converters vi 2-31 2-31 3.1 3.2 3.3 3.4 3.5 Introduction The , Handler 3.10 Timing Considerations 3-1 3-1 3-2 3-2 4.1 4.2 4-1 4.3 4.4 Introduction , Assembly Language Listing 2-30 Figure 3-1 Connection Block Diagram 3-4 Figure 3-2 , DSP96002 S Host Interface A/ B IRQA M Port A/ B M DMA M Memory DSP96002 TS Figure 1-1 , 32 -Bit Buses Figure 1-2 Host Interface Block Diagram 1-4 MOTOROLA A DMA request is


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PDF DSP96002 APR10 000000A 03803F85 DSP96002ADS DSP96002UM/AD 56-Bit DSP96002/D, DSP56ADC16 56adc16 bba 3rd sem datasheet VMEbus interface handbook ADS96002 BBA 1st sem date sheet architecture of microprocessor 80386 DSP56ADC16S adc16s micro bts datasheet
1995 - B1151 Y

Abstract: b1333 B1402 D3S 59 B1432 3n14 DSP56000 b1151 B1571-1 DSP96002
Text: =6 (=2*N, mod 7) B-32 y: s4 s3 s2 s1 m4=3 (=N, mod 4) DSP96002 USER'S MANUAL MOTOROLA , APPENDIX B DSP BENCHMARKS B .1 DSP96002 STANDARD DSP BENCHMARKS Program size and , expense of not obtaining exact IEEE conformance. B .1.1 Real Multiply c=a* b move fmpy.s x:(r0 , 1 - 3 3 (3 d0.s,x:(r1) 1 - move d4,d6,d0 3) B -1 B .1.2 N Real Multiplies c(I) = a(I) * b (I) , I=1,.,N Program ICycles Words 1 1 move #aaddr,r0 move #baddr,r4


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PDF DSP96002 DSP56000/1 B-204 B1151 Y b1333 B1402 D3S 59 B1432 3n14 DSP56000 b1151 B1571-1
1996 - DSP96002

Abstract: DSP96002 APPLICATIONS 64x32
Text: Control Port B Control Program Interrupt Controller External Data Bus Switch 32 Data , MOTOROLA SEMICONDUCTOR PRODUCT INFORMATION Order this document by: DSP96002P/D DSP96002 32 , (OnCETM) debug circuitry. The Central Processing Unit (CPU) consists of three 32 -bit execution units , Control YAB * XAB * PAB * Port A Address External 32 Address Switch Dual Channel DMA Controller 4 32 -bit Host Interface Internal Switch And Bit Manipulation Unit Timer 32 Data


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PDF DSP96002P/D DSP96002 32-BIT DSP96002 DSP96002 APPLICATIONS 64x32
1995 - half adder ic number

Abstract: 32 bit carry select adder code DSP96002 fft ic number of half adder for full adder and half adder 32 bit carry select adder radix 2 booth multiplier 32 bit booth multiplier for fixed point floating point adder full adder 2 bit ic
Text: spaces for each port, A and B , are addressed via a single 32 -bit unidirectional address bus driven by a , SECTION 3 CHIP ARCHITECTURE 3.1 INTRODUCTION The DSP96002 architecture is a 32 , Address Generation Unit AGU) core architecture are described. 3.2 DSP96002 BLOCK DIAGRAM The , Stack · Program Memory · Port A and Port B External Bus Interfaces · Internal Bus , bidirectional 32 -bit buses, X Data Bus (XDB), Y Data Bus (YDB), Global Data Bus (GDB), the DMA Data Bus (DDB


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PDF DSP96002 32-bit half adder ic number 32 bit carry select adder code DSP96002 fft ic number of half adder for full adder and half adder 32 bit carry select adder radix 2 booth multiplier 32 bit booth multiplier for fixed point floating point adder full adder 2 bit ic
1995 - D-10

Abstract: D-12 D-16 DSP96002 3F800000 DSP96002 APPLICATIONS DSP96002 fft
Text: either 32 -bits long (Single Real), 64 bits long (Double Real) or 96 bits long (Register operand). The , for memory storage of floating point numbers. SP numbers are represented by 32 -bits in memory, and , . The value of the sign bit is irrelevant in this en- coding. QNaNs ( b =1) Quiet NaNs are , required by the standard. This QNaN is encoded by a fractional field of all ones ( all b = 1 in f , always a "legal" QNaN. Figure D-4 shows the encoding for QNaNs. SNaNs ( b =0) Signaling NaNs are never


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PDF 32-bit DSP96002 D-10 D-12 D-16 3F800000 DSP96002 APPLICATIONS DSP96002 fft
1991 - DSP96002

Abstract: MC68XX Nippon capacitors
Text: programmable ROMs on-chip. The Central Processing Unit (CPU) consists of three 32 -bit execution units , 32 -bit mantissa and 11-bit exponent is also implemented. All four rounding modes are supported - 1 , generation parts. The Data ALU also supports integer arithmetic including a 32 x 32 multiplication with a , and a dual channel DMA controller, the DSP96002 has six on-chip memories, two independent 32 -bit expansion bus ports (facilitating interfacing to page mode RAMs and VRAMs), two independent 32 -bit host


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PDF DSP96002AD/D DSP96002 DSP96002 DSP96002/D) MC68XX Nippon capacitors
1997 - ABB B18

Abstract: DSP96002 APPLICATIONS JG-27 DSP96002 Nippon capacitors ICT-286-S-TG 74FACT00 BA-06 PAL Decoder 16L8 JG11
Text: Table 2-9 DSP96002 ADM P1/J3 Port A Connector (Continued) PIN # ROW B ROW C 32 Note: ROW A , 30 bD29 RESET bA29 31 bD30 GND bA30 32 2-16 ROW B 29 Note: ROW , detailed schematics.Appendix B lists the Bill Of Materials (BOM) for the board. Detailed information is , 2.4.3 DSP96002 Port A/ B User EPROM Decoders . . . . . . . . . . . 2-10 2.4.4 DSP96002 Port A/ B User , . . . . . . . . . . . . A-1 APPENDIX B DSP96002ADM BILL OF MATERIALS . . . . . . . . . . . . B


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PDF DSP96002ADM DSP96002ADMUM/AD DSP96002 DSP96002ADM) additio2-TG30 ICT-203-S-TG ICE-283-S-TG ICT-286-S-TG PGA-244AH3-S-TG ICA-143-SCO-TG30 ABB B18 DSP96002 APPLICATIONS JG-27 Nippon capacitors ICT-286-S-TG 74FACT00 BA-06 PAL Decoder 16L8 JG11
1990 - f333

Abstract: BF740 mc88000 DSP96002 fft BA28 BA25 BA30 DSP96002 BF173 TC55-20
Text: Vss 32 (2) (4) DATA BUS A aD0-aD31 Vcc Vss 32 ADDRESS BUS B (2) (4) 32 32 , internal memory implemented. External memory spaces for each port, A and B , are addressed via a single 32 , ROMs on-chip. The Central Processing Unit (CPU) consists of three 32 -bit execution units operating in , Binary Floating-Point Arithmetic. Single extended precision with a 32 -bit mantissa and 11-bit exponent , supports integer arithmetic including a 32 x 32 multiplication with a full, nontruncated, 64-bit product


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PDF DSP96002/D DSP96002 96-bit DSP96002 beff17b2 bef41f07 bee900b7 beddbe79 bed25a09 f333 BF740 mc88000 DSP96002 fft BA28 BA25 BA30 BF173 TC55-20
Not Available

Abstract: No abstract text available
Text: Min - Typical - Max 0.4 Unit V I0L = 3.2 mA f = 33.3 MHz2'3 f = 40 MHz2,3 f = 60 MHz2 , . 2-4 DSP96002/D, Rev. 2 b3 b ? 2 4 a 014A443 bfl? MOTOROLA Specifications AC Electrical , °C MOTOROLA I DSP96002/D, Rev. 2 b3 b 7 2 4 f l Q14fl44t> 3Tb 2-7 Specifications AC Electrical , Min 2 1.5 Max 14 Max 12 - Max 8 - ns 2 2 2 2 2 - 32 - ns 33 14 , 6 - - 3.0 ns MOTOROLA DSP96002/D, Rev. 2 b3 b 7 2 4 f l 0146452 fc>ST 2-13


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PDF DSP96002. DSP96002/D, G14fl47b
1995 - 100S

Abstract: DSP96002
Text: *23 Linear (Modulo 2* 32 ) where MMMMMMMM = Modifier Register Contents in Hex Figure A , * * * * * * * ? ? ? * ­ ­ ­ ­ ­ ­ ­ ? ­ ­ Note 31 Note 5 Note 32 ,33 Note 23, 32 ,34 Note , . Cleared otherwise. Note 18 V - Cleared if the most significant 32 bits of the 64-bit result are the sign extension of the least significant 32 bits. Set otherwise. Note 19 All ? Bits - Set if , the most significant 32 bits of the 64-bit result are zero. Set otherwise. Note 26 C - Set if


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PDF DSP96002 100S
1995 - DSP96002

Abstract: HAL0 HAL00
Text: interrupt source are shown. Interrupt starting addresses are internally-generated 32 -bit addresses which , Channel 2 Reserved Reserved Reserved Reserved Host A Command (default) Host B Command (default , Memory Host A Write X Memory Host A Write Y Memory Host A Write P Memory Host B Receive Data Host B Transmit Data Host B Read X Memory Host B Read Y Memory Host B Read P Memory Host B Write X Memory Host B Write Y Memory Host B Write P Memory Reserved : Reserved User interrupt vector : User


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PDF DSP96002 HAL0 HAL00
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