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CX7297-011 TE Connectivity (CX7297-011) MXSB-24B/1XU-2XU
CJ7360-005 TE Connectivity (CJ7360-005) CSJA-24B/1XU-1XU-M
CJ7360-011 TE Connectivity (CJ7360-011) CSJA-24B/1XU-1XU-M
CJ7356-011 TE Connectivity (CJ7356-011) CSJA-24B/1XU-1XU
CX7297-005 TE Connectivity (CX7297-005) MXSB-24B/1XU-2XU
CAW-1C-24B (1617087-1) TE Connectivity (1617087-1) CAW-1C-24B = HALF.10A.1 POLE.2

DSP56300--24-B Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1999 - DSP56300

Abstract: DSP56000 DSP56002 DSP56303
Text: , B SUB #ii,D ;#ii is 6-bit immediate short data SUB #iiiiii,D ;#iiiiii is 24 -bit immediate , DSP products. 1 6 3 24 -bit Sync. Serial Timer / Serial Event (SSI , YDB Internal Data Bus Switch 7 Y Data X Data Program Memory Memory Memory 512 × 24 RAM 256 × 24 RAM 256 × 24 RAM 64 × 24 ROM 256 × 24 ROM 256 × 24 ROM (boot) (A-law / -la w) (sine) PAB XAB YAB Address Generation Unit 24 -bit 56000 DSP Core PLL 16-bit Bus 24 -bit Bus


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PDF AN1829/D DSP56002 DSP56303 DSP56303 DSP56303. AN1830/D, DSP56303, DSP56300 DSP56000
1996 - vhdl code for 8 bit barrel shifter

Abstract: 16 bit single cycle mips vhdl MOTOROLA DSP56300 architecture pga 132 packaging architectural block diagram of motorola 563xx TQFP112 vhdl code for 16 bit barrel shifter 32 bit barrel shifter vhdl 563xx 32 bit single cycle mips vhdl
Text: LOGIC UNIT PIPELINE REG 48 56 56 24 56 SHIFTER 24 56 A (56) B (56) 56 56 56 , INTERFACE E TRIPLE TIMER B B Memory Expansion Area 24 -BIT 56300 FAMILY CORE , Digital Signal Processing Division Introducing Motorola DSP's 24 -bit DSP56300 Architecture , Performance 56300 Core 24 / 24 563xx 56302 On Chip RAM Emulation 33, 40 563xx ROM 144 Pin TQFP 56xxx Core 56002 1992 40, 50, 66, 80, LV40 132 PQFP/ 144 TQFP 24 / 24 0.65 µ 56004 RAM


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PDF 24-bit DSP56300 563xx 56xxx PQFP/132 56xxx 6001A vhdl code for 8 bit barrel shifter 16 bit single cycle mips vhdl MOTOROLA DSP56300 architecture pga 132 packaging architectural block diagram of motorola 563xx TQFP112 vhdl code for 16 bit barrel shifter 32 bit barrel shifter vhdl 563xx 32 bit single cycle mips vhdl
1999 - DSP56000

Abstract: DSP56002 DSP56300 DSP56303
Text: , B DSP56300 only. Multiplies the immediate 24 -bit source operand with the 24 -bit source operand , destination accumulator A, B ;#ii is 6-bit immediate short data AND #iiiiii,D ;#iiiiii is 24 -bit immediate , , Y0, Y1 ;D is destination accumulator A, B ;#ii is 6-bit immediate short data ;#iiiiii is 24 , products. 6 3 24 -bit Sync. Serial Timer / Serial Event Freescale Semiconductor , Memory Memory Memory 512 × 24 RAM 256 × 24 RAM 256 × 24 RAM 64 × 24 ROM 256 × 24 ROM 256 × 24 ROM


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PDF AN1829/D DSP56002 DSP56303 DSP56303 DSP56303. AN1830/D, DSP56303, DSP56000 DSP56300
2004 - 23/ANSC140VIT/D

Abstract: SC1400 SC140 MSC8101 MSC7119 MSC7118 MSC7116 DSP56F800 DSP56300 AN2715
Text: 5 Core Architectures Compared . 2 16 Bits Versus 24 Bits , these devices. 1.1 16 Bits Versus 24 Bits The DSP56300 core is a 24 -bit architecture, so arithmetic operations process 24 -bit operands and produce 24 -bit results. The SC140 core is a 16-bit architecture that , DSP56300 word is 24 bits, but an SC140 word is 16 bits. Both cores support double-precision operations , default 24 -bit architecture of the DSP56300 core is used, you must remember that SC140 is a 16


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PDF DSP56300 SC140/SC1400 DSP56300-based SC140based DSP56300 SC140 SC140 23/ANSC140VIT/D SC1400 MSC8101 MSC7119 MSC7118 MSC7116 DSP56F800 AN2715
DSP56300

Abstract: ASR16 DSP56100 DSP56302 DSP56303 DSP56600
Text: DSP56300/600 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 , parallel with accesses to Y memory. The instruction width on the DSP56300/600 is 24 bits as opposed to 16 , is a 16-bit machine while the DSP56300 is a 24 -bit machine. To generate bit-exact output using a , U). The modes common to both are marked with B . Hence, there are sufficient options on the DSP56300 , Register U B B Address Register Rn - - - B Address Modifier Register Mn - - U


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PDF APR22/D DSP56100 DSP56300/600 DSP56600 DSP56300/600 DSP56300 ASR16 DSP56302 DSP56303
2004 - DSP56300

Abstract: AN2208 saturation instructions DSP56300-hardware SC1400 SC140 MSC8101 DSP56F800 DSP56321 BUT15
Text: eor y0, b Freescale Semiconductor, Inc. DSP56300 24 -bit precision code: eor d6,d7 The , Scheiwe CONTENTS 1 Core Architectures Compared . 1 1.1 16 Bits Versus 24 Bits . 1 , 16 Bits Versus 24 Bits The DSP56300 core is a 24 -bit architecture, so arithmetic operations process 24 -bit operands and produce 24 -bit results. The SC140 core is a 16-bit architecture that operates on , word is 24 bits, but an SC140 word is 16 bits. Both cores support double-precision operations. The


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PDF AN2715/D DSP56300 SC140/SC1400 DSP56300-bthorized Suite56 AN2715/D, AN2208 saturation instructions DSP56300-hardware SC1400 SC140 MSC8101 DSP56F800 DSP56321 BUT15
1999 - DSP56300

Abstract: AN1829 AN1830 DSP56000 DSP56002 DSP56303 DSP56002 instruction set
Text: -bit immediate short ;#iiiiii is 24 -bit immediate long ASL D A, B ;D is destination accumulator ASL , , ;X1, Y1 ;D is destination accumulator A, B MACI (+/-)#iiiiii,S,D ;#iiiiii is 24 -bit immediate , is destination accumulator A, B MACRI (+/-)#iiiiii,S,D ;#iiiiii is 24 -bit immediate long data , ;#iiiiii is 24 -bit immediate CLB S,D B ;S is source accumulator A, ;D is destination accumulator , -bit short immediate data or a 24 -bit long immediate data and a source accumulator. LSL D A, B ;D is


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PDF AN1829 DSP56002 DSP56303 DSP56303 DSP56303. AN1830, DSP56303, DSP56300 AN1829 AN1830 DSP56000 DSP56002 instruction set
2004 - AN2208

Abstract: saturation instructions SC1400 SC140 MSC8101 DSP56F800 DSP56321 DSP56300 AN2715 AN220
Text: 2 16 Bits Versus 24 Bits . 2 Endianness and Bit Ordering , 24 Bits The DSP56300 core is a 24 -bit architecture, so arithmetic operations process 24 -bit operands and produce 24 -bit results. The SC140 core is a 16-bit architecture that operates on 16-bit operands. This change in operand size affects memory requirements and precision. A DSP56300 word is 24 bits, but , a 16-bit core with the same level of precision as the SC140 core. However, if the default 24


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PDF AN2715 DSP56300 SC140/SC1400 DSP56300-based SC140based DSP56300 SC140 SC140 AN2208 saturation instructions SC1400 MSC8101 DSP56F800 DSP56321 AN2715 AN220
1996 - DSP56300 Family Manual

Abstract: B445 SBC 1386 EX DSP56300FM DSP56300 finite impulse response DSP56300 semiconductor manual MARKING KN1 DDR pinout A-20
Text: xi Contents B .11 B .12 B .13 B .14 B .15 B .16 B .17 B .18 B .19 B .20 B .21 B .22 B .23 B.24 , DSP56300 Family Manual 24 -Bit Digital Signal Processors DSP56300FM Rev. 5, April 2005 How , Programs B From CDR Process to HiP Process C Index INDEX 1 Introduction 2 Core , Restrictions B Benchmark Programs C From CDR Process to HiP Process INDEX Index Contents , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Normal Processing State . . . . . .


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PDF DSP56300 24-Bit DSP56300FM CH370 Shimo-Megu23 Index-13 Index-14 DSP56300 Family Manual B445 SBC 1386 EX DSP56300FM DSP56300 finite impulse response semiconductor manual MARKING KN1 DDR pinout A-20
ASR16

Abstract: DSP56100 DSP56300 DSP56302 DSP56303 DSP56600
Text: . . . . . . . . . . . . . . . 2-4 Table 2-2 DSP56100, DSP56300, and DSP56600 Instruction Set , parallel with accesses to Y memory. The instruction width on the DSP56300/600 is 24 bits as opposed to 16 , is a 16-bit machine while the DSP56300 is a 24 -bit machine. To generate bit-exact output using a , that are unsupported (marked with a U). The modes common to both are marked with B . Hence, there are , Semiconductor, Inc. S C D A Data or Control Register U B B Address Register Rn -


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PDF APR22/D DSP56100 DSP56300/600 DSP56600 DSP56300/600 ASR16 DSP56300 DSP56302 DSP56303
DSP56300 finite impulse response

Abstract: iir filter diagrams real world applications of msp timer peripheral DSP56300
Text: Chapter 1 Overview This manual describes the DSP56311 24 -bit digital signal processor (DSP), its , B , Programming Reference - Peripheral addresses, interrupt addresses, and interrupt priorities for , Motorola's popular DSP56000 core family), a barrel shifter, 24 -bit addressing, instruction cache, and DMA , pipelined 24 24 -bit parallel multiplier-accumulator s Bit field unit, comprising a 56-bit parallel , instructions s Software-controllable 24 -bit, 48-bit, or 56-bit arithmetic support s Four 24 -bit or


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PDF DSP56311 24-bit DSP56300 DSP56300FM/AD) DSP56311 DSP56311/D DSP56300 finite impulse response iir filter diagrams real world applications of msp timer peripheral
74LS45

Abstract: No abstract text available
Text: added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24 , Chapter 1 Overview This manual describes the DSP56301 24 -bit digital signal processor (DSP), its , code for the DSP56301. s Appendix B , Programming Reference Peripheral addresses, interrupt , pipelined 24 x 24 -bit parallel multiplier-accumulator (MAC) - 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) - Conditional ALU instructions - 24 -bit or


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PDF DSP56301 24-bit DSP56300 DSP56300FM/AD) DSP56301/D DSP56301. 74LS45
CACHE MEMORY FOR core i7

Abstract: DSP56000 DSP56300 DSP56301 DSP56302 DSP56303 DSP56305 DSP56600 DSP56602
Text: iterations. Freescale Semiconductor, Inc. clr b #0,x0 do tst jne enddo # 24 ,_END_LOOP , THE MAX INSTRUCTION . . . . . . . . . . . . . . . 2-7 2.4 USING THE BARREL SHIFTER . . . . . . . . . , .7-8 B -1 B -1 B -2 B -3 APPENDIX C USING THE PROFILER . . . . . . . . . C.1 SCOPE . . . . . . . , -2 A-3 APPENDIX B DEBUG AND TEST SUPPORT. . . . B .1 ONCE PORT FEATURES . . . . . . . . . . . . . . . B .2 JTAG PORT FEATURES. . . . . . . . . . . . . . . . B .3 ADDRESS TRACING . . . . . . . . . .


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PDF APR20/D DSP56300/DSP56600 DSP56300 DSP56600 DSP56000 CACHE MEMORY FOR core i7 DSP56000 DSP56301 DSP56302 DSP56303 DSP56305 DSP56602
2004 - ASR16

Abstract: DSP56100 DSP56300 DSP56302 DSP56600
Text: Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Table 2-2 , width on the DSP56300/600 is 24 bits as opposed to 16 bits on the DSP56100. If an application will , a 24 -bit machine. To generate bit-exact output using a DSP56300 family part, 16-bit Arithmetic mode , Modes than those that are unsupported (marked with a U). The modes common to both are marked with B , B B Address Register Rn - - - B Address Modifier Register Mn - - U Address


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PDF APR22/D DSP56100 DSP56300/600 CH370 DSP56600 DSP56300/600 ASR16 DSP56300 DSP56302
18 x 16 barrel shifter

Abstract: design of 18 x 16 barrel shifter block diagram for barrel shifter DSP56300
Text: Advance Information 24 -BIT DIGITAL SIGNAL PROCESSOR The DSP56303 is a member of the DSP56300 core family , DSP56300 core family include a barrel shifter, 24 bit addressing, instruction cache, and DMA. The DSP56303 , Expansion Area Program RAM Triple Tim er Host Interface H I08 4096 x 24 ESSI Interface SCI Interface or (3 072 x 2 4 and Instruction C ache 1024x24) X D ata RAM 2 0 4 8 x 24 Y D ata RAM 2048 x 24 I , External Address Bus Switch External Bus Interface 18 ADDRESS 24 -Bit DSP56300 Core DDB YDB 13


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PDF DSP56303P/D DSP56303 24-BIT DSP56303 DSP56300 DSP56000 18 x 16 barrel shifter design of 18 x 16 barrel shifter block diagram for barrel shifter
1996 - XC56156FE60

Abstract: XC56004FJ50 XC56001AFC27 XC96002RC40 XC56004 XC96002RC33 xc56001 FIR CODE FOR 8051 IN ASSEMBLY LANGUAGE XC56L811BU40 xc56156
Text: Processors . . . . 2.1­3 DSP56300-24-Bit Digital Signal Processors . . . . 2.1­5 DSP56600-16-Bit Digital , ROM-based in 80-pin QFP XC56009PV80 80 MHz ROM-based in 80-pin QFP DSP56300-24-Bit Digital Signal , DSP56300-24-Bit Digital Signal Processors (continued) DSP56301 Features 52 6 6 3 Memory , Selection Guide DSP56300-24-Bit Digital Signal Processors (continued) · Up to forty-two programmable , Digital Signal Processors DSP56300-24-Bit Digital Signal Processors (continued) DSP56302 Features


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PDF DSP56100--16-Bit DSP56800--16-Bit DSP56000--24-Bit DSP56300--24-Bit DSP56600--16-Bit DSP96002--32-Bit DSP56ADC16--The DSP96000 DSP56000 DSP56KCCAJ XC56156FE60 XC56004FJ50 XC56001AFC27 XC96002RC40 XC56004 XC96002RC33 xc56001 FIR CODE FOR 8051 IN ASSEMBLY LANGUAGE XC56L811BU40 xc56156
1996 - 0J17D

Abstract: DSP56300 DSP56309 ED15 ED17 ED20 DSP56300 Family Manual
Text: . Separate these two consecutive moves by any other instruction. b . Split XY Data Move to two moves. Pertains to: DSP56300 Family Manual, Section B -5 "Peripheral pipeline restrictions. Description (added 5 , . Pertains to: DSP56300 Family Manual, Appendix B , Section B .4.1.3 DSP56309 Errata © 1996-1999 Motorola , options)} This is not a bug but a documentation update (Appendix B , DSP56300 Family Manual). , Description (added 11/ 24 /98): 0J17D In the Technical Datasheet Voh-TTL should be listed at 2.4 Volts


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PDF DSP56309 0J17D lint563" 0J17D DSP56300 ED15 ED17 ED20 DSP56300 Family Manual
16 bit full adder

Abstract: K-192
Text: or B accumulator. A 56-bit result can be stored as a 24 -bit operand. The LSP can either be truncated , 24 -bit Digital Signal Processor (DSP), its memory, operating modes, and peripheral modules. The , -ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI) ­ Describes the 24 -bit Enhanced Synchronous Serial Interface (ESSI , Interface (SPI) SECTION 8-SERIAL COMMUNICATIONS INTERFACE (SCI) ­ Describes the 24 -bit Serial , . Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24


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PDF DSP56304 DSP56304UM/AD DSP56300 16 bit full adder K-192
2004 - DSP563XX architecture

Abstract: AN1764 DSP56309UM EB343 DSPCOMMPARALLEL 1F90S AN2277 DSP56xxx architecture SC1400 292 MAPBGA
Text: Freescale Freescale > Digital Signal Processors > DSP56300 > DSP56309 DSP56309 : 24 -bit Digital Signal , code compatible with the DSP56000 core Highly parallel instruction set Fully pipelined 24 x 24 -bit parallel multiplier-accumulator (MAC) 56-bit parallel barrel shifter 24 -bit or 16-bit arithmetic support , data RAM, and Y data RAM size is programmable: Program RAM 24576 x 24 -bit 23552 x 24 -bit Instruction Cache 0 1024 x 24 -bit X Data RAM 5120 x 24 -bit 5120 x 24 -bit Y Data RAM 5120 x 24 -bit 5120 x


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PDF DSP56309 DSP56300 DSP56309 24-bit DSP56300 Suite56 DSP563XX architecture AN1764 DSP56309UM EB343 DSPCOMMPARALLEL 1F90S AN2277 DSP56xxx architecture SC1400 292 MAPBGA
2004 - core i3 addressing modes

Abstract: DSP56000 DSP56300 DSP56301 DSP56302 DSP56303 DSP56305 DSP56600 DSP56602
Text: Semiconductor, Inc. clr b #0,x0 do tst jne enddo # 24 ,_END_LOOP a _CONT _CONT lsr addc , THE MAX INSTRUCTION . . . . . . . . . . . . . . . 2-7 2.4 USING THE BARREL SHIFTER . . . . . . . . . , . . . . . . . . . . . . . . . . . .7-8 B -1 B -1 B -2 B -3 APPENDIX C USING THE PROFILER . . . , A-1 A-1 A-1 A-2 A-2 A-3 APPENDIX B DEBUG AND TEST SUPPORT. . . . B .1 ONCE PORT FEATURES . . . . . . . . . . . . . . . B .2 JTAG PORT FEATURES. . . . . . . . . . . . . . . . B .3 ADDRESS


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PDF APR20/D DSP56300/DSP56600 DSP56300 DSP56600 DSP56000 core i3 addressing modes DSP56000 DSP56301 DSP56302 DSP56303 DSP56305 DSP56602
DSP56000

Abstract: DSP56000 users manual DSP56602 DSP56600 DSP56305 DSP56303 DSP56302 DSP56301 DSP56300 relay cross reference
Text: , terminating if the register turns 0 before the full 24 iterations. clr b #0,x0 do tst jne enddo # 24 ,_END_LOOP a _CONT _CONT lsr addc _END_LOOP a x0, b Bit 0 of the result (B1) could be , . . . . . 2-6 2.3 THE MAX INSTRUCTION . . . . . . . . . . . . . . . 2-7 2.4 USING THE BARREL , A.2 DISABLING FUNCTIONAL BLOCKS . . . . . . APPENDIX B DEBUG AND TEST SUPPORT. . . . B .1 ONCE PORT FEATURES . . . . . . . . . . . . . . . B .2 JTAG PORT FEATURES. . . . . . . . . . . . . . . . B


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PDF APR20/D DSP56300/DSP56600 DSP56300 DSP56600 DSP56000 DSP56000 DSP56000 users manual DSP56602 DSP56305 DSP56303 DSP56302 DSP56301 relay cross reference
16 bit full adder

Abstract: ASPC3
Text: or B accumulator. A 56-bit result can be stored as a 24 -bit operand. The LSP can either be truncated , 24 -bit Digital Signal Processor (DSP), its memory, operating modes, and peripheral modules. The , -ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI) ­ Describes the 24 -bit Enhanced Synchronous Serial Interface (ESSI , Interface (SPI) SECTION 8-SERIAL COMMUNICATIONS INTERFACE (SCI) ­ Describes the 24 -bit Serial , architectural enhancements to the DSP56300 core family include a barrel shifter, 24 -bit addressing, an


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PDF DSP56302 DSP56302UM/AD DSP56300 16 bit full adder ASPC3
1999 - DSP56300

Abstract: DSP56303PV80 APR27 AT28C16-25 DSP56000 DSP56301 DSP56303 QS3245 512Kx8-bit
Text: (EPROM) with the Freescale DSP56300 family of DSPs. This document supplements the DSP56300 24 , 24 -Bit Digital Signal Processor Family Manual, user and technical data manuals, and AMD EPROM and , .18 Erasable Programmable Read-Only Memory .27 128K × 24 -Bit Boot, P, X' and Y EPROM Example , Family DSP56300 Family The DSP56300 family of DSPs uses a programmable 24 -bit fixed-point core , expansion bus. The main features of the DSP56300 core include: · Modified Harvard architecture with 24


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PDF DSP56300 24-Bit 24-Bit DSP56301, DSP56303 DSP56303PV80 APR27 AT28C16-25 DSP56000 DSP56301 DSP56303 QS3245 512Kx8-bit
1999 - DSP56300 Family Manual

Abstract: DSP96002 DSP56300 B126
Text: . . . . . . . . . . . . . B-24 FIR Lattice Filter . . . . . . . . . . . . . . . . . . . . . . . . . , DSP56300 Family Manual 24 -Bit Digital Signal Processor DSP56300FM/AD Revision 2.0, August 1999 , . . . . . . . . . . 7-5 7.1.4.1 EXTEST ( B [3 ­ 0] = 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.1.4.2 SAMPLE/PRELOAD ( B [3 ­ 0] = 0001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.1.4.3 IDCODE ( B [3 ­ 0] = 0010) . . . . . . . . . . . . .


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PDF DSP56300 24-Bit DSP56300FM/AD Index-13 DSP56300 Family Manual DSP96002 B126
2004 - ASR16

Abstract: DSP56100 DSP56300 DSP56303 DSP56600
Text: . . . . . . . . . . . . . . . . . 2-4 Table 2-2 DSP56100, DSP56300, and DSP56600 Instruction , parallel with accesses to Y memory. The instruction width on the DSP56300/600 is 24 bits as opposed to 16 , is a 16-bit machine while the DSP56300 is a 24 -bit machine. To generate bit-exact output using a , marked with B . Hence, there are sufficient options on the DSP56300/600 to work around the unsupported , Register U B B Address Register Rn - - - B Address Modifier Register Mn - - U


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PDF APR22/D DSP56100 DSP56300/600 DSP56303 DSP56600 DSP56300/600 DSP56600 ASR16 DSP56300 DSP56303
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