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Part Manufacturer Description Datasheet Download Buy Part
CX7297-011 TE Connectivity (CX7297-011) MXSB-24B/1XU-2XU
CJ7360-005 TE Connectivity (CJ7360-005) CSJA-24B/1XU-1XU-M
CJ7360-011 TE Connectivity (CJ7360-011) CSJA-24B/1XU-1XU-M
CJ7356-011 TE Connectivity (CJ7356-011) CSJA-24B/1XU-1XU
CX7297-005 TE Connectivity (CX7297-005) MXSB-24B/1XU-2XU
CAW-1C-24B (1617087-1) TE Connectivity (1617087-1) CAW-1C-24B = HALF.10A.1 POLE.2

DSP56000--24-B Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
DSP56001 users manual

Abstract: ADI1290 DSP56000 DSP56001 PB10 PB12
Text: I/O (Ports B and C) ­ Host Interface ­ Serial Communication Interface (SCI) ­ Synchronous Serial , B OR HOST ADDRESS GENERATION UNIT PAB Y MEMORY RAM 256x24 ROM 256x24 ROM , -BIT ACCUMULATORS PROGRAM CONTROL UNIT XTAL 16 BITS MODB/IRQB MODA/IRQA RESET EXTAL 24 BITS Figure 2-1 DSP56000 Block Diagram YAB PORT B OR HOST ADDRESS GENERATION UNIT 15 9 , ACCUMULATORS PROGRAM CONTROL UNIT XTAL EXTAL MODB/IRQB MODA/IRQA RESET 16 BITS 24 BITS


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PDF DSP56000/DSP56001 DSP56001 users manual ADI1290 DSP56000 DSP56001 PB10 PB12
1995 - ADI1290

Abstract: DSP56000 DSP56001 PB10 PB12 DSP56001 host port
Text: · Input/Output: ­ Memory Expansion (Port A) ­ General-Purpose I/O (Ports B and C) ­ Host , component. MOTOROLA DSP56000/DSP56001 USER'S MANUAL 2-1 YAB PORT B OR HOST ADDRESS , CONTROL UNIT XTAL 16 BITS MODB/IRQB MODA/IRQA RESET EXTAL 24 BITS Figure 2-1 DSP56000 Block Diagram YAB PORT B OR HOST ADDRESS GENERATION UNIT 15 ON-CHIP PERIPHERALS HOST , EXTAL MODB/IRQB MODA/IRQA RESET 16 BITS 24 BITS Figure 2-2 DSP56001 Block Diagram 2-2


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PDF DSP56000/DSP56001 ADI1290 DSP56000 DSP56001 PB10 PB12 DSP56001 host port
IN5711

Abstract: ADI1290 dsp56001 DSP560000 mc6801-type PB12 PB10 BD13 BD12 BD10
Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. SECTION 10 PORT B Port B is a , general-purpose I/O, port B can be used for device control. When configured as the HI, port B provides a convenient connection to another processor. This section describes both port B configurations, including , ADDRESS SWITCH EXTERNAL DATA SWITCH A0 - A15 - D0 - D23 - 24 PORT A I/0 (47 , ) TXD PC2 PC6 SCI INTERFACE RXD PC1 PORT B I/0 (15) H0 - H7 HA0 HA1 HA2 HR


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PDF DSP56000/DSP56001 IN5711 ADI1290 dsp56001 DSP560000 mc6801-type PB12 PB10 BD13 BD12 BD10
advantages Mobile Controlled Robot using DTMF

Abstract: voice control robot circuits diagram Mobile Controlled Robot using DTMF applications DSP56000 fast fourier transforms DSP56001 users manual circuit diagram for RF based robot DSP56000 DSP56000 DATASHEET analog dtmf control robot circuits diagram voice controlled mobile robot
Text: . · Precision - The data paths are 24 bits wide, providing 144 dB of dynamic range; intermediate , unit (AGU, program control unit, data ALU), YAB PORT B OR HOST ADDRESS GENERATION UNIT , ACCUMULATORS PROGRAM CONTROL UNIT MODB/IRQB MODA/IRQA RESET 16 BITS 24 BITS Figure 1-4 DSP56000 , . The data ALU, AGUs, and program control unit operate in parallel so that an instruction prefetch, a 24 -bit x 24 -bit multiplication, a 56-bit addition, two data moves, and two address-pointer updates using


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PDF DSP56001 DSP56000 DSP56000/DSP56001 advantages Mobile Controlled Robot using DTMF voice control robot circuits diagram Mobile Controlled Robot using DTMF applications DSP56000 fast fourier transforms DSP56001 users manual circuit diagram for RF based robot DSP56000 DATASHEET analog dtmf control robot circuits diagram voice controlled mobile robot
1995 - 8 bit adder

Abstract: DSP56000 DSP56001 "saturation arithmetic"
Text: to the 56-bit accumulators A or B with a 48- or 24 -bit operand. When a 24 -bit operand is written , - One 24 bit Y Y:A Y: B + - - - 7FFFFF 800000 One 24 bit X and Y X:A , 800000 7FFFFF 800000 7FFFFF 800000 7FFFFF 800000 Two 24 bit L (X:Y) 4-8 X:A X: B L , than bus YAB PORT B OR HOST ADDRESS GENERATION UNIT 15 PAB BOOTSTRAP ROM 32x24 , CONTROL UNIT MODB/IRQB MODA/IRQA RESET 16 BITS 24 BITS Figure 4-1 DSP56001 Block Diagram


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PDF DSP56000/DSP56001 32x24 256x24 24-bit 56-bit 8 bit adder DSP56000 DSP56001 "saturation arithmetic"
1995 - ADI1290

Abstract: DSP56001 MBD301 MC6800 MC68000
Text: memories/devices, and multiple bus master systems. The port A data bus is 24 bits wide with a separate 16 , ). External memory is divided into three 64K-word X 24 -bit spaces ­ X:, Y:, and P:. An internal , BUS SWITCH EXTERNAL ADDRESS BUS A0 - A15 PROGRAM ADDRESS (PA) 24 - BIT INTERNAL DATA BUSES X DATA (XD) 24 Y DATA (YD) EXTERNAL DATA BUS D0 - D23 EXTERNAL DATA BUS SWITCH , MOTOROLA VCC +5 V VSS GROUND 16 ADDRESS BUS A0 - A15 PROGRAM MEMORY ADDRESS 24 DATA


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PDF 16-bit 64K-word 24-bit DSP56000/DSP56001 DSP56000 DSP56000/ DSP56001 ADI1290 DSP56001 MBD301 MC6800 MC68000
1995 - Mobile Controlled Robot using DTMF applications

Abstract: voice control robot circuits diagram advantages Mobile Controlled Robot using DTMF voice controlled mobile robot Servo motor based mobile robot control RF CONTROLLED ROBOT DSP56000 fast fourier transforms DSP56001 DSP56001 programming viterbi convolution
Text: . · Precision - The data paths are 24 bits wide, providing 144 dB of dynamic range; intermediate , unit (AGU, program control unit, data ALU), YAB PORT B OR HOST ADDRESS GENERATION UNIT , CONTROL UNIT MODB/IRQB MODA/IRQA RESET 16 BITS 24 BITS Figure 1-4 DSP56000 Block Diagram 1-8 , unit operate in parallel so that an instruction prefetch, a 24 -bit x 24 -bit multiplication, a 56 , features: 12-word x 24 -bit, on-chip program RAM instead of 3.75K program ROM 32-word x 24 -bit bootstrap


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PDF DSP56001 DSP56000 DSP56000/DSP56001 Mobile Controlled Robot using DTMF applications voice control robot circuits diagram advantages Mobile Controlled Robot using DTMF voice controlled mobile robot Servo motor based mobile robot control RF CONTROLLED ROBOT DSP56000 fast fourier transforms DSP56001 programming viterbi convolution
circuit diagram of pid controller

Abstract: mc68hc99 DSP56000 users manual DSP56ADC16 DSP56000 motorola temperature control using pid controller APR5 DC-101 transistor SMD making code GC DSP56000
Text: (tr), Settling Time (ts), Percent Overshoot, and Steady-State Error (ess) 2-4 General Feedback , ) P Controller, ( b ) PD Controller, and (c) PID Controller 3-3 Output, c(t), Error, e(t), and , Controller via the Port B I/O Lines 8-10 Using External Interrupts to Provide Velocity-Feedback , is both a high-speed microcontroller and a powerful DSP. The DSP56001 has 512 24 -bit words of , high-volume products, the DSP56000 offers 3.75K 24 -bit words of program ROM, which can be factory programmed


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PDF DSP56000/SPS/DSP56001 DSP56000/DSP56001 circuit diagram of pid controller mc68hc99 DSP56000 users manual DSP56ADC16 DSP56000 motorola temperature control using pid controller APR5 DC-101 transistor SMD making code GC DSP56000
1994 - RF transmitter and Receiver circuit for robot con

Abstract: HALL EFFECT 21l video player circuit diagram DSP5001 Rf controlled robot using 8051 microcontroller 10244 Motorola scr DSP56001 HALL sensor 21l audio procesor line following robot diagram 8051
Text: /IRQA RESET EXTAL 24 BITS Figure 2-1 DSP56000 Block Diagram YAB PORT B OR HOST , DSP56001 24 -BIT DIGITAL SIGNAL PROCESSOR USER'S MANUAL Motorola, Inc. Semiconductor Products , . · Precision - The data paths are 24 bits wide, providing 144 dB of dynamic range; intermediate , unit (AGU, program control unit, data ALU), YAB PORT B OR HOST ADDRESS GENERATION UNIT , CONTROL UNIT MODB/IRQB MODA/IRQA RESET 16 BITS 24 BITS Figure 1-4 DSP56000 Block Diagram 1-8


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PDF DSP56001 24-BIT DSP56001 DSP56000 DSP56000/DSP56001 RF transmitter and Receiver circuit for robot con HALL EFFECT 21l video player circuit diagram DSP5001 Rf controlled robot using 8051 microcontroller 10244 Motorola scr HALL sensor 21l audio procesor line following robot diagram 8051
1995 - BD10

Abstract: BD12 BD13 PB10 PB12
Text: SECTION 10 PORT B Port B is a dual-purpose I/O port that can be used as 1) 15 general-purpose , interface (HI) (see Figure 10-1). When configured as general-purpose I/O, port B can be used for device control. When configured as the HI, port B provides a convenient connection to another processor. This section describes both port B configurations, including examples of how to configure and use the port , A15 - D0 - D23 - 24 PORT A I/0 (47) - - - - - - - PS DS X/Y RD


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PDF DSP56000/DSP56001 BD10 BD12 BD13 PB10 PB12
ADSP-2111

Abstract: DSP56000 2111-1N design of 18 x 16 barrel shifter in computer DSP56166 DSP56001 ADSP-2105 ADSP-2100A ADSP-2100 BUT21
Text: via the Result Bus, which 24 Bits I Program Memory Data Bus -/ I I / , Ài. ik À k , processor. The Data ALU contains four 24 -bit input registers, a multiply-accumulator/logic unit (MAC), two , B accumulators. Because all DSP56000 computational operations share common input and output , :LSP). When a 56-bit result is to be stored as a 24 -bit operand, the LSP can either be truncated or rounded into the MSP. In order to protect against overflows, accumulation registers A and B each have


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PDF AN-231 ADSP-2111 DSP56166) ADSP-2105 ADSP-2111, ADSP-2100 ADSP-2100A, ADSP-2101) DSP56000 2111-1N design of 18 x 16 barrel shifter in computer DSP56166 DSP56001 ADSP-2100A BUT21
ADI1290

Abstract: DSP56001 FFT DSC freescale EWS300-24 instruction manual
Text: the instruction ( B ,X:(R1)+X0, B ) moves the 24 -bit limited value of B ($800000) into the X:$1234 memory , , B ,X1 Y:(R6)­N6, B , moves the 24 -bit limited negative saturation constant $800000 into the X1 , address register to move the 24 -bit value in the Y memory location Y:$2020 into the 56-bit B accumulator , move Note: The MOVE A,X: B ,Y: operation will result in one or two 24 -bit positive and/or , modes may be used. Example: : RND B (R3)+N3;round value in B into B1, R3+N3©R3 : Before Execution


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PDF 16-bit DSP56000/DSP56001 ADI1290 DSP56001 FFT DSC freescale EWS300-24 instruction manual
DSP56001

Abstract: 56001 DSP56001 users manual DSP56000 000E-6
Text: B (A0 or B0) by loading the 24 -bit operand into X0 or Y0, forming a 48-bit word by loading X1 or , , B2, B1, B0, A, and B . The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR , X1 or X0 ( 24 Bits) Yn Input Register Y1 or Y0 ( 24 Bits) An Accumulator Registers A2, A1, A0 (A2 - 8 Bits, A1 and A0 - 24 Bits) Bn Accumulator Registers B2, B1, B0 (B2 - 8 Bits, B1 and B0 - 24 Bits) X Freescale Semiconductor, Inc. Xn Input Register X = X1: X0 (48 Bits


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PDF DSP56000/ DSP56001 DSP56000/DSP56001 56001 DSP56001 users manual DSP56000 000E-6
ADI1290

Abstract: rom 2716 DSP56001 users manual DSP56001 MBD301 MC6800 MC68000
Text: master systems. The port A data bus is 24 bits wide with a separate 16-bit address bus capable of a , divided into three 64K-word X 24 -bit spaces ­ X:, Y:, and P:. An internal wait-state generator can be , A15 Freescale Semiconductor, Inc. PROGRAM ADDRESS (PA) 24 - BIT INTERNAL DATA BUSES X DATA (XD) 24 Y DATA (YD) EXTERNAL DATA BUS D0 - D23 EXTERNAL DATA BUS SWITCH PROGRAM , , Inc. VCC +5 V VSS GROUND 16 ADDRESS BUS A0 - A15 PROGRAM MEMORY ADDRESS 24 DATA


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PDF 16-bit 64K-word 24-bit DSP56000/DSP56001 ADI1290 rom 2716 DSP56001 users manual DSP56001 MBD301 MC6800 MC68000
1995 - ADI1290

Abstract: DSP56001 EWS300-24 instruction manual
Text: move portion of the instruction ( B ,X:(R1)+X0, B ) moves the 24 -bit limited value of B ($800000) into the , parallel move portion of the instruction, B ,X1 Y:(R6)­N6, B , moves the 24 -bit limited negative saturation , moves the 24 -bit limited value of B ($7FFFFF) into the Y:$1234 memory location and increments R1 to , the specified 24 -bit X and/or Y memory location(s) if the signed integer portion of the A and/or B , addressing mode. All update addressing modes may be used. Example: : RND B (R3)+N3;round value in B into


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PDF 16-bit DSP56000/DSP56001 ADI1290 DSP56001 EWS300-24 instruction manual
MC68HC99

Abstract: active noise cancellation DSP56000 PID DSP56001 scr fs04 deadbeat control deadbeat "vector instructions" saturation MC68000 MC68HC11
Text: 6.5 All bj(0) Coefficients are 1; b |(1), ^(2)^(1), and ^(2) Coefficients are Fractional 6-14 6.6 , Include Rise Time {%), Settling Time (y, Percent Overshoot, and Steady-State Error (ess) 2-4 Figure 3-1 , Feedback System Shown for a (a) P Controller, ( b ) PD Controller, and (c) PID Controller 3-3 Figure 3-3 , the DSP56000/DSP56001 to the MC68HC99 Disk Drive Controller via the Port B I/O Lines 8-10 Figure 8-8 , DSP56000/DSP56001 is both a high-speed microcontroller and a powerful DSP. The DSP56001 has 512 24


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PDF DSP56000/DSP56001 1ATX25217-4 MC68HC99 active noise cancellation DSP56000 PID DSP56001 scr fs04 deadbeat control deadbeat "vector instructions" saturation MC68000 MC68HC11
DSP56001 programming

Abstract: DSP56001 users manual DSP56000 DSP56001 "saturation arithmetic"
Text: 56 A (56) B (56) 56 56 SHIFTER/LIMITER 24 24 Figure 4-2 Data ALU MOTOROLA , extension is provided when writing to the 56-bit accumulators A or B with a 48- or 24 -bit operand. When a , bit Y Y:A Y: B + - - - 7FFFFF 800000 One 24 bit X and Y X:A Y:A X:A Y: B , 7FFFFF 800000 7FFFFF 800000 7FFFFF 800000 Two 24 bit L (X:Y) 4-8 X:A X: B L:A L: B , YAB PORT B OR HOST ADDRESS GENERATION UNIT 15 ON-CHIP PERIPHERALS HOST, SSI, SCI


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PDF DSP56000/DSP56001 56-bit DSP56001 programming DSP56001 users manual DSP56000 DSP56001 "saturation arithmetic"
1995 - 001C

Abstract: DSP56000 DSP56001
Text: loop counter (LC) dedicated to supporting the hardware DO loop instruction. YAB PORT B OR HOST , BITS 24 BITS Figure 6-1 DSP56001 Block Diagram MOTOROLA DSP56000/DSP56001 USER'S MANUAL , PDB 16 24 CLOCK PC LA LC SP INTERRUPTS CONTROL OMR 32 x 16 STACK SR 24 24 GLOBAL DATA BUS Figure 6-2 DSP56000/DSP56001 Program Control Unit during subroutine calls , none of the program control unit registers are 24 bits, they are read or written over 24 -bit buses


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PDF DSP56000/DSP56001. DSP56000/DSP56001 001C DSP56000 DSP56001
DSP56000

Abstract: DSP56001 users manual 001C DSP56001 32X24
Text: hardware DO loop instruction. YAB PORT B OR HOST 15 ON-CHIP PERIPHERALS HOST, SSI, SCI , ACCUMULATORS PROGRAM CONTROL UNIT MODB/IRQB MODA/IRQA RESET 16 BITS 24 BITS Figure 6-1 DSP56001 , -bit separate internal memory used to store the PC and SR PAB PDB 16 24 Freescale Semiconductor, Inc. CLOCK PC LA LC SP INTERRUPTS CONTROL OMR 32 x 16 STACK SR 24 24 , control unit registers are 24 bits, they are read or written over 24 -bit buses. When they are read, the


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PDF DSP56000/DSP56001 DSP56000 DSP56001 users manual 001C DSP56001 32X24
1995 - PB10

Abstract: PB12 8051 interfacing with 74HC165
Text: D0 - D23 - 24 PORT A I/0 (47) - - - - - - - PS DS X/Y RD WR BR/WT , - H7 HA0 HA1 HA2 HR/W HEN HREQ HACK PC0 PORT B I/0 (15) HOST/DMA PARALLEL , 0 0 0 0 0 0 0 0 0 0 PORT B DATA PD PD PD PD PD PD PD PD PD REGISTER , ) X:$FFED SSI CONTROL REGISTER B (CRB) X:$FFEC SSI CONTROL REGISTER A (CRA) X:$FFEB , PORT C - DATA REGISTER (PCD) X:$FFE4 PORT B - DATA REGISTER (PBD) X:$FFE3 PORT C - DATA


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PDF DSP56000/DSP56001 DSP56000/DSP56001 PB10 PB12 8051 interfacing with 74HC165
1995 - 16 bit full adder

Abstract: DSP56001 8 bit binary full adder
Text: 8 9 0 23 A B C D 0 A1 A0 55 48 47 0 7 1 2 0 23 24 23 3 4 5 , EXECUTION F 6 0 23 B2 24 23 5 4 3 2 B1 0 1 F 0 23 E D A 0 C B , EXECUTION X1 X0 47 A 5 23 X1 24 23 B 4 C 6 0 0 23 0 0 0 0 0 1 0 A 5 23 X0 47 24 23 B 4 C 0 0 0 0 1 0 X MEMORY X MEMORY 23 , 23 A2 24 23 1 0 5 0 A 3 0 23 F A 6 B 0 0 A1 A0 55 48 47 0


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PDF DSP56000/DSP56001 32x24 256x24 256x24RIGINAL 16 bit full adder DSP56001 8 bit binary full adder
1995 - EWS300-24 instruction manual

Abstract: No abstract text available
Text: X X X X X X X X X X X 7 0 23 0 23 0 B2 B1 B0 55 48 47 24 23 0 X X X X X X X X A B C D , 47 X X X 23 X0 24 23 0 X X X X X X X X X 0 23 0 X1 X0 47 24 23 0 0 0 0 0 0 1 A 5 B , A and B were rounded to 24 bits before moving to the 24bit memory registers. The DSP offers , A 55 # 23 8 7 0 23 0 23 0 B 55 # 0 B0 B1 B2 23 0 A0 A1 , 24 -bit words ­ an operation word and an optional effective address extension word. The general


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PDF DSP56000/DSP56001 EWS300-24 instruction manual
1995 - DSP56000

Abstract: DSP56001
Text: representation. Note that 24 -bit operands can be added to the LSP portion of A or B (A0 or B0) by loading the 24 , , B2, B1, B0, A, and B . The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR , X1 or X0 ( 24 Bits) Yn Input Register Y1 or Y0 ( 24 Bits) An Accumulator Registers A2, A1, A0 (A2 - 8 Bits, A1 and A0 - 24 Bits) Bn Accumulator Registers B2, B1, B0 (B2 - 8 Bits, B1 and B0 - 24 Bits) X Input Register X = X1: X0 (48 Bits) Y Input Register Y = Y1: Y0 (48


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PDF DSP56000/ DSP56001 DSP56000/DSP56001 DSP56000
DSP56001

Abstract: 32X24 16 bit full adder
Text: 8 9 0 23 A B C D 0 A1 A0 55 48 47 0 7 1 2 0 23 24 23 3 4 5 , 0 1 F 0 23 E D A 0 C B A 7 B0 55 48 47 F 6 0 23 24 23 5 4 3 , X0 47 A 5 23 X1 24 23 B 4 C 6 0 0 23 0 0 0 0 0 1 0 A 5 23 X0 47 24 23 B 4 C Freescale Semiconductor, Inc. 0 0 0 0 1 0 X , A0 55 48 47 0 7 F 7 4 0 23 A2 24 23 1 0 5 0 A 3 0 23 F A 6 B


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PDF DSP56000/DSP56001 DSP56001 32X24 16 bit full adder
Not Available

Abstract: No abstract text available
Text: EXECUTION A2 A1 A0 55 48 47 24 23 0 X X X X X X X X 1 2 3 4 5 6 7 0 23 0 23 0 EXAMPLE B , B1 B0 55 48 47 24 23 0 X X X X X X X X A B C D E F 7 0 23 0 23 0 Freescale , X X X X X 0 23 0 X1 X0 47 24 23 0 0 0 0 0 0 1 A 5 B 4 C 6 23 0 23 0 P MEMORY 23 , contents of the 56-bit registers A and B were rounded to 24 bits before moving to the 24bit memory , # Freescale Semiconductor, Inc. 0 B 55 0 B0 B1 B2 23 0 A0 A1 A2


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PDF DSP56000/DSP56001
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