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2009 - DSP48A1

Abstract: DSP48A1 UG389 UG389 XC6SL DSP48A1 post adder verilog code for 16 bit carry select adder 8 bit carry select adder verilog code XC6SLX150T verilog code for barrel shifter UG073
Text: upstream cascaded DSP48A1. If not used, tie port to all zeros. It should also be noted that the UNISIM , the downstream cascaded DSP48A1. If not used, this port should be left unconnected. Input 48 Cascade input for Port P. If used, connect to the PCOUT of the upstream cascaded DSP48A1. If not used , to the PCIN of the downstream cascaded DSP48A1. If not used, this port should be left unconnected , Spartan-6 FPGA DSP48A1 Slice User Guide [optional] UG389 (v1.1) August 13, 2009 [optional


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PDF DSP48A1 UG389 DSP48A1 UG389 UG389 XC6SL DSP48A1 post adder verilog code for 16 bit carry select adder 8 bit carry select adder verilog code XC6SLX150T verilog code for barrel shifter UG073
2009 - SPARTAN-6 GTP

Abstract: Spartan-6 PCB design guide Digital filter design for SPARTAN 6 FPGA vhdl code for 4 bit barrel shifter electrocardiogram DSP48A1 digital FIR Filter VHDL code fir filter spartan 3 verilog code for barrel shifter DSP48A
Text: upstream cascaded DSP48A1. If not used, tie port to all zeros. It should also be noted that the UNISIM , the downstream cascaded DSP48A1. If not used, this port should be left unconnected. Input 48 Cascade input for Port P. If used, connect to the PCOUT of the upstream cascaded DSP48A1. If not used , to the PCIN of the downstream cascaded DSP48A1. If not used, this port should be left unconnected , Spartan-6 FPGA DSP48A1 Slice User Guide [optional] UG389 (v1.0) June 24, 2009 [optional


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PDF DSP48A1 UG389 SPARTAN-6 GTP Spartan-6 PCB design guide Digital filter design for SPARTAN 6 FPGA vhdl code for 4 bit barrel shifter electrocardiogram digital FIR Filter VHDL code fir filter spartan 3 verilog code for barrel shifter DSP48A
2010 - XA6SLX45

Abstract: Spartan-6 FPGA iodelay XA6SLX75 XA6SLX16 UG381 Xa6SLX9 2FGG484 SPARTAN 6 UG385 Spartan-6 PCB design guide
Text: , second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks , and PCI Express Efficient DSP48A1 slices · High-performance arithmetic and signal processing · , Distributed RAM (Kb) Block RAM Blocks DSP48A1 Slices(3) CMTs(5) 18 Kb(4) Max (Kb) Memory , flip-flops. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator. Block RAMs are , size, while retaining system design flexibility. Each DSP48A1 slice consists of a dedicated 18 × 18


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PDF DS170 UG382) UG393) UG386) XA6SLX45 Spartan-6 FPGA iodelay XA6SLX75 XA6SLX16 UG381 Xa6SLX9 2FGG484 SPARTAN 6 UG385 Spartan-6 PCB design guide
2009 - virtex 6 fpga based image processing

Abstract: SPARTAN-6 image processing spartan 6 LX150t Xilinx Spartan-6 FPGA Kits DSP48A1 Digital filter design for SPARTAN 6 FPGA car central lock virtex 5 fpga based image processing PCIe Endpoint spi flash spartan 6
Text: , second-generation DSP48A1 · Integrated memory controller blocks enable streamlined access to video and data , cell ratio, a 2X increase in block RAM ports, 2X logic capability, 50% more DSP48A1 slices, six-input , SelectIOTM Interface Technology Multi-voltage, multi-standard SelectIO banks Up to 180 Efficient DSP48A1 , data at full frame rate using highly parallel implementations based on DSP48A1 slices · Implement


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2009 - xc6slx45 pinout

Abstract: DS160 xc6slx75t XC6SLX4 2 CSG225 I XC6SLX75 XC6SLX45 XC6SLX9 2 CSG225 I XC6SLX16 SPARTAN 6 DS162 ISERDES spartan 6
Text: system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory , support compatible with the 33 MHz, 32- and 64-bit specification. Efficient DSP48A1 slices · , Flip-Flops Distributed RAM (Kb) Block RAM Blocks DSP48A1 Slices(3) CMTs(5) 18 Kb(4) Max (Kb , eight flip-flops. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator , . Each DSP48A1 slice consists of a dedicated 18 × 18 bit two's complement multiplier and a 48


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PDF DS160 UG382) UG393) UG386) xc6slx45 pinout DS160 xc6slx75t XC6SLX4 2 CSG225 I XC6SLX75 XC6SLX45 XC6SLX9 2 CSG225 I XC6SLX16 SPARTAN 6 DS162 ISERDES spartan 6
2010 - LPDDR KINTEX 7

Abstract: SPARTAN-6 spartan6 ug384 XA6SLX75
Text: include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced , Efficient DSP48A1 slices • High-performance arithmetic and signal processing • Fast 18 x 18 , Logic Cells(1) Slices(2) Max Flip-Flops Distributed RAM (Kb) Block RAM Blocks DSP48A1 , architecture. Each XA Spartan-6 FPGA slice contains four LUTs and eight flip-flops. Each DSP48A1 slice , design flexibility. Each DSP48A1 slice consists of a dedicated 18 × 18 bit two’s complement


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PDF DS170 UG382) UG393) UG394) LPDDR KINTEX 7 SPARTAN-6 spartan6 ug384 XA6SLX75
2011 - XQ6SLX75T

Abstract: XQ6SLX150 XQ6SLX75 spartan 6 LX150 XQ6SLX150T SPARTAN 6 UG385 SPARTAN-6 GTP LX150T spartan 6 LX150t FG484
Text: built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices , support compatible with the 33 MHz, 32- and 64-bit specification. Efficient DSP48A1 slices · , Logic Cells(1) Slices(2) Max Flip-Flops Distributed RAM (Kb) Block RAM Blocks DSP48A1 , flip-flops. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator. Block RAMs are , size, while retaining system design flexibility. Each DSP48A1 slice consists of a dedicated 18 × 18


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PDF DS172 UG383) UG384) UG386) DSP48A1 UG389) XQ6SLX75T XQ6SLX150 XQ6SLX75 spartan 6 LX150 XQ6SLX150T SPARTAN 6 UG385 SPARTAN-6 GTP LX150T spartan 6 LX150t FG484
2009 - iodelay

Abstract: SPARTAN-6 GTP DSP48A1 SPARTAN 6 peripherals datasheet XC6SLX75 DS160 spi flash spartan 6 Spartan-6 PCB design guide XC6SLX25 UG381
Text: system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory , support compatible with the 33 MHz, 32- and 64-bit specification. Efficient DSP48A1 slices · , Flip-Flops Distributed RAM (Kb) Block RAM Blocks DSP48A1 Slices(3) CMTs(5) 18 Kb(4) Max (Kb , eight flip-flops. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator , with small size, while retaining system design flexibility. Each DSP48A1 slice consists of a


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PDF DS160 UG394) UG383) DS170) iodelay SPARTAN-6 GTP DSP48A1 SPARTAN 6 peripherals datasheet XC6SLX75 DS160 spi flash spartan 6 Spartan-6 PCB design guide XC6SLX25 UG381
2009 - Spartan-6 Family Overview

Abstract: Spartan-6 DS160 XC6SLX SPARTAN 6 UG385 CSG324 XC6SL XC6SLX150 spartan6 XC6slx45
Text: blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory , DSP48A1 slices · High-performance arithmetic and signal processing · Fast 18 x 18 multiplier and 48 , Distributed RAM (Kb) DSP48A1 Slices(3) Block RAM Blocks 18 Kb(4) CMTs(5) Max (Kb) Memory Endpoint Maximum , LUTs and eight flip-flops. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an , design flexibility. Each DSP48A1 slice consists of a dedicated 18 × 18 bit two's complement multiplier


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PDF DS160 DS172) UG388) UG393) Spartan-6 Family Overview Spartan-6 DS160 XC6SLX SPARTAN 6 UG385 CSG324 XC6SL XC6SLX150 spartan6 XC6slx45
2009 - UG380

Abstract: Spartan-6 PCB design guide XC6SLX45T XC6SLX25 lx25t XC6SLX150 XC6SLX45 XC6SLX100 spartan6 block ram iodelay
Text: system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory , support compatible with the 33 MHz, 32- and 64-bit specification. Efficient DSP48A1 slices · , ) Slices(2) Max Flip-Flops Distributed RAM (Kb) Block RAM Blocks DSP48A1 Slices(3) CMTs(5 , . Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops. Each DSP48A1 slice contains an 18 x , flexibility. Each DSP48A1 slice consists of a dedicated 18 × 18 bit two's complement multiplier and a 48


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PDF DS160 UG383) UG384) UG386) DSP48A1 UG389) UG380 Spartan-6 PCB design guide XC6SLX45T XC6SLX25 lx25t XC6SLX150 XC6SLX45 XC6SLX100 spartan6 block ram iodelay
2009 - SPARTAN 6 xc6slx45 pin configuration

Abstract: XC6SLX45 spartan 6 partial configuration Spartan-6 FPGA iodelay XC6SLX16 XC6SLX9 SPARTAN 6 xc6slx45 XC6SLX150 DS160
Text: system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory , - and 64-bit specification. Efficient DSP48A1 slices - High-performance arithmetic and signal , Cells(1) Slices(2) Max Flip-Flops Distributed RAM (Kb) Block RAM Blocks DSP48A1 Slices(3 , architecture. Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops. Each DSP48A1 slice contains , size, while retaining system design flexibility. Each DSP48A1 slice consists of a dedicated 18 × 18


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PDF DS160 UG382) UG393) UG386) SPARTAN 6 xc6slx45 pin configuration XC6SLX45 spartan 6 partial configuration Spartan-6 FPGA iodelay XC6SLX16 XC6SLX9 SPARTAN 6 xc6slx45 XC6SLX150 DS160
2009 - DS160

Abstract: SPARTAN 6 XC6SLX45T Spartan-6 FPGA spi flash spartan 6 XC6SLX45 XC6SLX75T xc6slx75 XC6SLX16 iodelay
Text: system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory , Efficient DSP48A1 slices - High-performance arithmetic and signal processing - Fast 18 x 18 multiplier and , Cells(1) Slices(2) Max Flip-Flops Distributed RAM (Kb) Block RAM Blocks DSP48A1 Slices(3 , . Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops. Each DSP48A1 slice contains an 18 x , , while retaining system design flexibility. Each DSP48A1 slice consists of a dedicated 18 × 18 bit two


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PDF DS160 UG382) UG393) UG386) DS160 SPARTAN 6 XC6SLX45T Spartan-6 FPGA spi flash spartan 6 XC6SLX45 XC6SLX75T xc6slx75 XC6SLX16 iodelay
2010 - SPARTAN 6 UG385

Abstract: XA6SLX16 XA6SLX100 iodelay FTG256 Spartan-6 PCB design guide XA6SLX4 XA6sLx25
Text: include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced , interfaces including: Serial ATA and PCI Express Efficient DSP48A1 slices · High-performance arithmetic and , ) Slices(2) Max Flip-Flops Distributed RAM (Kb) DSP48A1 Slices(3) Block RAM Blocks 18 Kb(4) CMTs(5) Max (Kb , contains four LUTs and eight flip-flops. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and , size, while retaining system design flexibility. Each DSP48A1 slice consists of a dedicated 18 × 18 bit


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PDF DS170 UG388) UG393) UG394) SPARTAN 6 UG385 XA6SLX16 XA6SLX100 iodelay FTG256 Spartan-6 PCB design guide XA6SLX4 XA6sLx25
2011 - DSP48E1

Abstract: XC6SLX16-2 XC7V585T-1 xilinx vhdl code for floating point square root fpga 4062 UG812 XC6VLX75-1 xilinx vhdl code for floating point square root o vhdl code of 32bit floating point adder XC6SLX16 FIT rate
Text: -6 FPGA Family Logic DSP48A1+logic (1) in multiplier body DSP48A1 used in multiplier body DSP48A1 , Multiplication Using DSP48A1 Fraction Width 4 to 17 18 to 34 (inc. single) 35 to 51 52 to 64 (inc. double) 1 , Using DSP48A1 Fraction Width single double Maximum Latency (clock cycles) No Usage 36 Full Usage , of Floating-Point Reciprocal Square Root Using DSP48A1 Fraction Width single Maximum Latency


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PDF DS816 ZynqTM-7000, DSP48E1 XC6SLX16-2 XC7V585T-1 xilinx vhdl code for floating point square root fpga 4062 UG812 XC6VLX75-1 xilinx vhdl code for floating point square root o vhdl code of 32bit floating point adder XC6SLX16 FIT rate
xc3s500e fg320

Abstract: xc3s1800a fgg 484 XC3S50A/AN VQ100 XC3S250E vqg100 XC3S400 PQ208 SPARTAN-3 XC3S400 pq208 architecture xc3s1600e fg320 CPG196 LVCMOS33
Text: 66 100 116 133 179 200 240 288 125 148 174 249 270 DSP48A1 , independent 9Kb blocks. Each CMT contains two DCMs and one PLL. Each DSP48A1 slice contains an 18x18


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PDF XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T XC6SLX100T xc3s500e fg320 xc3s1800a fgg 484 XC3S50A/AN VQ100 XC3S250E vqg100 XC3S400 PQ208 SPARTAN-3 XC3S400 pq208 architecture xc3s1600e fg320 CPG196 LVCMOS33
2011 - Not Available

Abstract: No abstract text available
Text: Device Xilinx Spartan-6 FPGA. Model XC6SLX150-3FG676 FPGA with 147,433 logic cells and 180 DSP48A1


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PDF XC6SLX150 XC5VLX30T 32-BIT 125MHZ 64-BIT LX30T
2005 - XC6SLX16-2

Abstract: XC6VLX75 DS335 XC6VLX75-1 3-bit binary multiplier using adder VERILOG DSP48A1 vhdl code for multiplication on spartan 6 verilog code for single precision floating point multiplication DSP48 floating point DSP48E1
Text: Speed Grade DSP48A1 (max usage) 2 100 97 94 192 DSP48A1 (full usage) 1 117 , Speed Grade DSP48A1 (max usage) 5 174 160 191 192 DSP48A1 (full usage) 4 193 169 232 244 DSP48A1 (medium usage) 1 495 488 545 233 Logic (no usage) 0


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PDF DS335 IEEE-754 XC6SLX16-2 XC6VLX75 XC6VLX75-1 3-bit binary multiplier using adder VERILOG DSP48A1 vhdl code for multiplication on spartan 6 verilog code for single precision floating point multiplication DSP48 floating point DSP48E1
2009 - XC6SLX

Abstract: XC6SL Spartan-6 LX45 UG382 XC6SLX25 ISERDES spartan 6 BUFIO2 DSP48A1 XC6SLX4 Spartan-6 FPGA LX9
Text: (CLBs) available in all Spartan-6 devices. · Spartan-6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples , X-Ref Target - Figure 1-2 CLB CLB CLB Block RAM (18 Kb) DSP48A1 Slices Block RAM (18 Kb) DSP48A1 Slices Block RAM (18 Kb) SelectIO Logic SelectIO Logic CLB SelectIO Logic CLB SelectIO Logic CLB CLB Block RAM (18 Kb) DSP48A1 Slices Block RAM (18


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PDF UG382 XC6SLX XC6SL Spartan-6 LX45 UG382 XC6SLX25 ISERDES spartan 6 BUFIO2 DSP48A1 XC6SLX4 Spartan-6 FPGA LX9
2009 - Not Available

Abstract: No abstract text available
Text: DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs , ) DSP48A1 Slices Block RAM (18 Kb) DSP48A1 Slices Block RAM (18 Kb) SelectIO Logic , ) DSP48A1 Slices Block RAM (18 Kb) DSP48A1 Slices Block RAM (18 Kb) SelectIO Logic , RAM (18 Kb) DSP48A1 Slices Block RAM (18 Kb) DSP48A1 Slices Block RAM (18 Kb , 16 CLB CLB Block RAM (18 Kb) DSP48A1 Slices Block RAM (18 Kb) DSP48A1 Slices


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PDF UG382
2009 - XC6slx45

Abstract: XC6SLX75 XC6SLX150 XC6SLX9 XC6SLX16 XC6SLX100 XC6SLX25 XC6slx4 XC6SLX75T xc6slx100t
Text: No file text available


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PDF DS162 XC6slx45 XC6SLX75 XC6SLX150 XC6SLX9 XC6SLX16 XC6SLX100 XC6SLX25 XC6slx4 XC6SLX75T xc6slx100t
2009 - XC6slx45

Abstract: XC6SLX25 xc6slx16 xc6slx9 XC6SLX25T xc6slx75 XC6SLX4 XC6SLX45T xilinx DDR3 controller user interface data sheet XC6SLX4 2 CSG225 I
Text: No file text available


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PDF DS162 XC6slx45 XC6SLX25 xc6slx16 xc6slx9 XC6SLX25T xc6slx75 XC6SLX4 XC6SLX45T xilinx DDR3 controller user interface data sheet XC6SLX4 2 CSG225 I
2009 - ug384

Abstract: CQ 346 vhdl code for spartan 6 ternary content addressable memory VHDL Spartan-6 FPGA xc6slx75 DPRAM XC6SLX16 SRL16 structure of clb
Text: This Guide · Spartan-6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples. · Spartan-6 FPGA


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PDF UG384 ug384 CQ 346 vhdl code for spartan 6 ternary content addressable memory VHDL Spartan-6 FPGA xc6slx75 DPRAM XC6SLX16 SRL16 structure of clb
2009 - xc6slx45 pinout

Abstract: XC6SLX45 XC6SLX75T DSP48A1 XC6SLX45T XC6SLX9-CSG225 CSG484 Spartan-6 FPGA DCM_CLKGEN xc6slx75fg xc6slx150t
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PDF DS162 xc6slx45 pinout XC6SLX45 XC6SLX75T DSP48A1 XC6SLX45T XC6SLX9-CSG225 CSG484 Spartan-6 FPGA DCM_CLKGEN xc6slx75fg xc6slx150t
2010 - camera-link to hd-SDI converter

Abstract: Virtex-4QV DS-KIT-FX12MM1-G AES-S6DEV-LX150T-G VHDL code for ADC and DAC SPI with FPGA spartan 3 ADQ0007 XC6SL AES-XLX-V4FX-PCIE100-G SPARTAN-3 XC3S400 based MXS3FK ADS-XLX-SP3-EVL400
Text: Controller Blocks Embedded Hard IP Resources 66 DSP48A1 Slices (5) 0 2 2 2 2 4 , as two independent 9Kb blocks. Each CMT contains two DCMs and one PLL. Each DSP48A1 slice contains


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2009 - RAMB16BWER

Abstract: DSP48A1 RAMB16 RAMB16BWE INIT20 verilog code for 16 kb ram 0104220 RAMB16B
Text: Guide · Spartan-6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples. · Spartan-6 FPGA Memory


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PDF UG383 RAMB16BWER DSP48A1 RAMB16 RAMB16BWE INIT20 verilog code for 16 kb ram 0104220 RAMB16B
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