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Part Manufacturer Description Datasheet Download Buy Part
DS90CR485VSX/NOPB Texas Instruments 133MHz LVDS 48-bit Channel Link Serializer 100-TQFP -10 to 70
DS90CR485VS/NOPB Texas Instruments 133MHz LVDS 48-bit Channel Link Serializer 100-TQFP -10 to 70

DS90CR485/6 Datasheets Context Search

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2003 - DS90CR482

Abstract: DS90CR483 DS90CR484 DS90CR485 DS90CR486 PRBS-15 termination sense
Text: ), (Figure 5) 0.5 TJCC Transmitter Jitter Cycle-to-Cycle (Note 6 ) ns ns f = 66 MHz , 7) TPDL ps Transmitter Phase Lock Loop Set (Figure 6 ) TPDD 70 45 PLL Bandwidth 66MHz TPLLS 40 f = 100 MHz BWPLL f = 133 MHz 600 ps kHz 10 ms 100 6 (TCIP , and Guaranteed By Design (GBD) using statistical analysis. Note 6 : The limits are based on bench , Diagrams (Continued) 20019553 FIGURE 5. Setup/Hold with CLKIN 20019519 FIGURE 6 . Phase Lock


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PDF DS90CR485 133MHz 48-bit DS90CR485 DS90CR482 DS90CR483 DS90CR484 DS90CR486 PRBS-15 termination sense
2003 - PRBS15

Abstract: No abstract text available
Text: the speed of 6.384Gbps. Please refer to datasheet for information on Chipsets 6 of 32 , RXOUT23 Pin 4 D23 Pin 4 RXOUT47 Pin 4 RXOUT22 Pin 6 D22 Pin 6 RXOUT46 Pin 6 RXOUT21 Pin 8 D21 Pin 8 RXOUT45 Pin 8 RXOUT20 Pin 10 D20 Pin 10 , Pin 6 CLK1P Pin 6 RxCLK1P Pin 7 GND Pin 7 GND Pin 8 GND Pin 8 GND , ENABLED PRBS-15 / PRBS23 TEST1 / HIGH TEST1 Pin 5 Pin 6 CON6 / HIGH CON6 Pin 6


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PDF DS90CR485/486 DS90CR485/486 48-bit, CLINK3V48BT-133 PRBS15
PRBS-15

Abstract: PRBS23 PRBS-23 PRBS15 DS90CR482 DS90CR483 DS90CR484 DS90CR485 DS90CR486
Text: ) Note 5: TSTC THTC CLKIN (GBD Guaranteed By Design) Note 6 , ( ) FIGURE 5. Setup/Hold with CLKIN FIGURE 6 . Phase Lock Loop Set Time (VCC 2.37V) FIGURE 7. Power , Latency www.national.com/jpn/ 6 I/O D0-D23 I 24 LVCMOS/LVTTL VCC3V , ) 14 NC VCC P 3 2.5V GND G 6 2.5V VCC3V P 1 , ) 1 0 7 6 - 1 1 7 6


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PDF DS90CR485 DS90CR486 DS90CR482 DS90CR484 DS90CR485 133MHz 384Gbps 66MHz 133MHz PRBS-15 PRBS23 PRBS-23 PRBS15 DS90CR482 DS90CR483 DS90CR484
VS100A

Abstract: AN1108 E1-D15 DS90CR481 DS90CR483 DS90CR484 DS90CR485 DS90CR486 E1-D13
Text: Receiver Powerdown Delay, (Figure 6 ) RSKMD Receiver Skew Margin with Deskew, BAL Low (Figure 7), (Note 6 ) f 133 MHz 275 ps f 100 MHz 400 ps f 66 MHz 500 Receiver Deskew , HIGH HIGH LOW (GBD Guaranteed By Design) Note 6 : (RSKMD) DESKEW , Propagation Delay - Latency FIGURE 5. DS90CR486 Phase Lock Loop Set Time (VCC 3.0V) FIGURE 6 . DS90CR486 , . Receiver Skew Margin with DESKEW (RSKMD) www.national.com/JPN/ 6 DS90CR486 LVDS FIGURE


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PDF 133MHz48 384Gbps) DS90CR486 133MHz 384Gbit/s 798MB/s) DS90CR486 DS90CR485 DS90CR481 DS90CR483 VS100A AN1108 E1-D15 DS90CR481 DS90CR483 DS90CR484 E1-D13
2003 - Not Available

Abstract: No abstract text available
Text: Bandwidth ≥ 66MHz TPLLS Transmitter Phase Lock Loop Set (Figure 6 ) 10 ms TPDD , ) 8(TCIP) ns (5) 4 600 6 (TCIP) 7(TCIP) kHz The limits are based on bench , €“ FEBRUARY 2003 – REVISED MARCH 2013 www.ti.com Figure 6 . Phase Lock Loop Set Time (VCC ≥ 2.37V , O 1 Negative LVDS differential clock output. (1) 6 Description Inputs default to , supply pins for core logic. GND G 6 Ground pins for 2.5V power supply. VCC3V P 1


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PDF DS90CR485 SNLS143D DS90CR485 133MHz 48-bit
2003 - tolerance j12

Abstract: LVDS 30 pin connector cable LVDS connector 30 pin MDR 26 pin LVDS connector 40 pins NAME connector 30 pin IDC MDR 68 pin configuration MDR 14 pin lvds connectors pin assignments CLINK3V485
Text: on Chipsets 6 of 32 DS90CR485/486 Evaluation Kit User Manual Rev. 1.01 Getting Started , D23 Pin 4 RXOUT47 Pin 4 RXOUT22 Pin 6 D22 Pin 6 RXOUT46 Pin 6 RXOUT21 , Pin 4 TxOUT1P Pin 4 RxOUT1P Pin 5 TxOUT2P Pin 5 RxOUT2P Pin 6 CLK1P Pin 6 RxCLK1P Pin 7 GND Pin 7 GND Pin 8 GND Pin 8 GND Pin 9 TxOUT3P , ENABLED PRBS-15 / PRBS23 TEST1 / HIGH TEST1 Pin 5 Pin 6 CON6 / HIGH CON6 Pin 6


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PDF DS90CR485/486 DS90CR485/486 48-bit, CLINK3V48BT-133 CLINK3V485/486 tolerance j12 LVDS 30 pin connector cable LVDS connector 30 pin MDR 26 pin LVDS connector 40 pins NAME connector 30 pin IDC MDR 68 pin configuration MDR 14 pin lvds connectors pin assignments CLINK3V485
2003 - mdr 68 pin configuration

Abstract: 94v0 c29 C0805C104K5RACTR MDR 68 pinout MDR 26 pin plug MDR 14 pin MDR 26 pin MINI D ribbon j6 con4 94v0 circuit board r29 Skewclear
Text: 6 of 32 DS90CR485/486 Evaluation Kit User Manual Rev. 1.0 Getting Started 7 of 32 , RXOUT23 Pin 4 D23 Pin 4 RXOUT47 Pin 4 RXOUT22 Pin 6 D22 Pin 6 RXOUT46 Pin 6 RXOUT21 Pin 8 D21 Pin 8 RXOUT45 Pin 8 RXOUT20 Pin 10 D20 Pin 10 , 6 CLK1P Pin 6 RxCLK1P Pin 7 GND Pin 7 GND Pin 8 GND Pin 8 GND , PRBS DISABLED / PRBS ENABLED PRBS-15 / PRBS23 TEST1 / HIGH TEST1 Pin 5 Pin 6 CON6 / HIGH


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PDF DS90CR485/486 DS90CR485/486 48-bit, CLINK3V48BT-133 TS-0755-05 mdr 68 pin configuration 94v0 c29 C0805C104K5RACTR MDR 68 pinout MDR 26 pin plug MDR 14 pin MDR 26 pin MINI D ribbon j6 con4 94v0 circuit board r29 Skewclear
2003 - A7p marking code

Abstract: No abstract text available
Text: TPDD TPDL (5) PLL Bandwidth 66MHz Transmitter Phase Lock Loop Set (Figure 6 ) Transmitter Powerdown Delay (Figure 7) Transmitter Input to Output Latency (Figure 8) 6 (TCIP) 7(TCIP) 8(TCIP) The , 2003 ­ REVISED MARCH 2013 www.ti.com Figure 6 . Phase Lock Loop Set Time (VCC 2.37V) Figure 7 , Pin Name D0-D23 CLKIN PD TxOUTP TxOUTM CLK1P CLK1M (1) 6 I/O I I I O O O O No. of Pins 24 1 1 8 8 1 1 , pins for LVDS outputs. P G P G P G P G 3 6 1 1 2 3 4 5 Inputs default to "low" when left open


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PDF DS90CR485 SNLS143D DS90CR485 133MHz 48-bit 66MHz 100-Pin TIA/EIA-644-A A7p marking code
2003 - PRBS-15

Abstract: No abstract text available
Text: ) Transmitter Jitter Cycle-to-Cycle (Note 6 ) f = 133 MHz f = 100 MHz f = 66 MHz BWPLL TPLLS TPDD TPDL PLL Bandwidth 66MHz Transmitter Phase Lock Loop Set (Figure 6 ) Transmitter Powerdown Delay (Figure 7) Transmitter Input to Output Latency (Figure 8) 6 (TCIP) 7(TCIP) -100 -150 -200 0.5 0.5 40 45 50 600 10 100 8 , and Guaranteed By Design (GBD) using statistical analysis. Note 6 : The limits are based on bench , 5. Setup/Hold with CLKIN 20019519 FIGURE 6 . Phase Lock Loop Set Time (VCC 2.37V) 20019521


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PDF DS90CR485 133MHz 48-bit PRBS-15
2003 - termination sense

Abstract: DS90CR482 DS90CR484 DS90CR485 DS90CR486 PRBS-15
Text: ), (Figure 5) 0.5 TJCC Transmitter Jitter Cycle-to-Cycle (Note 6 ) ns ns f = 66 MHz , 7) TPDL ps Transmitter Phase Lock Loop Set (Figure 6 ) TPDD 70 45 PLL Bandwidth 66MHz TPLLS 40 f = 100 MHz BWPLL f = 133 MHz 600 ps kHz 10 ms 100 6 (TCIP , and Guaranteed By Design (GBD) using statistical analysis. Note 6 : The limits are based on bench , Diagrams (Continued) 20019553 FIGURE 5. Setup/Hold with CLKIN 20019519 FIGURE 6 . Phase Lock


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PDF DS90CR485 133MHz 48-bit DS90CR485 termination sense DS90CR482 DS90CR484 DS90CR486 PRBS-15
2003 - Not Available

Abstract: No abstract text available
Text: Bandwidth ≥ 66MHz 600 ps kHz TPLLS Transmitter Phase Lock Loop Set (Figure 6 ) 10 ms , Latency (Figure 8) 8(TCIP) ns (5) 4 6 (TCIP) 7(TCIP) The limits are based on bench , €“ FEBRUARY 2003 – REVISED MARCH 2013 www.ti.com Figure 6 . Phase Lock Loop Set Time (VCC ≥ 2.37V , O 1 Negative LVDS differential clock output. (1) 6 Description Inputs default to , supply pins for core logic. GND G 6 Ground pins for 2.5V power supply. VCC3V P 1


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PDF DS90CR485 SNLS143D DS90CR485 133MHz 48-bit
2003 - DS90CR482

Abstract: DS90CR483 DS90CR484 DS90CR485 DS90CR486 PRBS-15 d13 e1
Text: ), (Figure 5) 0.5 TJCC Transmitter Jitter Cycle-to-Cycle (Note 6 ) ns ns f = 66 MHz , 7) TPDL ps Transmitter Phase Lock Loop Set (Figure 6 ) TPDD 70 45 PLL Bandwidth 66MHz TPLLS 40 f = 100 MHz BWPLL f = 133 MHz 600 ps kHz 10 ms 100 6 (TCIP , and Guaranteed By Design (GBD) using statistical analysis. Note 6 : The limits are based on bench , Diagrams (Continued) 20019553 FIGURE 5. Setup/Hold with CLKIN 20019519 FIGURE 6 . Phase Lock


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PDF DS90CR485 133MHz 48-bit DS90CR485 DS90CR482 DS90CR483 DS90CR484 DS90CR486 PRBS-15 d13 e1
2003 - Not Available

Abstract: No abstract text available
Text: , (Figure 6 ) 1 µs 4 f = 100 MHz 400 ps 500 f = 133 MHz −150 +150 ps â , €“ REVISED MARCH 2013 www.ti.com Figure 5. DS90CR486 Phase Lock Loop Set Time (VCC > 3.0V) Figure 6 , information. Figure 7. Receiver Skew Margin with DESKEW (RSKMD) 6 Submit Documentation Feedback , . This pin must be tied to logic High or Vcc. VCC I 6 Power supply pins for LVCMOS/LVTTL , LVDS inputs. 6 No Connect. Make NO Connection to these pins - leave open. NC 10 Submit


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PDF DS90CR486 SNLS149C DS90CR486 133MHz 48-Bit 66MHz 133MHz 100-pin
2003 - Not Available

Abstract: No abstract text available
Text: , (Figure 6 ) 1 µs 4 f = 100 MHz 400 ps 500 f = 133 MHz −150 +150 ps â , €“ REVISED MARCH 2013 www.ti.com Figure 5. DS90CR486 Phase Lock Loop Set Time (VCC > 3.0V) Figure 6 , information. Figure 7. Receiver Skew Margin with DESKEW (RSKMD) 6 Submit Documentation Feedback , . This pin must be tied to logic High or Vcc. VCC I 6 Power supply pins for LVCMOS/LVTTL , LVDS inputs. 6 No Connect. Make NO Connection to these pins - leave open. NC 10 Submit


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PDF DS90CR486 SNLS149C DS90CR486 133MHz 48-Bit 66MHz 133MHz 100-pin
2003 - SNLS143C

Abstract: No abstract text available
Text: ) Transmitter Jitter Cycle-to-Cycle (Note 6 ) f = 133 MHz f = 100 MHz f = 66 MHz BWPLL TPLLS TPDD TPDL PLL Bandwidth 66MHz Transmitter Phase Lock Loop Set (Figure 6 ) Transmitter Powerdown Delay (Figure 7) Transmitter Input to Output Latency (Figure 8) 6 (TCIP) 7(TCIP) -100 -150 -200 0.5 0.5 40 45 50 600 10 100 8 , and Guaranteed By Design (GBD) using statistical analysis. Note 6 : The limits are based on bench , 5. Setup/Hold with CLKIN 20019519 FIGURE 6 . Phase Lock Loop Set Time (VCC 2.37V) 20019521


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PDF DS90CR485 DS90CR485 133MHz 48-bit SNLS143C SNLS143C
2006 - 1108 D16

Abstract: DS90CR481 DS90CR483 DS90CR484 DS90CR485 DS90CR486
Text: Powerdown Delay, (Figure 6 ) RSKMD Receiver Skew Margin with Deskew, BAL=Low f = 133 MHz (Figure 7), (Note 6 ) f = 100 MHz 8.0 2(TCIP)+10 Receiver Phase Lock Loop Set ,(Figure 5) RPDD 6.0 2 , bench characterization and Guaranteed By Design (GBD) using statistical analysis. Note 6 : Receiver Skew , Time (VCC > 3.0V) 20025222 FIGURE 6 . DS90CR486 Power Down Delay 5 www.national.com , . FIGURE 7. Receiver Skew Margin with DESKEW (RSKMD) www.national.com 6 DS90CR486 LVDS


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PDF DS90CR486 133MHz 48-Bit DS90CR486 384Gbit/s 798Mbytes/s) 1108 D16 DS90CR481 DS90CR483 DS90CR484 DS90CR485
2003 - Not Available

Abstract: No abstract text available
Text: 5) 10 ms Receiver Powerdown Delay, (Figure 6 ) 1 µs 4 f = 100 MHz 400 ps , www.ti.com Figure 5. DS90CR486 Phase Lock Loop Set Time (VCC > 3.0V) Figure 6 . DS90CR486 Power Down , Margin with DESKEW (RSKMD) 6 Submit Documentation Feedback Copyright © 2003–2013, Texas , infomation. CON1 I 1 Control Pin. This pin must be tied to logic High or Vcc. VCC I 6 , inputs. LVDSGND I 3 Ground pins for LVDS inputs. 6 No Connect. Make NO Connection to


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PDF DS90CR486 SNLS149C DS90CR486 133MHz 48-Bit 66MHz 133MHz 100-pin
2003 - Not Available

Abstract: No abstract text available
Text: , (Figure 4) Receiver Phase Lock Loop Set ,(Figure 5) Receiver Powerdown Delay, (Figure 6 ) Receiver Skew , . DS90CR486 Phase Lock Loop Set Time (VCC > 3.0V) Figure 6 . DS90CR486 Power Down Delay C-Setup and Hold , transmitter datasheet for more information. Figure 7. Receiver Skew Margin with DESKEW (RSKMD) 6 , LVDSGND NC I I I I I I I 1 6 8 1 2 2 3 6 10 Submit Documentation Feedback Product Folder Links , . Initially, the running word disparity may be any value between +7 and - 6 . The running word disparity shall


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PDF DS90CR486 SNLS149C DS90CR486 133MHz 48-Bit 66MHz 100-pin
2007 - DS90UR801

Abstract: TSSOP56 80000B AN-1084 DS90CR48x DS90CR213MTD DS90CR218AMTD DS90CR216AMTD DS90CR215MTD DS90CR214MTD
Text: 2005 5 2 12 17 4 10 11 6 18 19 LVDS SerDes / (SerDes) DS90CR2xxx DS90CR4xx SerDes SerDes SerDes SerDes SerDes SerDes , DS90CR485/486 DS90CR481/482 DS90CR481/486 DS90CR485/ 6 112 MHz 6.38 Gbps DS90CR483 , /802 16 66 MHz 24:1 DS90C241/124 24:1 SCAN928028/6260 ( 6 ) 5 35 MHz DS90UR241/124 , "-" 6 3M MDR / / / (4 10mil) PCB RF RF 0.001 µF 0.1 µF


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PDF DS90CR2xxx DS90CR4xx DS90CR485/486 DS90CR481/482 DS90CR481/486 DS90CR485/6 DS90CR483/484 66MHz DS90CR481/482/483/484 DS90UR801 TSSOP56 80000B AN-1084 DS90CR48x DS90CR213MTD DS90CR218AMTD DS90CR216AMTD DS90CR215MTD DS90CR214MTD
2003 - LVDS 30 pin cable

Abstract: 1108 D16 DS90CR481 DS90CR483 DS90CR484 DS90CR485 DS90CR486
Text: , (Figure 6 ) RSKMD Receiver Skew Margin with Deskew, BAL=Low (Figure 7), (Note 6 ) f = 133 MHz , Guaranteed By Design (GBD) using statistical analysis. Note 6 : Receiver Skew Margin with Deskew (RSKMD) is , Time (VCC > 3.0V) 20025222 FIGURE 6 . DS90CR486 Power Down Delay 5 www.national.com , . Receiver Skew Margin with DESKEW (RSKMD) www.national.com 6 DS90CR486 133MHz LVDS 48-Bit Channel , infomation. CON1 I 1 Control Pin. This pin must be tied to logic High or Vcc. VCC I 6


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PDF DS90CR486 133MHz 48-Bit DS90CR486 384Gbit/s 798Mbytes/s) LVDS 30 pin cable 1108 D16 DS90CR481 DS90CR483 DS90CR484 DS90CR485
2006 - an1108

Abstract: reciver
Text: Latency, (Figure 4) Receiver Phase Lock Loop Set ,(Figure 5) Receiver Powerdown Delay, (Figure 6 ) Receiver Skew Margin with Deskew, BAL=Low f = 133 MHz (Figure 7), (Note 6 ) f = 100 MHz f = 66 MHz RDR Receiver , characterization and Guaranteed By Design (GBD) using statistical analysis. Note 6 : Receiver Skew Margin with , FIGURE 5. DS90CR486 Phase Lock Loop Set Time (VCC > 3.0V) 20025222 FIGURE 6 . DS90CR486 Power Down , (RSKMD) www.national.com 6 DS90CR486 LVDS Interface 20025204 FIGURE 8. 48 LVCMOS/LVTTL


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PDF DS90CR486 DS90CR486 133MHz 48-Bit SNLS149B an1108 reciver
2006 - Not Available

Abstract: No abstract text available
Text: Page 6 Pages 18 - 19 Channel Link LVDS SerDes “Virtual Ribbon Cable” Introduction National , DS90CR481/482, DS90CR481/486†, or DS90CR485/ 6 > 112 MHz • Extended temperature ranges Clock , 10:1 SCAN928028/6260 ( 6 Channels) Bus LVDS Embedded Clock SerDes 28:4 DS90CR48x


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PDF DS90CR215 DS90CR216A DS90CR217, DS90CR218A DS90CR285 DS90CR286A, DS90CR287 DS90CR288A DS90CR481, DS90CR482
lvds

Abstract: DS90LV032A DS90LV031A DS90LV001 DS90CR486 DS90CR485 DS90CP22M-8 DS90C032 DS90C031 NSID
Text: No file text available


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PDF DS90LV047A DS90LV048A LVDS47/48EVK 800Mbps DS90CP22M-8 LVDSCP22EVK DS90LV001 LVDS001EVK DS90C031 DS90C032 lvds DS90LV032A DS90LV031A DS90LV001 DS90CR486 DS90CR485 DS90CP22M-8 DS90C032 DS90C031 NSID
2006 - DS90CR287

Abstract: M600 AN-1109 DS90CR212
Text: National Semiconductor Channel Link Design Guide June 2006 Introduction Page 2 Chip Operation Pages 12 - 15 Design Guidelines Pages 4 - 10 Evaluation Kits Pages 11 Cables & Connectors Speed vs Cable Length Page 6 Pages 18 - 19 Channel Link LVDS SerDes "Virtual Ribbon Cable , 112 MHz DS90CR481/482, DS90CR481/486, or DS90CR485/ 6 > 112 MHz · Extended temperature , SCAN928028/6260 ( 6 Channels) Bus LVDS Embedded Clock SerDes 28:4 DS90CR48x DS92LV16 10:1


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PDF DS90CR2xx DS90CR4xx DS90CR287 M600 AN-1109 DS90CR212
2001 - tektronix 463

Abstract: LVDS-008 10G BERT AN-81 national Amphenol r2100 ROGERS4350 GETEK FR4 LVDSCP22EVK DS92LV18 633200
Text: . 5-14 6 : 6.1 , Semiconductor's LVDS Group LVDS 5. LVDS 6 . LVDS TTL TTL 1 LVDS LVDS TTL 21 28 48 4 , 30 50 Bus LVDS 10mA LVDS Bus LVDS 18 16 10 PLL LVDS PHY 6 CMOS (DS92CK16 , ) 100mil 3-4 National Semiconductor's LVDS Group 3. 4. 5. 90° ( ) 45° 6 , ( ) LVDS 1 ( 6 ) 3.2.5 EMI 1 ( 6 ) 3.2.6 EMC LVDS EMI (1) (2


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