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DS21Q41 datasheet (9)

Part Manufacturer Description Type PDF
DS21Q41AFP Dallas Semiconductor Quad T1 Controller Scan PDF
DS21Q41B Dallas Semiconductor Quad T1 Framer Original PDF
DS21Q41B Maxim Integrated Products Quad T1 Framer Original PDF
DS21Q41BN Dallas Semiconductor Quad T1 Framer Original PDF
DS21Q41BT Dallas Semiconductor Framer, T1 Standard Format, 128-TQFP Original PDF
DS21Q41BT+ Maxim Integrated Products Quad T1 Framer Original PDF
DS21Q41BTN Dallas Semiconductor Quad T1 Framer Original PDF
DS21Q41BTN Dallas Semiconductor Quad T1 Framer Original PDF
DS21Q41-BTN Maxim Integrated Products Framer, Quad T1 Framer Original PDF

DS21Q41 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
DS2141

Abstract:
Text:  DS21Q41 B DALLAS SEMICONDUCTOR DS21Q41B Quad T1 Framer FEATURES • FourTI DS1/ISDN-PRI , ) grade version available ( DS21Q41BTN ) DESCRIPTION The DS21Q41 B combines four of the popular DS2141A T1 , This Material Copyrighted By Its Respective Manufacturer DS21Q41 B 1.0 INTRODUCTION The DS21Q41B , , in the DS21Q41B. Several new features have been added to the framers in the DS21Q41B over the DS2141 , This Material Copyrighted By Its Respective Manufacturer DS21Q41 B DS21Q41B BLOCK DIAGRAM Figure 1-1


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PDF DS21Q41 DS21Q41B SLC-96 128-PIN g4011-000 DS2141 DS2141A DS21Q41B DS21Q41BTN TR-54016 TR54016 TR62411
1997 - and or

Abstract:
Text: DS21Q41 /Q43 APPLICATION NOTE PCM Interface, INTERFACING TO THE MC68MH360 QUICC32 OCTOBER 23, 1996 Interconnections between the DS21Q41 or DS21Q43 and the Motorola MC68MH360 (QUICC32) are shown in Figure 1. The , RCLK From LIU MC68MH360 QUICC32 DS21Q41 /Q43 RSERx RCLKx RSYNCx *RLINKx *RLCLKx L1RXDA , internal to the QUICC32). DS21Q41 /Q43 NOTES 1. 2. Other signals affecting operation of device are not , delays (0 - 3 clocks) to mask the F-Bit in T1 applications. RFSDA = 1 for DS21Q41 , 0 for DS21Q43 3


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PDF DS21Q41/Q43 MC68MH360 QUICC32 DS21Q41 DS21Q43 MC68MH360 QUICC32) QUICC32 and or hdlc MC68360 mc68360* motorola
DS2141A

Abstract:
Text: Maxim > App Notes > T/E Carrier and Packetized Keywords: DS21Q41 , DS21Q43, MC68360, QUICC32 , DS21Q41 , DS21Q43 Interfacing to the MC68MH360 QUICC32 Abstract: This application note contains , diagram. Interconnections between the DS21Q41 or DS21Q43 and the Motorola MC68MH360 (QUICC32) are shown , the port by the host processor (CPU32 internal to the QUICC32). DS21Q41 , DS21Q43 Notes: 1. Other , . RFSDA = 1 for DS21Q41 , 0 for DS21Q43. B. Set clock edges for transmit on rising edge and receive on


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PDF DS21Q41, DS21Q43, MC68360, QUICC32, DS21Q43 MC68MH360 QUICC32 MC68360 DS2141Q DS2141A DS2143 DS2143Q
Not Available

Abstract:
Text: DS21Q41 B DALLAS SEMICONDUCTOR DS21Q41B Quad T1 Framer FEATURES • FourTI DS1/ISDN-PRI framing , Electronic-Library Service CopyRight 2003 DS21Q41 B 1.0 INTRODUCTION The DS21Q41B Quad T1 Framer is made up of five , , software written for the DS2141A can also be used with only slight modifications, in the DS21Q41B. Several , Electronic-Library Service CopyRight 2003 DS21Q41 B DS21Q41B BLOCK DIAGRAM Figure 1-1 RPOSO/1/2/3 ■RCLKO/1/2/3 â , Service CopyRight 2003 DS21Q41 B DS21Q41B PIN DESCRIPTION Table 1-4 Transmit Clock [TCLK]. 1.544 MHz


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PDF DS21Q41 DS21Q41B SLC-96 f11111111 128-PIN G4011-000
DS2141A

Abstract:
Text: COMMUNICATIONS CIRCUITS May 08, 2001 App Note 320: DS21Q41 , DS21Q43 Interfacing to the MC68MH360 QUICC32 This application note contains information necessary to interface the Motorola MC68360 , information to complete a basic schematic diagram. Interconnections between the DS21Q41 or DS21Q43 and the , port by the host processor (CPU32 internal to the QUICC32). DS21Q41 , DS21Q43 Notes: 1. Other signals , . RFSDA = 1 for DS21Q41 , 0 for DS21Q43. B. Set clock edges for transmit on rising edge and receive on


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PDF DS21Q41, DS21Q43 MC68MH360 QUICC32 MC68360 DS2141Q DS2143Q DS2143Q DS2141A DS2143
AN302

Abstract:
Text: Maxim > App Notes > COMMUNICATIONS CIRCUITS Keywords: multiplex, backplane, framers, clock operation, T1 controller, single chip transceiver, SCT, E1 framer, T1 framer May 01, 2001 APPLICATION NOTE 302 DS2141, DS21Q41 , DS21Q43 8-MHz System Clock Operation Abstract: The application note , following: DS21Q41 quad T1 framer, DS21Q43 E1 framer, DS2141 T1 controller, DS2151 T1 single chip transceiver (SCT), and DS2153 E1 SCT. The DS2141, DS21Q41 , DS21Q43, DS2151and DS2153 PCM signals can


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PDF DS2141, DS21Q41, DS21Q43 192MHz DS21Q41 DS2141 DS2151 DS2153 AN302 AN-302 APP302
DS2141A

Abstract:
Text: Maxim > App Notes > COMMUNICATIONS CIRCUITS TELECOM Keywords: DS21Q41 , DS21Q43, MC68360 , NOTE 320 DS21Q41 , DS21Q43 Interfacing to the MC68MH360 QUICC32 Abstract: This application note , diagram. Interconnections between the DS21Q41 or DS21Q43 and the Motorola MC68MH360 (QUICC32) are shown , processor (CPU32 internal to the QUICC32). DS21Q41 , DS21Q43 Notes: 1. Other signals affecting operation , receive frame sync delays (0-3 clocks) to mask the F-Bit in T1 applications. RFSDA = 1 for DS21Q41 , 0 for


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PDF DS21Q41, DS21Q43, MC68360, QUICC32, DS21Q43 MC68MH360 QUICC32 MC68360 DS2141Q DS2141A DS2143 DS2143Q
1997 - Not Available

Abstract:
Text: DS2141/43/Q41/Q43 APPLICATION NOTE Programming, Initialization March 12, 1996 GENERAL INITIALIZATION FOR DS21Q41 , DS21Q43 After power-up, when supplies and clocks have stabilized, internal registers must be initialized. It is a good idea to clear, set to 00H, ALL R/W registers. Certain registers have , pins. These registers are; DS21Q41 : TEST, TCR2 DS21Q43: TEST1, TEST2 Depending on the , RSYSCLK pin ( DS21Q41 , DS21Q43) is tied high, registers can be initialized (written to), but not read


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PDF DS2141/43/Q41/Q43 DS21Q41, DS21Q43 DS21Q41: DS21Q43: DS21Q43 DS21Q43)
DS2141

Abstract:
Text: Application Note 301 8 MHz System Clock Operation www.dalsemi.com This application note applies to the following products. T1 Framers DS2141 DS21Q41 E1 Framers DS2143 DS21Q43 T1 SCT' s , used to switch to another active line. Figures 3 and 4 apply to the DS2141, DS21Q41 , DS2143, DS21Q43, DS2151 and DS2153. Figures 3 and 4 apply to the DS2141, DS21Q41 , DS2143, DS21Q43, DS2151 and DS2153. Figure 3: DS21Q41 /Q43 OR DS2141/43/51/53 #1 RSYSCLK0 TSYSCLK0 SYSCLK RSER0 RSER


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PDF DS2141 DS21Q41 DS2143 DS21Q43 DS2151 DS2152 DS2153 DS2154 192MHz DS2141 DS2143 DS2151 DS2152 DS2153 DS2154
DS2172

Abstract:
Text: Application Note 334 Bit Error Tester, Interfacing to the DS2141, DS2143, DS21Q41 , DS21Q43, DS2151, DS2152, DS2153, DS2154 The Circuit in Figure 1 describes a method of interfacing the DS2172 BERT to the Dallas Semiconductor family of T1/E1 Framers and Single Chip Transceivers. The receive side of the DS2172 can be connected directly to the receive data stream of the Framer / SCT. RCHBLK is connected to the Receive Disable (RDIS) pin. RCHBLK and TCHBLK outputs from the Framer / SCT are used to


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PDF DS2141, DS2143, DS21Q41, DS21Q43, DS2151, DS2152, DS2153, DS2154 DS2172 framer E1 DS2141 DS2143 DS2151 DS2152 DS2153 DS2154
multiplex

Abstract:
Text: COMMUNICATIONS CIRCUITS Application Note 430: May 01, 2001 App Note 302: DS2141, DS21Q41 , DS21Q43 8-MHz System Clock Operation The DS2141, DS21Q41 , DS21Q43, DS2151and DS2153 PCM signals can interface to an 8 MHz system backplane. Typically this application is used to multiplex four 2.048 MHz PCM streams onto a single 8 MHz PCM stream. To accomplish this the elastic stores are enabled and placed in the 2.048 MHz SYSCLK mode. Figure 1 describes a timing scheme in which a single RSYNC is generated


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PDF DS2141, DS21Q41, DS21Q43 DS21Q43, DS2151and DS2153 multiplex 2048MHZ DS2141
DS26521

Abstract:
Text: Maxim > App Notes > TELECOM Keywords: transparent operation, T1, E1 framers, transceivers, DS21Q41 , DS21Q42, DS21FF42, DS21FT42, DS21Q43, DS21Q44, DS21FF44, DS21FT44, DS2151, DS2152, DS2153, DS2154, DS21352, DS21354, DS21552, DS21554, DS2155, DS21Q55, DS2150, DS21Q50, DS21Q352, DS21Q354 Dec 05, 2001 , T1/E1/J1 T1 SCTs Framers E1 SCTs T1/E1 SCTs DS21Q41 DS21Q43 DS26401 DS2151 , Transparent Operation on DS2151, DS21Q41 Hardware Considerations: TSER and TLINK must be tied together


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PDF DS21Q41, DS21Q42, DS21FF42, DS21FT42, DS21Q43, DS21Q44, DS21FF44, DS21FT44, DS2151, DS2152, DS26521 DS21Q44 DS21Q42 DS21FT44 DS21FT42 DS21FF44 DS21FF42 DS2153 DS2152 DS2151
CCR15

Abstract:
Text: APPLICATION NOTE 336 Application Note 336 Transparent Operation Device Description www.dalsemi.com This application note applies to the following products. T1 Framers DS21Q41 DS21Q42 DS21FF42 DS21FT42 E1 Framers DS21Q43 DS21Q44 DS21FF44 DS21FT44 T1 SCT' s DS2151 DS2152 DS21352 DS21552 DS21Q352 DS21Q553 E1 SCT' s DS2153 DS2154 DS21354 DS21554 DS21Q354 DS21Q554 The , DS2154: Register configurations: DS2151 DS21Q41 : Hardware considerations: Register configurations


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PDF DS21Q41 DS21Q42 DS21FF42 DS21FT42 DS21Q43 DS21Q44 DS21FF44 DS21FT44 DS2151 DS2152 CCR15 TCR16 DS21Q42 DS21Q354 DS21FT44 DS21FT42 DS21FF44 DS21FF42 DS2152 DS2151
LCV14

Abstract:
Text: or multiframe boundaries for the DS21Q41B. Via TCR2.2, the DS21Q41B can be pro grammed to output , is enabled. A pulse at this pin will establish frame boundaries for the DS21Q41B. Should be tied low , DS21Q41 , please see Figure 12-9. 021997 13/55 DS21Q41B TCR2: TRANSMIT CONTROL REGISTER 2 , calculation, and the FDL bits are not looped back, they are reinserted by the DS21Q41B. When PLB is enabled , the DS21Q41B. When a loop up code has been received for 5 seconds, the CPE is expected to loop the


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PDF DS21Q41B SLC-96 DS21Q41B 128-P 128-PIN 56-G4011-000 LCV14 Rbl 69
DS2141

Abstract:
Text: following products: DS2141 DS21Q43 DS2153 DS21FF44 DS21552 DS2156 DS21Q41 DS21Q44 DS2154 , Features PART DS2151 DS2152 DS21352/552 DS21Q41 /Q42 DS21FF/FT42 NAME TEST, TCR2, LICR TEST1 , : T1/E1 Framer Initialization and Programming SPECIAL INITIALIZATION FOR DS21Q41 Transmit clock , TCR1.7. The following sequence should be used to initialize the DS21Q41 , in which TCLK is not present


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PDF DS2155, DS21Q55, DS2156 DS2141 DS21Q43 DS2153 DS21FF44 DS21552 DS2156 DS21Q41 DS2141 DS2153 DS2154 DS2155 DS21552 DS21FF44 DS21Q44 DS21Q55
wac-02

Abstract:
Text: 308 309 310 345 DS21Q41 QUAD T1 CONTROLLER 313 301 326 328 335 336 338 339 , DS21Q44 vs DS21Q43 357 DS21Q42 vs DS21Q41 360 DS21x52 vs DS2152 361 DS21x54 vs DS2154


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PDF DS2172 DS2141A DS21Q41 DS2152 DS2154 DS2151 DS2153 wac-02 DS21Q44 DS21Q42 DS2143 Bit Error Rate Tester
2002 - CCR15

Abstract:
Text: Application Note 336 Transparent Operation www.maxim-ic.com This application note applies to the following products. T1 FRAMERS DS21Q41 DS21Q42 DS21FF42 DS21FT42 E1 FRAMERS DS21Q43 DS21Q44 DS21FF44 DS21FT44 T1 SCTs DS2151 DS2152 DS21352 DS21552 DS21Q352 DS21Q553 E1 SCTs DS2153 DS2154 DS21354 DS21554 DS21Q354 DS21Q554 DS2150 DS21Q50 T1/E1 SCTs DS2155 DS21Q55 The Dallas Semiconductor framers can , Register Configurations: 3 of 4 AN336 DS2151, DS21Q41 Hardware Considerations: TSER and TLINK


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PDF DS21Q41 DS21Q42 DS21FF42 DS21FT42 DS21Q43 DS21Q44 DS21FF44 DS21FT44 DS2151 DS2152 CCR15
DS2151

Abstract:
Text: Application Note 336 Transparent Operation www.maxim-ic.com INTRODUCTION This application note applies to the following products. T1 FRAMERS E1 FRAMERS DS21Q41 DS21Q42 DS21FF42 DS21FT42 DS21Q43 DS21Q44 DS21FF44 DS21FT44 T1/E1/J1 FRAMERS DS26401 T1 SCTs DS2151 DS2152 DS21352 DS21552 DS21Q352 DS21Q552 E1 SCTs DS2153 DS2154 DS21354 DS21554 DS21Q354 DS21Q554 DS2150 , ON DS2151, DS21Q41 Hardware Considerations: Register Configurations: TSER and TLINK must be


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PDF DS21Q41 DS21Q42 DS21FF42 DS21FT42 DS21Q43 DS21Q44 DS21FF44 DS21FT44 DS26401 DS2151 DS2151 DS2152 DS21FF42 DS21FF44 DS21FT42 DS21FT44 DS21Q42 DS21Q44 DS26401
IC 351

Abstract:
Text: 316 354 323 355 324 360 325 370 336 382 335 2713 337 351 DS21Q41 QUAD T1 , DS21Q42 vs. DS21Q41 360 § DS21x52 vs. DS2152 361 § DS21x54 vs. DS2154 403 §


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PDF DS2172/DS21372 DS2141A DS21Q50 DS2155 DS2148, DS21348, DS21Q48, DS21Q348 DS21448 DS3150 IC 351 BSDL siemens DS21Q55 DS21Q42 DS2172 DS2152 DS2151 control IC 391
DS21Q43A

Abstract:
Text: Application Note 301 Legacy T1/E1 8MHz Backplane Operation www.maxim-ic.com INTRODUCTION This application note applies to the following products: T1 FRAMERS DS2141A DS21Q41B E1 FRAMERS DS2143 DS21Q43A T1 SCTs DS2151 DS2152 E1 SCTs DS2153 DS2154 This application note will discuss the requirements for multiplexing four PCM streams into one 8MHz system backplane using Dallas , line. Figures 3 and 4 apply to the DS2141, DS21Q41 , DS2143, DS21Q43, DS2151, and DS2153. DS21Q41


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PDF DS2141A DS21Q41B DS2143 DS21Q43A DS2151 DS2152 DS2153 DS2154 DS2155, DS21554, DS21Q43A DS21554 DS2155 DS2154 DS2153 DS2152 DS2151 DS2143 DS2141A DS21354
LQFP Package 128-pin

Abstract:
Text: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244-3292 (972) 371-4000 Date: October 28, 1999 Product Change Notice - K91001 Subject: Assembly Site Change ­ 100 and 128 Pin LQFP Description of Change: STATS in Singapore has been qualified as an alternate source for assembly of the 100 pin and 128 pin LQFP package. Devices Affected DS2152 DS2154 DS2196 DS21352 DS21354 DS21552 DS21554 DS21Q41 DS21Q42 DS21Q43 DS21Q44 DS80H10 DS80H11 Traceability


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PDF K91001 DS2152 DS2154 DS2196 DS21352 DS21354 DS21552 DS21554 DS21Q41 DS21Q42 LQFP Package 128-pin DS80H10 k9100 DS21Q42 DS2196 DS21554 DS21552 DS2154 DS2152 ON SEMICONDUCTOR TRACEABILITY
APP342

Abstract:
Text: , TCR2, LICR DS21Q41 /Q42 TEST, TCR2 DS21FF/FT42 TEST1, TCR2 DS2153 TEST1, TEST2, LICR , . Wait for SYSCLK to stabilize if elastic stores enabled Special Initialization for DS21Q41 Transmit , setting TCR1.7. The following sequence should be used to initialize the DS21Q41 , in which TCLK is not


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PDF DS2155, DS21Q55, DS2156 DS2154: DS21552: DS21554: DS21FF42: DS21FF44: DS21FT42: DS21FT44: APP342 DS2151 DS2152 DS2153 DS2154 DS2155 DS21Q55
rneg2

Abstract:
Text: DS21Q41AFP PRODUCT PREVIEW DALLAS SEMICONDUCTOR DS21Q41AFP Quad T1 Controller FEATURES • Quad T1 , 75 74 73 72 71 70 69 68 6766 65 1 64 2 O DS21Q41AFP 10 11 12 13 14 15 16 17 18 47 19 46 20 45 21 44 , " 0.95" DESCRIPTION The DS21Q41AFP Quad T1 Controller is a monolithic device which consists of four , available in the DS21Q41 AFP and the DS2141A data sheet serves to describe the quad device as well. Please , ICminer.com Electronic-Library Service CopyRight 2003 DS21Q41AFP DS21Q41AFP BLOCK DIAGRAM RPOS RCLK RNEG


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PDF DS21Q41AFP DS2141AT1 DS21Q43FP 80-pin DS2141A rneg2
rneg2

Abstract:
Text:  DS21Q41AFP PRODUCT PREVIEW DALLAS SEMICONDUCTOR DS21Q41AFP Quad T1 Controller FEATURES â , 78 77 76 75 74 73 72 71 70 69 68 6766 65 1 64 2 O DS21Q41AFP 10 11 12 13 14 15 16 17 18 47 , Footprint of 80-pin QFP 0.72" 0.95" DESCRIPTION The DS21Q41AFP Quad T1 Controller is a monolithic device , features of the DS2141A are available in the DS21Q41 AFP and the DS2141A data sheet serves to describe the , U.S.A. 030894 1/2 281 This Material Copyrighted By Its Respective Manufacturer DS21Q41AFP


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PDF DS21Q41AFP DS2141AT1 DS21Q43FP 80-pin DS21Q41AFP DS2141A rneg2
DS2141

Abstract:
Text: DS2141 DS2143 DS2151 DS2153 DS2156 DS21Q41 DS21Q43 DS2152 DS2154 DS2155


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PDF DS2141 DS2143 DS2151 DS215Data DS21Q42: DS21Q44: DS21Q552: DS21Q554: DS26518: DS26519: DS2141 DS21Q42 DS21Q354 DS21FT44 DS21FT42 DS21FF44 DS21FF42 DS2151 DS2143 DS21Q44
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